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This commit is contained in:
Hector Martin
207
channel/channelapp/stub/crt0.S
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207
channel/channelapp/stub/crt0.S
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// this file was taken from libogc, see http://www.devkitpro.org/
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#include "asm.h"
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#define _SDA_BASE_ 32768
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#define _SDA2_BASE_ 32768
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.text
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.section .init
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# crt0.s file for the GameCube V1.1 by Costis (costis@gbaemu.com)!
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#
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# Updates: Added support for clearing the BSS section so that global
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# variables are cleared to 0 upon start-up.
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#
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# This is start-up code for initializing the GameCube system and hardware
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# before executing the actual user program code. It clears the GPR's,
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# initializes the FPR's, initializes the Data, Code, and L2 caches, clears
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# and initializes SPR's, and disables exceptions (interrupts).
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#
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# Have fun!!! Please e-mail any suggestions or bugs to costis@gbaemu.com.
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# Entry Point
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.extern __PSInit
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.extern __SyscallInit
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.extern __CacheInit
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.extern __SystemInit
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.extern __sbss_start, __bss_end
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.extern __bat_config
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.extern _main
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.globl _start, __main
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_start:
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b startup
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.ascii "STUB"
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.ascii "HAXX"
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.long 0
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startup:
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# Disable interrupts first thing
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mfmsr r3
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rlwinm r4,r3,0,17,15
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rlwinm r4,r4,0,26,24
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mtmsr r4
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# Go into real mode
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isync
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lis r3,real@h
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ori r3,r3,real@l
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clrlwi r3,r3,2
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mtsrr0 r3
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mfmsr r3
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li r4,0x30
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andc r3,r3,r4
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mtsrr1 r3
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rfi
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real:
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# Set up the BATs the way we like them
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// HID0 = 00110c64:
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// bus checkstops off, sleep modes off,
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// caches off, caches invalidate,
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// store gathering off, enable data cache
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// flush assist, enable branch target cache,
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// enable branch history table
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lis 3,0x0011 ; ori 3,3,0x0c64 ; mtspr 1008,3 ; isync
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// MSR = 00002000 (FP on)
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li 4,0x2000 ; mtmsr 4
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// HID0 |= 0000c000 (caches on)
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ori 3,3,0xc000 ; mtspr 1008,3 ; isync
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// clear all BATs
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li 0,0
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mtspr 528,0 ; mtspr 530,0 ; mtspr 532,0 ; mtspr 534,0 // IBATU 0..3
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mtspr 536,0 ; mtspr 538,0 ; mtspr 540,0 ; mtspr 542,0 // DBATU 0..3
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mtspr 560,0 ; mtspr 562,0 ; mtspr 564,0 ; mtspr 566,0 // IBATU 4..7
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mtspr 568,0 ; mtspr 570,0 ; mtspr 572,0 ; mtspr 574,0 // DBATU 4..7
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isync
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// clear all SRs
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lis 0,0x8000
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mtsr 0,0 ; mtsr 1,0 ; mtsr 2,0 ; mtsr 3,0
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mtsr 4,0 ; mtsr 5,0 ; mtsr 6,0 ; mtsr 7,0
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mtsr 8,0 ; mtsr 9,0 ; mtsr 10,0 ; mtsr 11,0
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mtsr 12,0 ; mtsr 13,0 ; mtsr 14,0 ; mtsr 15,0
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isync
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// set [DI]BAT0 for 256MB@80000000,
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// real 00000000, WIMG=0000, R/W
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li 3,2 ; lis 4,0x8000 ; ori 4,4,0x1fff
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mtspr IBAT0L,3 ; mtspr IBAT0U,4 ; mtspr DBAT0L,3 ; mtspr DBAT0U,4 ; isync
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// set [DI]BAT4 for 256MB@90000000,
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// real 10000000, WIMG=0000, R/W
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addis 3,3,0x1000 ; addis 4,4,0x1000
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mtspr IBAT4L,3 ; mtspr IBAT4U,4 ; mtspr DBAT4L,3 ; mtspr DBAT4U,4 ; isync
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// set DBAT1 for 256MB@c0000000,
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// real 00000000, WIMG=0101, R/W
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li 3,0x2a ; lis 4,0xc000 ; ori 4,4,0x1fff
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mtspr DBAT1L,3 ; mtspr DBAT1U,4 ; isync
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// set DBAT5 for 256MB@d0000000,
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// real 10000000, WIMG=0101, R/W
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addis 3,3,0x1000 ; addis 4,4,0x1000
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mtspr DBAT5L,3 ; mtspr DBAT5U,4 ; isync
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// enable [DI]BAT4-7 in HID4
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lis 3, 0x8200
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mtspr 1011,3
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// set MSR[DR:IR] = 11, jump to _start
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lis 3,virtual@h ; ori 3,3, virtual@l ; mtsrr0 3
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mfmsr 3 ; ori 3,3,0x30 ; mtsrr1 3
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rfi
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virtual:
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bl InitGPRS # Initialize the General Purpose Registers
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bl __CacheInit # Initialize the system caches
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bl __SyscallInit # Initialize the System Call handler
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bl __SystemInit # Initialize more cache aspects, clear a few SPR's, and disable interrupts.
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# Clear the BSS section!
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lis r3,__sbss_start@h
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ori r3,r3,__sbss_start@l
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li r4,0
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lis r5,__bss_end@h
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ori r5,r5,__bss_end@l
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sub r5,r5,r3
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bl _memset
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bl _main # Branch to the user code!
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eloop:
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b eloop # If the main function returns, which should never happen then just loop endlessly.
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InitGPRS:
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# Clear all of the GPR's to 0
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li r0,0
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li r3,0
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li r4,0
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li r5,0
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li r6,0
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li r7,0
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li r8,0
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li r9,0
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li r10,0
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li r11,0
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li r12,0
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li r14,0
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li r15,0
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li r16,0
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li r17,0
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li r18,0
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li r19,0
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li r20,0
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li r21,0
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li r22,0
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li r23,0
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li r24,0
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li r25,0
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li r26,0
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li r27,0
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li r28,0
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li r29,0
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li r30,0
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li r31,0
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lis sp,__crt0stack@h # we take 0x8173FFF0 as the topmost starting point for our stack,this gives us ~128Kb Stack
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ori sp,sp,__crt0stack@l
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addi sp,sp,-4
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stw r0,0(sp)
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stwu sp,-56(sp)
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lis r2,_SDA2_BASE_@h
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ori r2,r2,_SDA2_BASE_@l # Set the Small Data 2 (Read Only) base register.
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lis r13,_SDA_BASE_@h
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ori r13,r13,_SDA_BASE_@l # Set the Small Data (Read\Write) base register.
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blr
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//r3 = ptr, r4 = fill, r5 = size
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.globl _memset
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_memset:
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clrlwi. r6,r5,29
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srwi r5,r5,2
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subi r3,r3,4
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mtctr r5
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1: stwu r4,4(r3)
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bdnz 1b
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cmplwi r6,0
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beq 3f
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2: stbu r4,1(r3)
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addic. r6,r6,-1
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bne+ 2b
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3: blr
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.section .bss
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.balign 8
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__crt0stack_end:
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.space 0x8000
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__crt0stack:
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