/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/*    Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */

/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */

/* Do not edit. */

/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */

#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM

enum {
	ARM_PHI = 0,
	ARM_INLINEASM = 1,
	ARM_INLINEASM_BR = 2,
	ARM_CFI_INSTRUCTION = 3,
	ARM_EH_LABEL = 4,
	ARM_GC_LABEL = 5,
	ARM_ANNOTATION_LABEL = 6,
	ARM_KILL = 7,
	ARM_EXTRACT_SUBREG = 8,
	ARM_INSERT_SUBREG = 9,
	ARM_IMPLICIT_DEF = 10,
	ARM_SUBREG_TO_REG = 11,
	ARM_COPY_TO_REGCLASS = 12,
	ARM_DBG_VALUE = 13,
	ARM_DBG_VALUE_LIST = 14,
	ARM_DBG_INSTR_REF = 15,
	ARM_DBG_PHI = 16,
	ARM_DBG_LABEL = 17,
	ARM_REG_SEQUENCE = 18,
	ARM_COPY = 19,
	ARM_BUNDLE = 20,
	ARM_LIFETIME_START = 21,
	ARM_LIFETIME_END = 22,
	ARM_PSEUDO_PROBE = 23,
	ARM_ARITH_FENCE = 24,
	ARM_STACKMAP = 25,
	ARM_FENTRY_CALL = 26,
	ARM_PATCHPOINT = 27,
	ARM_LOAD_STACK_GUARD = 28,
	ARM_PREALLOCATED_SETUP = 29,
	ARM_PREALLOCATED_ARG = 30,
	ARM_STATEPOINT = 31,
	ARM_LOCAL_ESCAPE = 32,
	ARM_FAULTING_OP = 33,
	ARM_PATCHABLE_OP = 34,
	ARM_PATCHABLE_FUNCTION_ENTER = 35,
	ARM_PATCHABLE_RET = 36,
	ARM_PATCHABLE_FUNCTION_EXIT = 37,
	ARM_PATCHABLE_TAIL_CALL = 38,
	ARM_PATCHABLE_EVENT_CALL = 39,
	ARM_PATCHABLE_TYPED_EVENT_CALL = 40,
	ARM_ICALL_BRANCH_FUNNEL = 41,
	ARM_MEMBARRIER = 42,
	ARM_G_ASSERT_SEXT = 43,
	ARM_G_ASSERT_ZEXT = 44,
	ARM_G_ASSERT_ALIGN = 45,
	ARM_G_ADD = 46,
	ARM_G_SUB = 47,
	ARM_G_MUL = 48,
	ARM_G_SDIV = 49,
	ARM_G_UDIV = 50,
	ARM_G_SREM = 51,
	ARM_G_UREM = 52,
	ARM_G_SDIVREM = 53,
	ARM_G_UDIVREM = 54,
	ARM_G_AND = 55,
	ARM_G_OR = 56,
	ARM_G_XOR = 57,
	ARM_G_IMPLICIT_DEF = 58,
	ARM_G_PHI = 59,
	ARM_G_FRAME_INDEX = 60,
	ARM_G_GLOBAL_VALUE = 61,
	ARM_G_EXTRACT = 62,
	ARM_G_UNMERGE_VALUES = 63,
	ARM_G_INSERT = 64,
	ARM_G_MERGE_VALUES = 65,
	ARM_G_BUILD_VECTOR = 66,
	ARM_G_BUILD_VECTOR_TRUNC = 67,
	ARM_G_CONCAT_VECTORS = 68,
	ARM_G_PTRTOINT = 69,
	ARM_G_INTTOPTR = 70,
	ARM_G_BITCAST = 71,
	ARM_G_FREEZE = 72,
	ARM_G_INTRINSIC_FPTRUNC_ROUND = 73,
	ARM_G_INTRINSIC_TRUNC = 74,
	ARM_G_INTRINSIC_ROUND = 75,
	ARM_G_INTRINSIC_LRINT = 76,
	ARM_G_INTRINSIC_ROUNDEVEN = 77,
	ARM_G_READCYCLECOUNTER = 78,
	ARM_G_LOAD = 79,
	ARM_G_SEXTLOAD = 80,
	ARM_G_ZEXTLOAD = 81,
	ARM_G_INDEXED_LOAD = 82,
	ARM_G_INDEXED_SEXTLOAD = 83,
	ARM_G_INDEXED_ZEXTLOAD = 84,
	ARM_G_STORE = 85,
	ARM_G_INDEXED_STORE = 86,
	ARM_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 87,
	ARM_G_ATOMIC_CMPXCHG = 88,
	ARM_G_ATOMICRMW_XCHG = 89,
	ARM_G_ATOMICRMW_ADD = 90,
	ARM_G_ATOMICRMW_SUB = 91,
	ARM_G_ATOMICRMW_AND = 92,
	ARM_G_ATOMICRMW_NAND = 93,
	ARM_G_ATOMICRMW_OR = 94,
	ARM_G_ATOMICRMW_XOR = 95,
	ARM_G_ATOMICRMW_MAX = 96,
	ARM_G_ATOMICRMW_MIN = 97,
	ARM_G_ATOMICRMW_UMAX = 98,
	ARM_G_ATOMICRMW_UMIN = 99,
	ARM_G_ATOMICRMW_FADD = 100,
	ARM_G_ATOMICRMW_FSUB = 101,
	ARM_G_ATOMICRMW_FMAX = 102,
	ARM_G_ATOMICRMW_FMIN = 103,
	ARM_G_ATOMICRMW_UINC_WRAP = 104,
	ARM_G_ATOMICRMW_UDEC_WRAP = 105,
	ARM_G_FENCE = 106,
	ARM_G_BRCOND = 107,
	ARM_G_BRINDIRECT = 108,
	ARM_G_INVOKE_REGION_START = 109,
	ARM_G_INTRINSIC = 110,
	ARM_G_INTRINSIC_W_SIDE_EFFECTS = 111,
	ARM_G_ANYEXT = 112,
	ARM_G_TRUNC = 113,
	ARM_G_CONSTANT = 114,
	ARM_G_FCONSTANT = 115,
	ARM_G_VASTART = 116,
	ARM_G_VAARG = 117,
	ARM_G_SEXT = 118,
	ARM_G_SEXT_INREG = 119,
	ARM_G_ZEXT = 120,
	ARM_G_SHL = 121,
	ARM_G_LSHR = 122,
	ARM_G_ASHR = 123,
	ARM_G_FSHL = 124,
	ARM_G_FSHR = 125,
	ARM_G_ROTR = 126,
	ARM_G_ROTL = 127,
	ARM_G_ICMP = 128,
	ARM_G_FCMP = 129,
	ARM_G_SELECT = 130,
	ARM_G_UADDO = 131,
	ARM_G_UADDE = 132,
	ARM_G_USUBO = 133,
	ARM_G_USUBE = 134,
	ARM_G_SADDO = 135,
	ARM_G_SADDE = 136,
	ARM_G_SSUBO = 137,
	ARM_G_SSUBE = 138,
	ARM_G_UMULO = 139,
	ARM_G_SMULO = 140,
	ARM_G_UMULH = 141,
	ARM_G_SMULH = 142,
	ARM_G_UADDSAT = 143,
	ARM_G_SADDSAT = 144,
	ARM_G_USUBSAT = 145,
	ARM_G_SSUBSAT = 146,
	ARM_G_USHLSAT = 147,
	ARM_G_SSHLSAT = 148,
	ARM_G_SMULFIX = 149,
	ARM_G_UMULFIX = 150,
	ARM_G_SMULFIXSAT = 151,
	ARM_G_UMULFIXSAT = 152,
	ARM_G_SDIVFIX = 153,
	ARM_G_UDIVFIX = 154,
	ARM_G_SDIVFIXSAT = 155,
	ARM_G_UDIVFIXSAT = 156,
	ARM_G_FADD = 157,
	ARM_G_FSUB = 158,
	ARM_G_FMUL = 159,
	ARM_G_FMA = 160,
	ARM_G_FMAD = 161,
	ARM_G_FDIV = 162,
	ARM_G_FREM = 163,
	ARM_G_FPOW = 164,
	ARM_G_FPOWI = 165,
	ARM_G_FEXP = 166,
	ARM_G_FEXP2 = 167,
	ARM_G_FLOG = 168,
	ARM_G_FLOG2 = 169,
	ARM_G_FLOG10 = 170,
	ARM_G_FNEG = 171,
	ARM_G_FPEXT = 172,
	ARM_G_FPTRUNC = 173,
	ARM_G_FPTOSI = 174,
	ARM_G_FPTOUI = 175,
	ARM_G_SITOFP = 176,
	ARM_G_UITOFP = 177,
	ARM_G_FABS = 178,
	ARM_G_FCOPYSIGN = 179,
	ARM_G_IS_FPCLASS = 180,
	ARM_G_FCANONICALIZE = 181,
	ARM_G_FMINNUM = 182,
	ARM_G_FMAXNUM = 183,
	ARM_G_FMINNUM_IEEE = 184,
	ARM_G_FMAXNUM_IEEE = 185,
	ARM_G_FMINIMUM = 186,
	ARM_G_FMAXIMUM = 187,
	ARM_G_PTR_ADD = 188,
	ARM_G_PTRMASK = 189,
	ARM_G_SMIN = 190,
	ARM_G_SMAX = 191,
	ARM_G_UMIN = 192,
	ARM_G_UMAX = 193,
	ARM_G_ABS = 194,
	ARM_G_LROUND = 195,
	ARM_G_LLROUND = 196,
	ARM_G_BR = 197,
	ARM_G_BRJT = 198,
	ARM_G_INSERT_VECTOR_ELT = 199,
	ARM_G_EXTRACT_VECTOR_ELT = 200,
	ARM_G_SHUFFLE_VECTOR = 201,
	ARM_G_CTTZ = 202,
	ARM_G_CTTZ_ZERO_UNDEF = 203,
	ARM_G_CTLZ = 204,
	ARM_G_CTLZ_ZERO_UNDEF = 205,
	ARM_G_CTPOP = 206,
	ARM_G_BSWAP = 207,
	ARM_G_BITREVERSE = 208,
	ARM_G_FCEIL = 209,
	ARM_G_FCOS = 210,
	ARM_G_FSIN = 211,
	ARM_G_FSQRT = 212,
	ARM_G_FFLOOR = 213,
	ARM_G_FRINT = 214,
	ARM_G_FNEARBYINT = 215,
	ARM_G_ADDRSPACE_CAST = 216,
	ARM_G_BLOCK_ADDR = 217,
	ARM_G_JUMP_TABLE = 218,
	ARM_G_DYN_STACKALLOC = 219,
	ARM_G_STRICT_FADD = 220,
	ARM_G_STRICT_FSUB = 221,
	ARM_G_STRICT_FMUL = 222,
	ARM_G_STRICT_FDIV = 223,
	ARM_G_STRICT_FREM = 224,
	ARM_G_STRICT_FMA = 225,
	ARM_G_STRICT_FSQRT = 226,
	ARM_G_READ_REGISTER = 227,
	ARM_G_WRITE_REGISTER = 228,
	ARM_G_MEMCPY = 229,
	ARM_G_MEMCPY_INLINE = 230,
	ARM_G_MEMMOVE = 231,
	ARM_G_MEMSET = 232,
	ARM_G_BZERO = 233,
	ARM_G_VECREDUCE_SEQ_FADD = 234,
	ARM_G_VECREDUCE_SEQ_FMUL = 235,
	ARM_G_VECREDUCE_FADD = 236,
	ARM_G_VECREDUCE_FMUL = 237,
	ARM_G_VECREDUCE_FMAX = 238,
	ARM_G_VECREDUCE_FMIN = 239,
	ARM_G_VECREDUCE_ADD = 240,
	ARM_G_VECREDUCE_MUL = 241,
	ARM_G_VECREDUCE_AND = 242,
	ARM_G_VECREDUCE_OR = 243,
	ARM_G_VECREDUCE_XOR = 244,
	ARM_G_VECREDUCE_SMAX = 245,
	ARM_G_VECREDUCE_SMIN = 246,
	ARM_G_VECREDUCE_UMAX = 247,
	ARM_G_VECREDUCE_UMIN = 248,
	ARM_G_SBFX = 249,
	ARM_G_UBFX = 250,
	ARM_ABS = 251,
	ARM_ADDSri = 252,
	ARM_ADDSrr = 253,
	ARM_ADDSrsi = 254,
	ARM_ADDSrsr = 255,
	ARM_ADJCALLSTACKDOWN = 256,
	ARM_ADJCALLSTACKUP = 257,
	ARM_ASRi = 258,
	ARM_ASRr = 259,
	ARM_B = 260,
	ARM_BCCZi64 = 261,
	ARM_BCCi64 = 262,
	ARM_BLX_noip = 263,
	ARM_BLX_pred_noip = 264,
	ARM_BL_PUSHLR = 265,
	ARM_BMOVPCB_CALL = 266,
	ARM_BMOVPCRX_CALL = 267,
	ARM_BR_JTadd = 268,
	ARM_BR_JTm_i12 = 269,
	ARM_BR_JTm_rs = 270,
	ARM_BR_JTr = 271,
	ARM_BX_CALL = 272,
	ARM_CMP_SWAP_16 = 273,
	ARM_CMP_SWAP_32 = 274,
	ARM_CMP_SWAP_64 = 275,
	ARM_CMP_SWAP_8 = 276,
	ARM_CONSTPOOL_ENTRY = 277,
	ARM_COPY_STRUCT_BYVAL_I32 = 278,
	ARM_ITasm = 279,
	ARM_Int_eh_sjlj_dispatchsetup = 280,
	ARM_Int_eh_sjlj_longjmp = 281,
	ARM_Int_eh_sjlj_setjmp = 282,
	ARM_Int_eh_sjlj_setjmp_nofp = 283,
	ARM_Int_eh_sjlj_setup_dispatch = 284,
	ARM_JUMPTABLE_ADDRS = 285,
	ARM_JUMPTABLE_INSTS = 286,
	ARM_JUMPTABLE_TBB = 287,
	ARM_JUMPTABLE_TBH = 288,
	ARM_LDMIA_RET = 289,
	ARM_LDRBT_POST = 290,
	ARM_LDRConstPool = 291,
	ARM_LDRHTii = 292,
	ARM_LDRLIT_ga_abs = 293,
	ARM_LDRLIT_ga_pcrel = 294,
	ARM_LDRLIT_ga_pcrel_ldr = 295,
	ARM_LDRSBTii = 296,
	ARM_LDRSHTii = 297,
	ARM_LDRT_POST = 298,
	ARM_LEApcrel = 299,
	ARM_LEApcrelJT = 300,
	ARM_LOADDUAL = 301,
	ARM_LSLi = 302,
	ARM_LSLr = 303,
	ARM_LSRi = 304,
	ARM_LSRr = 305,
	ARM_MEMCPY = 306,
	ARM_MLAv5 = 307,
	ARM_MOVCCi = 308,
	ARM_MOVCCi16 = 309,
	ARM_MOVCCi32imm = 310,
	ARM_MOVCCr = 311,
	ARM_MOVCCsi = 312,
	ARM_MOVCCsr = 313,
	ARM_MOVPCRX = 314,
	ARM_MOVTi16_ga_pcrel = 315,
	ARM_MOV_ga_pcrel = 316,
	ARM_MOV_ga_pcrel_ldr = 317,
	ARM_MOVi16_ga_pcrel = 318,
	ARM_MOVi32imm = 319,
	ARM_MOVsra_flag = 320,
	ARM_MOVsrl_flag = 321,
	ARM_MQPRCopy = 322,
	ARM_MQQPRLoad = 323,
	ARM_MQQPRStore = 324,
	ARM_MQQQQPRLoad = 325,
	ARM_MQQQQPRStore = 326,
	ARM_MULv5 = 327,
	ARM_MVE_MEMCPYLOOPINST = 328,
	ARM_MVE_MEMSETLOOPINST = 329,
	ARM_MVNCCi = 330,
	ARM_PICADD = 331,
	ARM_PICLDR = 332,
	ARM_PICLDRB = 333,
	ARM_PICLDRH = 334,
	ARM_PICLDRSB = 335,
	ARM_PICLDRSH = 336,
	ARM_PICSTR = 337,
	ARM_PICSTRB = 338,
	ARM_PICSTRH = 339,
	ARM_RORi = 340,
	ARM_RORr = 341,
	ARM_RRX = 342,
	ARM_RRXi = 343,
	ARM_RSBSri = 344,
	ARM_RSBSrsi = 345,
	ARM_RSBSrsr = 346,
	ARM_SEH_EpilogEnd = 347,
	ARM_SEH_EpilogStart = 348,
	ARM_SEH_Nop = 349,
	ARM_SEH_Nop_Ret = 350,
	ARM_SEH_PrologEnd = 351,
	ARM_SEH_SaveFRegs = 352,
	ARM_SEH_SaveLR = 353,
	ARM_SEH_SaveRegs = 354,
	ARM_SEH_SaveRegs_Ret = 355,
	ARM_SEH_SaveSP = 356,
	ARM_SEH_StackAlloc = 357,
	ARM_SMLALv5 = 358,
	ARM_SMULLv5 = 359,
	ARM_SPACE = 360,
	ARM_STOREDUAL = 361,
	ARM_STRBT_POST = 362,
	ARM_STRBi_preidx = 363,
	ARM_STRBr_preidx = 364,
	ARM_STRH_preidx = 365,
	ARM_STRT_POST = 366,
	ARM_STRi_preidx = 367,
	ARM_STRr_preidx = 368,
	ARM_SUBS_PC_LR = 369,
	ARM_SUBSri = 370,
	ARM_SUBSrr = 371,
	ARM_SUBSrsi = 372,
	ARM_SUBSrsr = 373,
	ARM_SpeculationBarrierISBDSBEndBB = 374,
	ARM_SpeculationBarrierSBEndBB = 375,
	ARM_TAILJMPd = 376,
	ARM_TAILJMPr = 377,
	ARM_TAILJMPr4 = 378,
	ARM_TCRETURNdi = 379,
	ARM_TCRETURNri = 380,
	ARM_TPsoft = 381,
	ARM_UMLALv5 = 382,
	ARM_UMULLv5 = 383,
	ARM_VLD1LNdAsm_16 = 384,
	ARM_VLD1LNdAsm_32 = 385,
	ARM_VLD1LNdAsm_8 = 386,
	ARM_VLD1LNdWB_fixed_Asm_16 = 387,
	ARM_VLD1LNdWB_fixed_Asm_32 = 388,
	ARM_VLD1LNdWB_fixed_Asm_8 = 389,
	ARM_VLD1LNdWB_register_Asm_16 = 390,
	ARM_VLD1LNdWB_register_Asm_32 = 391,
	ARM_VLD1LNdWB_register_Asm_8 = 392,
	ARM_VLD2LNdAsm_16 = 393,
	ARM_VLD2LNdAsm_32 = 394,
	ARM_VLD2LNdAsm_8 = 395,
	ARM_VLD2LNdWB_fixed_Asm_16 = 396,
	ARM_VLD2LNdWB_fixed_Asm_32 = 397,
	ARM_VLD2LNdWB_fixed_Asm_8 = 398,
	ARM_VLD2LNdWB_register_Asm_16 = 399,
	ARM_VLD2LNdWB_register_Asm_32 = 400,
	ARM_VLD2LNdWB_register_Asm_8 = 401,
	ARM_VLD2LNqAsm_16 = 402,
	ARM_VLD2LNqAsm_32 = 403,
	ARM_VLD2LNqWB_fixed_Asm_16 = 404,
	ARM_VLD2LNqWB_fixed_Asm_32 = 405,
	ARM_VLD2LNqWB_register_Asm_16 = 406,
	ARM_VLD2LNqWB_register_Asm_32 = 407,
	ARM_VLD3DUPdAsm_16 = 408,
	ARM_VLD3DUPdAsm_32 = 409,
	ARM_VLD3DUPdAsm_8 = 410,
	ARM_VLD3DUPdWB_fixed_Asm_16 = 411,
	ARM_VLD3DUPdWB_fixed_Asm_32 = 412,
	ARM_VLD3DUPdWB_fixed_Asm_8 = 413,
	ARM_VLD3DUPdWB_register_Asm_16 = 414,
	ARM_VLD3DUPdWB_register_Asm_32 = 415,
	ARM_VLD3DUPdWB_register_Asm_8 = 416,
	ARM_VLD3DUPqAsm_16 = 417,
	ARM_VLD3DUPqAsm_32 = 418,
	ARM_VLD3DUPqAsm_8 = 419,
	ARM_VLD3DUPqWB_fixed_Asm_16 = 420,
	ARM_VLD3DUPqWB_fixed_Asm_32 = 421,
	ARM_VLD3DUPqWB_fixed_Asm_8 = 422,
	ARM_VLD3DUPqWB_register_Asm_16 = 423,
	ARM_VLD3DUPqWB_register_Asm_32 = 424,
	ARM_VLD3DUPqWB_register_Asm_8 = 425,
	ARM_VLD3LNdAsm_16 = 426,
	ARM_VLD3LNdAsm_32 = 427,
	ARM_VLD3LNdAsm_8 = 428,
	ARM_VLD3LNdWB_fixed_Asm_16 = 429,
	ARM_VLD3LNdWB_fixed_Asm_32 = 430,
	ARM_VLD3LNdWB_fixed_Asm_8 = 431,
	ARM_VLD3LNdWB_register_Asm_16 = 432,
	ARM_VLD3LNdWB_register_Asm_32 = 433,
	ARM_VLD3LNdWB_register_Asm_8 = 434,
	ARM_VLD3LNqAsm_16 = 435,
	ARM_VLD3LNqAsm_32 = 436,
	ARM_VLD3LNqWB_fixed_Asm_16 = 437,
	ARM_VLD3LNqWB_fixed_Asm_32 = 438,
	ARM_VLD3LNqWB_register_Asm_16 = 439,
	ARM_VLD3LNqWB_register_Asm_32 = 440,
	ARM_VLD3dAsm_16 = 441,
	ARM_VLD3dAsm_32 = 442,
	ARM_VLD3dAsm_8 = 443,
	ARM_VLD3dWB_fixed_Asm_16 = 444,
	ARM_VLD3dWB_fixed_Asm_32 = 445,
	ARM_VLD3dWB_fixed_Asm_8 = 446,
	ARM_VLD3dWB_register_Asm_16 = 447,
	ARM_VLD3dWB_register_Asm_32 = 448,
	ARM_VLD3dWB_register_Asm_8 = 449,
	ARM_VLD3qAsm_16 = 450,
	ARM_VLD3qAsm_32 = 451,
	ARM_VLD3qAsm_8 = 452,
	ARM_VLD3qWB_fixed_Asm_16 = 453,
	ARM_VLD3qWB_fixed_Asm_32 = 454,
	ARM_VLD3qWB_fixed_Asm_8 = 455,
	ARM_VLD3qWB_register_Asm_16 = 456,
	ARM_VLD3qWB_register_Asm_32 = 457,
	ARM_VLD3qWB_register_Asm_8 = 458,
	ARM_VLD4DUPdAsm_16 = 459,
	ARM_VLD4DUPdAsm_32 = 460,
	ARM_VLD4DUPdAsm_8 = 461,
	ARM_VLD4DUPdWB_fixed_Asm_16 = 462,
	ARM_VLD4DUPdWB_fixed_Asm_32 = 463,
	ARM_VLD4DUPdWB_fixed_Asm_8 = 464,
	ARM_VLD4DUPdWB_register_Asm_16 = 465,
	ARM_VLD4DUPdWB_register_Asm_32 = 466,
	ARM_VLD4DUPdWB_register_Asm_8 = 467,
	ARM_VLD4DUPqAsm_16 = 468,
	ARM_VLD4DUPqAsm_32 = 469,
	ARM_VLD4DUPqAsm_8 = 470,
	ARM_VLD4DUPqWB_fixed_Asm_16 = 471,
	ARM_VLD4DUPqWB_fixed_Asm_32 = 472,
	ARM_VLD4DUPqWB_fixed_Asm_8 = 473,
	ARM_VLD4DUPqWB_register_Asm_16 = 474,
	ARM_VLD4DUPqWB_register_Asm_32 = 475,
	ARM_VLD4DUPqWB_register_Asm_8 = 476,
	ARM_VLD4LNdAsm_16 = 477,
	ARM_VLD4LNdAsm_32 = 478,
	ARM_VLD4LNdAsm_8 = 479,
	ARM_VLD4LNdWB_fixed_Asm_16 = 480,
	ARM_VLD4LNdWB_fixed_Asm_32 = 481,
	ARM_VLD4LNdWB_fixed_Asm_8 = 482,
	ARM_VLD4LNdWB_register_Asm_16 = 483,
	ARM_VLD4LNdWB_register_Asm_32 = 484,
	ARM_VLD4LNdWB_register_Asm_8 = 485,
	ARM_VLD4LNqAsm_16 = 486,
	ARM_VLD4LNqAsm_32 = 487,
	ARM_VLD4LNqWB_fixed_Asm_16 = 488,
	ARM_VLD4LNqWB_fixed_Asm_32 = 489,
	ARM_VLD4LNqWB_register_Asm_16 = 490,
	ARM_VLD4LNqWB_register_Asm_32 = 491,
	ARM_VLD4dAsm_16 = 492,
	ARM_VLD4dAsm_32 = 493,
	ARM_VLD4dAsm_8 = 494,
	ARM_VLD4dWB_fixed_Asm_16 = 495,
	ARM_VLD4dWB_fixed_Asm_32 = 496,
	ARM_VLD4dWB_fixed_Asm_8 = 497,
	ARM_VLD4dWB_register_Asm_16 = 498,
	ARM_VLD4dWB_register_Asm_32 = 499,
	ARM_VLD4dWB_register_Asm_8 = 500,
	ARM_VLD4qAsm_16 = 501,
	ARM_VLD4qAsm_32 = 502,
	ARM_VLD4qAsm_8 = 503,
	ARM_VLD4qWB_fixed_Asm_16 = 504,
	ARM_VLD4qWB_fixed_Asm_32 = 505,
	ARM_VLD4qWB_fixed_Asm_8 = 506,
	ARM_VLD4qWB_register_Asm_16 = 507,
	ARM_VLD4qWB_register_Asm_32 = 508,
	ARM_VLD4qWB_register_Asm_8 = 509,
	ARM_VMOVD0 = 510,
	ARM_VMOVDcc = 511,
	ARM_VMOVHcc = 512,
	ARM_VMOVQ0 = 513,
	ARM_VMOVScc = 514,
	ARM_VST1LNdAsm_16 = 515,
	ARM_VST1LNdAsm_32 = 516,
	ARM_VST1LNdAsm_8 = 517,
	ARM_VST1LNdWB_fixed_Asm_16 = 518,
	ARM_VST1LNdWB_fixed_Asm_32 = 519,
	ARM_VST1LNdWB_fixed_Asm_8 = 520,
	ARM_VST1LNdWB_register_Asm_16 = 521,
	ARM_VST1LNdWB_register_Asm_32 = 522,
	ARM_VST1LNdWB_register_Asm_8 = 523,
	ARM_VST2LNdAsm_16 = 524,
	ARM_VST2LNdAsm_32 = 525,
	ARM_VST2LNdAsm_8 = 526,
	ARM_VST2LNdWB_fixed_Asm_16 = 527,
	ARM_VST2LNdWB_fixed_Asm_32 = 528,
	ARM_VST2LNdWB_fixed_Asm_8 = 529,
	ARM_VST2LNdWB_register_Asm_16 = 530,
	ARM_VST2LNdWB_register_Asm_32 = 531,
	ARM_VST2LNdWB_register_Asm_8 = 532,
	ARM_VST2LNqAsm_16 = 533,
	ARM_VST2LNqAsm_32 = 534,
	ARM_VST2LNqWB_fixed_Asm_16 = 535,
	ARM_VST2LNqWB_fixed_Asm_32 = 536,
	ARM_VST2LNqWB_register_Asm_16 = 537,
	ARM_VST2LNqWB_register_Asm_32 = 538,
	ARM_VST3LNdAsm_16 = 539,
	ARM_VST3LNdAsm_32 = 540,
	ARM_VST3LNdAsm_8 = 541,
	ARM_VST3LNdWB_fixed_Asm_16 = 542,
	ARM_VST3LNdWB_fixed_Asm_32 = 543,
	ARM_VST3LNdWB_fixed_Asm_8 = 544,
	ARM_VST3LNdWB_register_Asm_16 = 545,
	ARM_VST3LNdWB_register_Asm_32 = 546,
	ARM_VST3LNdWB_register_Asm_8 = 547,
	ARM_VST3LNqAsm_16 = 548,
	ARM_VST3LNqAsm_32 = 549,
	ARM_VST3LNqWB_fixed_Asm_16 = 550,
	ARM_VST3LNqWB_fixed_Asm_32 = 551,
	ARM_VST3LNqWB_register_Asm_16 = 552,
	ARM_VST3LNqWB_register_Asm_32 = 553,
	ARM_VST3dAsm_16 = 554,
	ARM_VST3dAsm_32 = 555,
	ARM_VST3dAsm_8 = 556,
	ARM_VST3dWB_fixed_Asm_16 = 557,
	ARM_VST3dWB_fixed_Asm_32 = 558,
	ARM_VST3dWB_fixed_Asm_8 = 559,
	ARM_VST3dWB_register_Asm_16 = 560,
	ARM_VST3dWB_register_Asm_32 = 561,
	ARM_VST3dWB_register_Asm_8 = 562,
	ARM_VST3qAsm_16 = 563,
	ARM_VST3qAsm_32 = 564,
	ARM_VST3qAsm_8 = 565,
	ARM_VST3qWB_fixed_Asm_16 = 566,
	ARM_VST3qWB_fixed_Asm_32 = 567,
	ARM_VST3qWB_fixed_Asm_8 = 568,
	ARM_VST3qWB_register_Asm_16 = 569,
	ARM_VST3qWB_register_Asm_32 = 570,
	ARM_VST3qWB_register_Asm_8 = 571,
	ARM_VST4LNdAsm_16 = 572,
	ARM_VST4LNdAsm_32 = 573,
	ARM_VST4LNdAsm_8 = 574,
	ARM_VST4LNdWB_fixed_Asm_16 = 575,
	ARM_VST4LNdWB_fixed_Asm_32 = 576,
	ARM_VST4LNdWB_fixed_Asm_8 = 577,
	ARM_VST4LNdWB_register_Asm_16 = 578,
	ARM_VST4LNdWB_register_Asm_32 = 579,
	ARM_VST4LNdWB_register_Asm_8 = 580,
	ARM_VST4LNqAsm_16 = 581,
	ARM_VST4LNqAsm_32 = 582,
	ARM_VST4LNqWB_fixed_Asm_16 = 583,
	ARM_VST4LNqWB_fixed_Asm_32 = 584,
	ARM_VST4LNqWB_register_Asm_16 = 585,
	ARM_VST4LNqWB_register_Asm_32 = 586,
	ARM_VST4dAsm_16 = 587,
	ARM_VST4dAsm_32 = 588,
	ARM_VST4dAsm_8 = 589,
	ARM_VST4dWB_fixed_Asm_16 = 590,
	ARM_VST4dWB_fixed_Asm_32 = 591,
	ARM_VST4dWB_fixed_Asm_8 = 592,
	ARM_VST4dWB_register_Asm_16 = 593,
	ARM_VST4dWB_register_Asm_32 = 594,
	ARM_VST4dWB_register_Asm_8 = 595,
	ARM_VST4qAsm_16 = 596,
	ARM_VST4qAsm_32 = 597,
	ARM_VST4qAsm_8 = 598,
	ARM_VST4qWB_fixed_Asm_16 = 599,
	ARM_VST4qWB_fixed_Asm_32 = 600,
	ARM_VST4qWB_fixed_Asm_8 = 601,
	ARM_VST4qWB_register_Asm_16 = 602,
	ARM_VST4qWB_register_Asm_32 = 603,
	ARM_VST4qWB_register_Asm_8 = 604,
	ARM_WIN__CHKSTK = 605,
	ARM_WIN__DBZCHK = 606,
	ARM_t2ABS = 607,
	ARM_t2ADDSri = 608,
	ARM_t2ADDSrr = 609,
	ARM_t2ADDSrs = 610,
	ARM_t2BF_LabelPseudo = 611,
	ARM_t2BR_JT = 612,
	ARM_t2CALL_BTI = 613,
	ARM_t2DoLoopStart = 614,
	ARM_t2DoLoopStartTP = 615,
	ARM_t2LDMIA_RET = 616,
	ARM_t2LDRBpcrel = 617,
	ARM_t2LDRConstPool = 618,
	ARM_t2LDRHpcrel = 619,
	ARM_t2LDRLIT_ga_pcrel = 620,
	ARM_t2LDRSBpcrel = 621,
	ARM_t2LDRSHpcrel = 622,
	ARM_t2LDR_POST_imm = 623,
	ARM_t2LDR_PRE_imm = 624,
	ARM_t2LDRpci_pic = 625,
	ARM_t2LDRpcrel = 626,
	ARM_t2LEApcrel = 627,
	ARM_t2LEApcrelJT = 628,
	ARM_t2LoopDec = 629,
	ARM_t2LoopEnd = 630,
	ARM_t2LoopEndDec = 631,
	ARM_t2MOVCCasr = 632,
	ARM_t2MOVCCi = 633,
	ARM_t2MOVCCi16 = 634,
	ARM_t2MOVCCi32imm = 635,
	ARM_t2MOVCClsl = 636,
	ARM_t2MOVCClsr = 637,
	ARM_t2MOVCCr = 638,
	ARM_t2MOVCCror = 639,
	ARM_t2MOVSsi = 640,
	ARM_t2MOVSsr = 641,
	ARM_t2MOVTi16_ga_pcrel = 642,
	ARM_t2MOV_ga_pcrel = 643,
	ARM_t2MOVi16_ga_pcrel = 644,
	ARM_t2MOVi32imm = 645,
	ARM_t2MOVsi = 646,
	ARM_t2MOVsr = 647,
	ARM_t2MVNCCi = 648,
	ARM_t2RSBSri = 649,
	ARM_t2RSBSrs = 650,
	ARM_t2STRB_preidx = 651,
	ARM_t2STRH_preidx = 652,
	ARM_t2STR_POST_imm = 653,
	ARM_t2STR_PRE_imm = 654,
	ARM_t2STR_preidx = 655,
	ARM_t2SUBSri = 656,
	ARM_t2SUBSrr = 657,
	ARM_t2SUBSrs = 658,
	ARM_t2SpeculationBarrierISBDSBEndBB = 659,
	ARM_t2SpeculationBarrierSBEndBB = 660,
	ARM_t2TBB_JT = 661,
	ARM_t2TBH_JT = 662,
	ARM_t2WhileLoopSetup = 663,
	ARM_t2WhileLoopStart = 664,
	ARM_t2WhileLoopStartLR = 665,
	ARM_t2WhileLoopStartTP = 666,
	ARM_tADCS = 667,
	ARM_tADDSi3 = 668,
	ARM_tADDSi8 = 669,
	ARM_tADDSrr = 670,
	ARM_tADDframe = 671,
	ARM_tADJCALLSTACKDOWN = 672,
	ARM_tADJCALLSTACKUP = 673,
	ARM_tBLXNS_CALL = 674,
	ARM_tBLXr_noip = 675,
	ARM_tBL_PUSHLR = 676,
	ARM_tBRIND = 677,
	ARM_tBR_JTr = 678,
	ARM_tBXNS_RET = 679,
	ARM_tBX_CALL = 680,
	ARM_tBX_RET = 681,
	ARM_tBX_RET_vararg = 682,
	ARM_tBfar = 683,
	ARM_tCMP_SWAP_16 = 684,
	ARM_tCMP_SWAP_32 = 685,
	ARM_tCMP_SWAP_8 = 686,
	ARM_tLDMIA_UPD = 687,
	ARM_tLDRConstPool = 688,
	ARM_tLDRLIT_ga_abs = 689,
	ARM_tLDRLIT_ga_pcrel = 690,
	ARM_tLDR_postidx = 691,
	ARM_tLDRpci_pic = 692,
	ARM_tLEApcrel = 693,
	ARM_tLEApcrelJT = 694,
	ARM_tLSLSri = 695,
	ARM_tMOVCCr_pseudo = 696,
	ARM_tPOP_RET = 697,
	ARM_tRSBS = 698,
	ARM_tSBCS = 699,
	ARM_tSUBSi3 = 700,
	ARM_tSUBSi8 = 701,
	ARM_tSUBSrr = 702,
	ARM_tTAILJMPd = 703,
	ARM_tTAILJMPdND = 704,
	ARM_tTAILJMPr = 705,
	ARM_tTBB_JT = 706,
	ARM_tTBH_JT = 707,
	ARM_tTPsoft = 708,
	ARM_ADCri = 709,
	ARM_ADCrr = 710,
	ARM_ADCrsi = 711,
	ARM_ADCrsr = 712,
	ARM_ADDri = 713,
	ARM_ADDrr = 714,
	ARM_ADDrsi = 715,
	ARM_ADDrsr = 716,
	ARM_ADR = 717,
	ARM_AESD = 718,
	ARM_AESE = 719,
	ARM_AESIMC = 720,
	ARM_AESMC = 721,
	ARM_ANDri = 722,
	ARM_ANDrr = 723,
	ARM_ANDrsi = 724,
	ARM_ANDrsr = 725,
	ARM_BF16VDOTI_VDOTD = 726,
	ARM_BF16VDOTI_VDOTQ = 727,
	ARM_BF16VDOTS_VDOTD = 728,
	ARM_BF16VDOTS_VDOTQ = 729,
	ARM_BF16_VCVT = 730,
	ARM_BF16_VCVTB = 731,
	ARM_BF16_VCVTT = 732,
	ARM_BFC = 733,
	ARM_BFI = 734,
	ARM_BICri = 735,
	ARM_BICrr = 736,
	ARM_BICrsi = 737,
	ARM_BICrsr = 738,
	ARM_BKPT = 739,
	ARM_BL = 740,
	ARM_BLX = 741,
	ARM_BLX_pred = 742,
	ARM_BLXi = 743,
	ARM_BL_pred = 744,
	ARM_BX = 745,
	ARM_BXJ = 746,
	ARM_BX_RET = 747,
	ARM_BX_pred = 748,
	ARM_Bcc = 749,
	ARM_CDE_CX1 = 750,
	ARM_CDE_CX1A = 751,
	ARM_CDE_CX1D = 752,
	ARM_CDE_CX1DA = 753,
	ARM_CDE_CX2 = 754,
	ARM_CDE_CX2A = 755,
	ARM_CDE_CX2D = 756,
	ARM_CDE_CX2DA = 757,
	ARM_CDE_CX3 = 758,
	ARM_CDE_CX3A = 759,
	ARM_CDE_CX3D = 760,
	ARM_CDE_CX3DA = 761,
	ARM_CDE_VCX1A_fpdp = 762,
	ARM_CDE_VCX1A_fpsp = 763,
	ARM_CDE_VCX1A_vec = 764,
	ARM_CDE_VCX1_fpdp = 765,
	ARM_CDE_VCX1_fpsp = 766,
	ARM_CDE_VCX1_vec = 767,
	ARM_CDE_VCX2A_fpdp = 768,
	ARM_CDE_VCX2A_fpsp = 769,
	ARM_CDE_VCX2A_vec = 770,
	ARM_CDE_VCX2_fpdp = 771,
	ARM_CDE_VCX2_fpsp = 772,
	ARM_CDE_VCX2_vec = 773,
	ARM_CDE_VCX3A_fpdp = 774,
	ARM_CDE_VCX3A_fpsp = 775,
	ARM_CDE_VCX3A_vec = 776,
	ARM_CDE_VCX3_fpdp = 777,
	ARM_CDE_VCX3_fpsp = 778,
	ARM_CDE_VCX3_vec = 779,
	ARM_CDP = 780,
	ARM_CDP2 = 781,
	ARM_CLREX = 782,
	ARM_CLZ = 783,
	ARM_CMNri = 784,
	ARM_CMNzrr = 785,
	ARM_CMNzrsi = 786,
	ARM_CMNzrsr = 787,
	ARM_CMPri = 788,
	ARM_CMPrr = 789,
	ARM_CMPrsi = 790,
	ARM_CMPrsr = 791,
	ARM_CPS1p = 792,
	ARM_CPS2p = 793,
	ARM_CPS3p = 794,
	ARM_CRC32B = 795,
	ARM_CRC32CB = 796,
	ARM_CRC32CH = 797,
	ARM_CRC32CW = 798,
	ARM_CRC32H = 799,
	ARM_CRC32W = 800,
	ARM_DBG = 801,
	ARM_DMB = 802,
	ARM_DSB = 803,
	ARM_EORri = 804,
	ARM_EORrr = 805,
	ARM_EORrsi = 806,
	ARM_EORrsr = 807,
	ARM_ERET = 808,
	ARM_FCONSTD = 809,
	ARM_FCONSTH = 810,
	ARM_FCONSTS = 811,
	ARM_FLDMXDB_UPD = 812,
	ARM_FLDMXIA = 813,
	ARM_FLDMXIA_UPD = 814,
	ARM_FMSTAT = 815,
	ARM_FSTMXDB_UPD = 816,
	ARM_FSTMXIA = 817,
	ARM_FSTMXIA_UPD = 818,
	ARM_HINT = 819,
	ARM_HLT = 820,
	ARM_HVC = 821,
	ARM_ISB = 822,
	ARM_LDA = 823,
	ARM_LDAB = 824,
	ARM_LDAEX = 825,
	ARM_LDAEXB = 826,
	ARM_LDAEXD = 827,
	ARM_LDAEXH = 828,
	ARM_LDAH = 829,
	ARM_LDC2L_OFFSET = 830,
	ARM_LDC2L_OPTION = 831,
	ARM_LDC2L_POST = 832,
	ARM_LDC2L_PRE = 833,
	ARM_LDC2_OFFSET = 834,
	ARM_LDC2_OPTION = 835,
	ARM_LDC2_POST = 836,
	ARM_LDC2_PRE = 837,
	ARM_LDCL_OFFSET = 838,
	ARM_LDCL_OPTION = 839,
	ARM_LDCL_POST = 840,
	ARM_LDCL_PRE = 841,
	ARM_LDC_OFFSET = 842,
	ARM_LDC_OPTION = 843,
	ARM_LDC_POST = 844,
	ARM_LDC_PRE = 845,
	ARM_LDMDA = 846,
	ARM_LDMDA_UPD = 847,
	ARM_LDMDB = 848,
	ARM_LDMDB_UPD = 849,
	ARM_LDMIA = 850,
	ARM_LDMIA_UPD = 851,
	ARM_LDMIB = 852,
	ARM_LDMIB_UPD = 853,
	ARM_LDRBT_POST_IMM = 854,
	ARM_LDRBT_POST_REG = 855,
	ARM_LDRB_POST_IMM = 856,
	ARM_LDRB_POST_REG = 857,
	ARM_LDRB_PRE_IMM = 858,
	ARM_LDRB_PRE_REG = 859,
	ARM_LDRBi12 = 860,
	ARM_LDRBrs = 861,
	ARM_LDRD = 862,
	ARM_LDRD_POST = 863,
	ARM_LDRD_PRE = 864,
	ARM_LDREX = 865,
	ARM_LDREXB = 866,
	ARM_LDREXD = 867,
	ARM_LDREXH = 868,
	ARM_LDRH = 869,
	ARM_LDRHTi = 870,
	ARM_LDRHTr = 871,
	ARM_LDRH_POST = 872,
	ARM_LDRH_PRE = 873,
	ARM_LDRSB = 874,
	ARM_LDRSBTi = 875,
	ARM_LDRSBTr = 876,
	ARM_LDRSB_POST = 877,
	ARM_LDRSB_PRE = 878,
	ARM_LDRSH = 879,
	ARM_LDRSHTi = 880,
	ARM_LDRSHTr = 881,
	ARM_LDRSH_POST = 882,
	ARM_LDRSH_PRE = 883,
	ARM_LDRT_POST_IMM = 884,
	ARM_LDRT_POST_REG = 885,
	ARM_LDR_POST_IMM = 886,
	ARM_LDR_POST_REG = 887,
	ARM_LDR_PRE_IMM = 888,
	ARM_LDR_PRE_REG = 889,
	ARM_LDRcp = 890,
	ARM_LDRi12 = 891,
	ARM_LDRrs = 892,
	ARM_MCR = 893,
	ARM_MCR2 = 894,
	ARM_MCRR = 895,
	ARM_MCRR2 = 896,
	ARM_MLA = 897,
	ARM_MLS = 898,
	ARM_MOVPCLR = 899,
	ARM_MOVTi16 = 900,
	ARM_MOVi = 901,
	ARM_MOVi16 = 902,
	ARM_MOVr = 903,
	ARM_MOVr_TC = 904,
	ARM_MOVsi = 905,
	ARM_MOVsr = 906,
	ARM_MRC = 907,
	ARM_MRC2 = 908,
	ARM_MRRC = 909,
	ARM_MRRC2 = 910,
	ARM_MRS = 911,
	ARM_MRSbanked = 912,
	ARM_MRSsys = 913,
	ARM_MSR = 914,
	ARM_MSRbanked = 915,
	ARM_MSRi = 916,
	ARM_MUL = 917,
	ARM_MVE_ASRLi = 918,
	ARM_MVE_ASRLr = 919,
	ARM_MVE_DLSTP_16 = 920,
	ARM_MVE_DLSTP_32 = 921,
	ARM_MVE_DLSTP_64 = 922,
	ARM_MVE_DLSTP_8 = 923,
	ARM_MVE_LCTP = 924,
	ARM_MVE_LETP = 925,
	ARM_MVE_LSLLi = 926,
	ARM_MVE_LSLLr = 927,
	ARM_MVE_LSRL = 928,
	ARM_MVE_SQRSHR = 929,
	ARM_MVE_SQRSHRL = 930,
	ARM_MVE_SQSHL = 931,
	ARM_MVE_SQSHLL = 932,
	ARM_MVE_SRSHR = 933,
	ARM_MVE_SRSHRL = 934,
	ARM_MVE_UQRSHL = 935,
	ARM_MVE_UQRSHLL = 936,
	ARM_MVE_UQSHL = 937,
	ARM_MVE_UQSHLL = 938,
	ARM_MVE_URSHR = 939,
	ARM_MVE_URSHRL = 940,
	ARM_MVE_VABAVs16 = 941,
	ARM_MVE_VABAVs32 = 942,
	ARM_MVE_VABAVs8 = 943,
	ARM_MVE_VABAVu16 = 944,
	ARM_MVE_VABAVu32 = 945,
	ARM_MVE_VABAVu8 = 946,
	ARM_MVE_VABDf16 = 947,
	ARM_MVE_VABDf32 = 948,
	ARM_MVE_VABDs16 = 949,
	ARM_MVE_VABDs32 = 950,
	ARM_MVE_VABDs8 = 951,
	ARM_MVE_VABDu16 = 952,
	ARM_MVE_VABDu32 = 953,
	ARM_MVE_VABDu8 = 954,
	ARM_MVE_VABSf16 = 955,
	ARM_MVE_VABSf32 = 956,
	ARM_MVE_VABSs16 = 957,
	ARM_MVE_VABSs32 = 958,
	ARM_MVE_VABSs8 = 959,
	ARM_MVE_VADC = 960,
	ARM_MVE_VADCI = 961,
	ARM_MVE_VADDLVs32acc = 962,
	ARM_MVE_VADDLVs32no_acc = 963,
	ARM_MVE_VADDLVu32acc = 964,
	ARM_MVE_VADDLVu32no_acc = 965,
	ARM_MVE_VADDVs16acc = 966,
	ARM_MVE_VADDVs16no_acc = 967,
	ARM_MVE_VADDVs32acc = 968,
	ARM_MVE_VADDVs32no_acc = 969,
	ARM_MVE_VADDVs8acc = 970,
	ARM_MVE_VADDVs8no_acc = 971,
	ARM_MVE_VADDVu16acc = 972,
	ARM_MVE_VADDVu16no_acc = 973,
	ARM_MVE_VADDVu32acc = 974,
	ARM_MVE_VADDVu32no_acc = 975,
	ARM_MVE_VADDVu8acc = 976,
	ARM_MVE_VADDVu8no_acc = 977,
	ARM_MVE_VADD_qr_f16 = 978,
	ARM_MVE_VADD_qr_f32 = 979,
	ARM_MVE_VADD_qr_i16 = 980,
	ARM_MVE_VADD_qr_i32 = 981,
	ARM_MVE_VADD_qr_i8 = 982,
	ARM_MVE_VADDf16 = 983,
	ARM_MVE_VADDf32 = 984,
	ARM_MVE_VADDi16 = 985,
	ARM_MVE_VADDi32 = 986,
	ARM_MVE_VADDi8 = 987,
	ARM_MVE_VAND = 988,
	ARM_MVE_VBIC = 989,
	ARM_MVE_VBICimmi16 = 990,
	ARM_MVE_VBICimmi32 = 991,
	ARM_MVE_VBRSR16 = 992,
	ARM_MVE_VBRSR32 = 993,
	ARM_MVE_VBRSR8 = 994,
	ARM_MVE_VCADDf16 = 995,
	ARM_MVE_VCADDf32 = 996,
	ARM_MVE_VCADDi16 = 997,
	ARM_MVE_VCADDi32 = 998,
	ARM_MVE_VCADDi8 = 999,
	ARM_MVE_VCLSs16 = 1000,
	ARM_MVE_VCLSs32 = 1001,
	ARM_MVE_VCLSs8 = 1002,
	ARM_MVE_VCLZs16 = 1003,
	ARM_MVE_VCLZs32 = 1004,
	ARM_MVE_VCLZs8 = 1005,
	ARM_MVE_VCMLAf16 = 1006,
	ARM_MVE_VCMLAf32 = 1007,
	ARM_MVE_VCMPf16 = 1008,
	ARM_MVE_VCMPf16r = 1009,
	ARM_MVE_VCMPf32 = 1010,
	ARM_MVE_VCMPf32r = 1011,
	ARM_MVE_VCMPi16 = 1012,
	ARM_MVE_VCMPi16r = 1013,
	ARM_MVE_VCMPi32 = 1014,
	ARM_MVE_VCMPi32r = 1015,
	ARM_MVE_VCMPi8 = 1016,
	ARM_MVE_VCMPi8r = 1017,
	ARM_MVE_VCMPs16 = 1018,
	ARM_MVE_VCMPs16r = 1019,
	ARM_MVE_VCMPs32 = 1020,
	ARM_MVE_VCMPs32r = 1021,
	ARM_MVE_VCMPs8 = 1022,
	ARM_MVE_VCMPs8r = 1023,
	ARM_MVE_VCMPu16 = 1024,
	ARM_MVE_VCMPu16r = 1025,
	ARM_MVE_VCMPu32 = 1026,
	ARM_MVE_VCMPu32r = 1027,
	ARM_MVE_VCMPu8 = 1028,
	ARM_MVE_VCMPu8r = 1029,
	ARM_MVE_VCMULf16 = 1030,
	ARM_MVE_VCMULf32 = 1031,
	ARM_MVE_VCTP16 = 1032,
	ARM_MVE_VCTP32 = 1033,
	ARM_MVE_VCTP64 = 1034,
	ARM_MVE_VCTP8 = 1035,
	ARM_MVE_VCVTf16f32bh = 1036,
	ARM_MVE_VCVTf16f32th = 1037,
	ARM_MVE_VCVTf16s16_fix = 1038,
	ARM_MVE_VCVTf16s16n = 1039,
	ARM_MVE_VCVTf16u16_fix = 1040,
	ARM_MVE_VCVTf16u16n = 1041,
	ARM_MVE_VCVTf32f16bh = 1042,
	ARM_MVE_VCVTf32f16th = 1043,
	ARM_MVE_VCVTf32s32_fix = 1044,
	ARM_MVE_VCVTf32s32n = 1045,
	ARM_MVE_VCVTf32u32_fix = 1046,
	ARM_MVE_VCVTf32u32n = 1047,
	ARM_MVE_VCVTs16f16_fix = 1048,
	ARM_MVE_VCVTs16f16a = 1049,
	ARM_MVE_VCVTs16f16m = 1050,
	ARM_MVE_VCVTs16f16n = 1051,
	ARM_MVE_VCVTs16f16p = 1052,
	ARM_MVE_VCVTs16f16z = 1053,
	ARM_MVE_VCVTs32f32_fix = 1054,
	ARM_MVE_VCVTs32f32a = 1055,
	ARM_MVE_VCVTs32f32m = 1056,
	ARM_MVE_VCVTs32f32n = 1057,
	ARM_MVE_VCVTs32f32p = 1058,
	ARM_MVE_VCVTs32f32z = 1059,
	ARM_MVE_VCVTu16f16_fix = 1060,
	ARM_MVE_VCVTu16f16a = 1061,
	ARM_MVE_VCVTu16f16m = 1062,
	ARM_MVE_VCVTu16f16n = 1063,
	ARM_MVE_VCVTu16f16p = 1064,
	ARM_MVE_VCVTu16f16z = 1065,
	ARM_MVE_VCVTu32f32_fix = 1066,
	ARM_MVE_VCVTu32f32a = 1067,
	ARM_MVE_VCVTu32f32m = 1068,
	ARM_MVE_VCVTu32f32n = 1069,
	ARM_MVE_VCVTu32f32p = 1070,
	ARM_MVE_VCVTu32f32z = 1071,
	ARM_MVE_VDDUPu16 = 1072,
	ARM_MVE_VDDUPu32 = 1073,
	ARM_MVE_VDDUPu8 = 1074,
	ARM_MVE_VDUP16 = 1075,
	ARM_MVE_VDUP32 = 1076,
	ARM_MVE_VDUP8 = 1077,
	ARM_MVE_VDWDUPu16 = 1078,
	ARM_MVE_VDWDUPu32 = 1079,
	ARM_MVE_VDWDUPu8 = 1080,
	ARM_MVE_VEOR = 1081,
	ARM_MVE_VFMA_qr_Sf16 = 1082,
	ARM_MVE_VFMA_qr_Sf32 = 1083,
	ARM_MVE_VFMA_qr_f16 = 1084,
	ARM_MVE_VFMA_qr_f32 = 1085,
	ARM_MVE_VFMAf16 = 1086,
	ARM_MVE_VFMAf32 = 1087,
	ARM_MVE_VFMSf16 = 1088,
	ARM_MVE_VFMSf32 = 1089,
	ARM_MVE_VHADD_qr_s16 = 1090,
	ARM_MVE_VHADD_qr_s32 = 1091,
	ARM_MVE_VHADD_qr_s8 = 1092,
	ARM_MVE_VHADD_qr_u16 = 1093,
	ARM_MVE_VHADD_qr_u32 = 1094,
	ARM_MVE_VHADD_qr_u8 = 1095,
	ARM_MVE_VHADDs16 = 1096,
	ARM_MVE_VHADDs32 = 1097,
	ARM_MVE_VHADDs8 = 1098,
	ARM_MVE_VHADDu16 = 1099,
	ARM_MVE_VHADDu32 = 1100,
	ARM_MVE_VHADDu8 = 1101,
	ARM_MVE_VHCADDs16 = 1102,
	ARM_MVE_VHCADDs32 = 1103,
	ARM_MVE_VHCADDs8 = 1104,
	ARM_MVE_VHSUB_qr_s16 = 1105,
	ARM_MVE_VHSUB_qr_s32 = 1106,
	ARM_MVE_VHSUB_qr_s8 = 1107,
	ARM_MVE_VHSUB_qr_u16 = 1108,
	ARM_MVE_VHSUB_qr_u32 = 1109,
	ARM_MVE_VHSUB_qr_u8 = 1110,
	ARM_MVE_VHSUBs16 = 1111,
	ARM_MVE_VHSUBs32 = 1112,
	ARM_MVE_VHSUBs8 = 1113,
	ARM_MVE_VHSUBu16 = 1114,
	ARM_MVE_VHSUBu32 = 1115,
	ARM_MVE_VHSUBu8 = 1116,
	ARM_MVE_VIDUPu16 = 1117,
	ARM_MVE_VIDUPu32 = 1118,
	ARM_MVE_VIDUPu8 = 1119,
	ARM_MVE_VIWDUPu16 = 1120,
	ARM_MVE_VIWDUPu32 = 1121,
	ARM_MVE_VIWDUPu8 = 1122,
	ARM_MVE_VLD20_16 = 1123,
	ARM_MVE_VLD20_16_wb = 1124,
	ARM_MVE_VLD20_32 = 1125,
	ARM_MVE_VLD20_32_wb = 1126,
	ARM_MVE_VLD20_8 = 1127,
	ARM_MVE_VLD20_8_wb = 1128,
	ARM_MVE_VLD21_16 = 1129,
	ARM_MVE_VLD21_16_wb = 1130,
	ARM_MVE_VLD21_32 = 1131,
	ARM_MVE_VLD21_32_wb = 1132,
	ARM_MVE_VLD21_8 = 1133,
	ARM_MVE_VLD21_8_wb = 1134,
	ARM_MVE_VLD40_16 = 1135,
	ARM_MVE_VLD40_16_wb = 1136,
	ARM_MVE_VLD40_32 = 1137,
	ARM_MVE_VLD40_32_wb = 1138,
	ARM_MVE_VLD40_8 = 1139,
	ARM_MVE_VLD40_8_wb = 1140,
	ARM_MVE_VLD41_16 = 1141,
	ARM_MVE_VLD41_16_wb = 1142,
	ARM_MVE_VLD41_32 = 1143,
	ARM_MVE_VLD41_32_wb = 1144,
	ARM_MVE_VLD41_8 = 1145,
	ARM_MVE_VLD41_8_wb = 1146,
	ARM_MVE_VLD42_16 = 1147,
	ARM_MVE_VLD42_16_wb = 1148,
	ARM_MVE_VLD42_32 = 1149,
	ARM_MVE_VLD42_32_wb = 1150,
	ARM_MVE_VLD42_8 = 1151,
	ARM_MVE_VLD42_8_wb = 1152,
	ARM_MVE_VLD43_16 = 1153,
	ARM_MVE_VLD43_16_wb = 1154,
	ARM_MVE_VLD43_32 = 1155,
	ARM_MVE_VLD43_32_wb = 1156,
	ARM_MVE_VLD43_8 = 1157,
	ARM_MVE_VLD43_8_wb = 1158,
	ARM_MVE_VLDRBS16 = 1159,
	ARM_MVE_VLDRBS16_post = 1160,
	ARM_MVE_VLDRBS16_pre = 1161,
	ARM_MVE_VLDRBS16_rq = 1162,
	ARM_MVE_VLDRBS32 = 1163,
	ARM_MVE_VLDRBS32_post = 1164,
	ARM_MVE_VLDRBS32_pre = 1165,
	ARM_MVE_VLDRBS32_rq = 1166,
	ARM_MVE_VLDRBU16 = 1167,
	ARM_MVE_VLDRBU16_post = 1168,
	ARM_MVE_VLDRBU16_pre = 1169,
	ARM_MVE_VLDRBU16_rq = 1170,
	ARM_MVE_VLDRBU32 = 1171,
	ARM_MVE_VLDRBU32_post = 1172,
	ARM_MVE_VLDRBU32_pre = 1173,
	ARM_MVE_VLDRBU32_rq = 1174,
	ARM_MVE_VLDRBU8 = 1175,
	ARM_MVE_VLDRBU8_post = 1176,
	ARM_MVE_VLDRBU8_pre = 1177,
	ARM_MVE_VLDRBU8_rq = 1178,
	ARM_MVE_VLDRDU64_qi = 1179,
	ARM_MVE_VLDRDU64_qi_pre = 1180,
	ARM_MVE_VLDRDU64_rq = 1181,
	ARM_MVE_VLDRDU64_rq_u = 1182,
	ARM_MVE_VLDRHS32 = 1183,
	ARM_MVE_VLDRHS32_post = 1184,
	ARM_MVE_VLDRHS32_pre = 1185,
	ARM_MVE_VLDRHS32_rq = 1186,
	ARM_MVE_VLDRHS32_rq_u = 1187,
	ARM_MVE_VLDRHU16 = 1188,
	ARM_MVE_VLDRHU16_post = 1189,
	ARM_MVE_VLDRHU16_pre = 1190,
	ARM_MVE_VLDRHU16_rq = 1191,
	ARM_MVE_VLDRHU16_rq_u = 1192,
	ARM_MVE_VLDRHU32 = 1193,
	ARM_MVE_VLDRHU32_post = 1194,
	ARM_MVE_VLDRHU32_pre = 1195,
	ARM_MVE_VLDRHU32_rq = 1196,
	ARM_MVE_VLDRHU32_rq_u = 1197,
	ARM_MVE_VLDRWU32 = 1198,
	ARM_MVE_VLDRWU32_post = 1199,
	ARM_MVE_VLDRWU32_pre = 1200,
	ARM_MVE_VLDRWU32_qi = 1201,
	ARM_MVE_VLDRWU32_qi_pre = 1202,
	ARM_MVE_VLDRWU32_rq = 1203,
	ARM_MVE_VLDRWU32_rq_u = 1204,
	ARM_MVE_VMAXAVs16 = 1205,
	ARM_MVE_VMAXAVs32 = 1206,
	ARM_MVE_VMAXAVs8 = 1207,
	ARM_MVE_VMAXAs16 = 1208,
	ARM_MVE_VMAXAs32 = 1209,
	ARM_MVE_VMAXAs8 = 1210,
	ARM_MVE_VMAXNMAVf16 = 1211,
	ARM_MVE_VMAXNMAVf32 = 1212,
	ARM_MVE_VMAXNMAf16 = 1213,
	ARM_MVE_VMAXNMAf32 = 1214,
	ARM_MVE_VMAXNMVf16 = 1215,
	ARM_MVE_VMAXNMVf32 = 1216,
	ARM_MVE_VMAXNMf16 = 1217,
	ARM_MVE_VMAXNMf32 = 1218,
	ARM_MVE_VMAXVs16 = 1219,
	ARM_MVE_VMAXVs32 = 1220,
	ARM_MVE_VMAXVs8 = 1221,
	ARM_MVE_VMAXVu16 = 1222,
	ARM_MVE_VMAXVu32 = 1223,
	ARM_MVE_VMAXVu8 = 1224,
	ARM_MVE_VMAXs16 = 1225,
	ARM_MVE_VMAXs32 = 1226,
	ARM_MVE_VMAXs8 = 1227,
	ARM_MVE_VMAXu16 = 1228,
	ARM_MVE_VMAXu32 = 1229,
	ARM_MVE_VMAXu8 = 1230,
	ARM_MVE_VMINAVs16 = 1231,
	ARM_MVE_VMINAVs32 = 1232,
	ARM_MVE_VMINAVs8 = 1233,
	ARM_MVE_VMINAs16 = 1234,
	ARM_MVE_VMINAs32 = 1235,
	ARM_MVE_VMINAs8 = 1236,
	ARM_MVE_VMINNMAVf16 = 1237,
	ARM_MVE_VMINNMAVf32 = 1238,
	ARM_MVE_VMINNMAf16 = 1239,
	ARM_MVE_VMINNMAf32 = 1240,
	ARM_MVE_VMINNMVf16 = 1241,
	ARM_MVE_VMINNMVf32 = 1242,
	ARM_MVE_VMINNMf16 = 1243,
	ARM_MVE_VMINNMf32 = 1244,
	ARM_MVE_VMINVs16 = 1245,
	ARM_MVE_VMINVs32 = 1246,
	ARM_MVE_VMINVs8 = 1247,
	ARM_MVE_VMINVu16 = 1248,
	ARM_MVE_VMINVu32 = 1249,
	ARM_MVE_VMINVu8 = 1250,
	ARM_MVE_VMINs16 = 1251,
	ARM_MVE_VMINs32 = 1252,
	ARM_MVE_VMINs8 = 1253,
	ARM_MVE_VMINu16 = 1254,
	ARM_MVE_VMINu32 = 1255,
	ARM_MVE_VMINu8 = 1256,
	ARM_MVE_VMLADAVas16 = 1257,
	ARM_MVE_VMLADAVas32 = 1258,
	ARM_MVE_VMLADAVas8 = 1259,
	ARM_MVE_VMLADAVau16 = 1260,
	ARM_MVE_VMLADAVau32 = 1261,
	ARM_MVE_VMLADAVau8 = 1262,
	ARM_MVE_VMLADAVaxs16 = 1263,
	ARM_MVE_VMLADAVaxs32 = 1264,
	ARM_MVE_VMLADAVaxs8 = 1265,
	ARM_MVE_VMLADAVs16 = 1266,
	ARM_MVE_VMLADAVs32 = 1267,
	ARM_MVE_VMLADAVs8 = 1268,
	ARM_MVE_VMLADAVu16 = 1269,
	ARM_MVE_VMLADAVu32 = 1270,
	ARM_MVE_VMLADAVu8 = 1271,
	ARM_MVE_VMLADAVxs16 = 1272,
	ARM_MVE_VMLADAVxs32 = 1273,
	ARM_MVE_VMLADAVxs8 = 1274,
	ARM_MVE_VMLALDAVas16 = 1275,
	ARM_MVE_VMLALDAVas32 = 1276,
	ARM_MVE_VMLALDAVau16 = 1277,
	ARM_MVE_VMLALDAVau32 = 1278,
	ARM_MVE_VMLALDAVaxs16 = 1279,
	ARM_MVE_VMLALDAVaxs32 = 1280,
	ARM_MVE_VMLALDAVs16 = 1281,
	ARM_MVE_VMLALDAVs32 = 1282,
	ARM_MVE_VMLALDAVu16 = 1283,
	ARM_MVE_VMLALDAVu32 = 1284,
	ARM_MVE_VMLALDAVxs16 = 1285,
	ARM_MVE_VMLALDAVxs32 = 1286,
	ARM_MVE_VMLAS_qr_i16 = 1287,
	ARM_MVE_VMLAS_qr_i32 = 1288,
	ARM_MVE_VMLAS_qr_i8 = 1289,
	ARM_MVE_VMLA_qr_i16 = 1290,
	ARM_MVE_VMLA_qr_i32 = 1291,
	ARM_MVE_VMLA_qr_i8 = 1292,
	ARM_MVE_VMLSDAVas16 = 1293,
	ARM_MVE_VMLSDAVas32 = 1294,
	ARM_MVE_VMLSDAVas8 = 1295,
	ARM_MVE_VMLSDAVaxs16 = 1296,
	ARM_MVE_VMLSDAVaxs32 = 1297,
	ARM_MVE_VMLSDAVaxs8 = 1298,
	ARM_MVE_VMLSDAVs16 = 1299,
	ARM_MVE_VMLSDAVs32 = 1300,
	ARM_MVE_VMLSDAVs8 = 1301,
	ARM_MVE_VMLSDAVxs16 = 1302,
	ARM_MVE_VMLSDAVxs32 = 1303,
	ARM_MVE_VMLSDAVxs8 = 1304,
	ARM_MVE_VMLSLDAVas16 = 1305,
	ARM_MVE_VMLSLDAVas32 = 1306,
	ARM_MVE_VMLSLDAVaxs16 = 1307,
	ARM_MVE_VMLSLDAVaxs32 = 1308,
	ARM_MVE_VMLSLDAVs16 = 1309,
	ARM_MVE_VMLSLDAVs32 = 1310,
	ARM_MVE_VMLSLDAVxs16 = 1311,
	ARM_MVE_VMLSLDAVxs32 = 1312,
	ARM_MVE_VMOVLs16bh = 1313,
	ARM_MVE_VMOVLs16th = 1314,
	ARM_MVE_VMOVLs8bh = 1315,
	ARM_MVE_VMOVLs8th = 1316,
	ARM_MVE_VMOVLu16bh = 1317,
	ARM_MVE_VMOVLu16th = 1318,
	ARM_MVE_VMOVLu8bh = 1319,
	ARM_MVE_VMOVLu8th = 1320,
	ARM_MVE_VMOVNi16bh = 1321,
	ARM_MVE_VMOVNi16th = 1322,
	ARM_MVE_VMOVNi32bh = 1323,
	ARM_MVE_VMOVNi32th = 1324,
	ARM_MVE_VMOV_from_lane_32 = 1325,
	ARM_MVE_VMOV_from_lane_s16 = 1326,
	ARM_MVE_VMOV_from_lane_s8 = 1327,
	ARM_MVE_VMOV_from_lane_u16 = 1328,
	ARM_MVE_VMOV_from_lane_u8 = 1329,
	ARM_MVE_VMOV_q_rr = 1330,
	ARM_MVE_VMOV_rr_q = 1331,
	ARM_MVE_VMOV_to_lane_16 = 1332,
	ARM_MVE_VMOV_to_lane_32 = 1333,
	ARM_MVE_VMOV_to_lane_8 = 1334,
	ARM_MVE_VMOVimmf32 = 1335,
	ARM_MVE_VMOVimmi16 = 1336,
	ARM_MVE_VMOVimmi32 = 1337,
	ARM_MVE_VMOVimmi64 = 1338,
	ARM_MVE_VMOVimmi8 = 1339,
	ARM_MVE_VMULHs16 = 1340,
	ARM_MVE_VMULHs32 = 1341,
	ARM_MVE_VMULHs8 = 1342,
	ARM_MVE_VMULHu16 = 1343,
	ARM_MVE_VMULHu32 = 1344,
	ARM_MVE_VMULHu8 = 1345,
	ARM_MVE_VMULLBp16 = 1346,
	ARM_MVE_VMULLBp8 = 1347,
	ARM_MVE_VMULLBs16 = 1348,
	ARM_MVE_VMULLBs32 = 1349,
	ARM_MVE_VMULLBs8 = 1350,
	ARM_MVE_VMULLBu16 = 1351,
	ARM_MVE_VMULLBu32 = 1352,
	ARM_MVE_VMULLBu8 = 1353,
	ARM_MVE_VMULLTp16 = 1354,
	ARM_MVE_VMULLTp8 = 1355,
	ARM_MVE_VMULLTs16 = 1356,
	ARM_MVE_VMULLTs32 = 1357,
	ARM_MVE_VMULLTs8 = 1358,
	ARM_MVE_VMULLTu16 = 1359,
	ARM_MVE_VMULLTu32 = 1360,
	ARM_MVE_VMULLTu8 = 1361,
	ARM_MVE_VMUL_qr_f16 = 1362,
	ARM_MVE_VMUL_qr_f32 = 1363,
	ARM_MVE_VMUL_qr_i16 = 1364,
	ARM_MVE_VMUL_qr_i32 = 1365,
	ARM_MVE_VMUL_qr_i8 = 1366,
	ARM_MVE_VMULf16 = 1367,
	ARM_MVE_VMULf32 = 1368,
	ARM_MVE_VMULi16 = 1369,
	ARM_MVE_VMULi32 = 1370,
	ARM_MVE_VMULi8 = 1371,
	ARM_MVE_VMVN = 1372,
	ARM_MVE_VMVNimmi16 = 1373,
	ARM_MVE_VMVNimmi32 = 1374,
	ARM_MVE_VNEGf16 = 1375,
	ARM_MVE_VNEGf32 = 1376,
	ARM_MVE_VNEGs16 = 1377,
	ARM_MVE_VNEGs32 = 1378,
	ARM_MVE_VNEGs8 = 1379,
	ARM_MVE_VORN = 1380,
	ARM_MVE_VORR = 1381,
	ARM_MVE_VORRimmi16 = 1382,
	ARM_MVE_VORRimmi32 = 1383,
	ARM_MVE_VPNOT = 1384,
	ARM_MVE_VPSEL = 1385,
	ARM_MVE_VPST = 1386,
	ARM_MVE_VPTv16i8 = 1387,
	ARM_MVE_VPTv16i8r = 1388,
	ARM_MVE_VPTv16s8 = 1389,
	ARM_MVE_VPTv16s8r = 1390,
	ARM_MVE_VPTv16u8 = 1391,
	ARM_MVE_VPTv16u8r = 1392,
	ARM_MVE_VPTv4f32 = 1393,
	ARM_MVE_VPTv4f32r = 1394,
	ARM_MVE_VPTv4i32 = 1395,
	ARM_MVE_VPTv4i32r = 1396,
	ARM_MVE_VPTv4s32 = 1397,
	ARM_MVE_VPTv4s32r = 1398,
	ARM_MVE_VPTv4u32 = 1399,
	ARM_MVE_VPTv4u32r = 1400,
	ARM_MVE_VPTv8f16 = 1401,
	ARM_MVE_VPTv8f16r = 1402,
	ARM_MVE_VPTv8i16 = 1403,
	ARM_MVE_VPTv8i16r = 1404,
	ARM_MVE_VPTv8s16 = 1405,
	ARM_MVE_VPTv8s16r = 1406,
	ARM_MVE_VPTv8u16 = 1407,
	ARM_MVE_VPTv8u16r = 1408,
	ARM_MVE_VQABSs16 = 1409,
	ARM_MVE_VQABSs32 = 1410,
	ARM_MVE_VQABSs8 = 1411,
	ARM_MVE_VQADD_qr_s16 = 1412,
	ARM_MVE_VQADD_qr_s32 = 1413,
	ARM_MVE_VQADD_qr_s8 = 1414,
	ARM_MVE_VQADD_qr_u16 = 1415,
	ARM_MVE_VQADD_qr_u32 = 1416,
	ARM_MVE_VQADD_qr_u8 = 1417,
	ARM_MVE_VQADDs16 = 1418,
	ARM_MVE_VQADDs32 = 1419,
	ARM_MVE_VQADDs8 = 1420,
	ARM_MVE_VQADDu16 = 1421,
	ARM_MVE_VQADDu32 = 1422,
	ARM_MVE_VQADDu8 = 1423,
	ARM_MVE_VQDMLADHXs16 = 1424,
	ARM_MVE_VQDMLADHXs32 = 1425,
	ARM_MVE_VQDMLADHXs8 = 1426,
	ARM_MVE_VQDMLADHs16 = 1427,
	ARM_MVE_VQDMLADHs32 = 1428,
	ARM_MVE_VQDMLADHs8 = 1429,
	ARM_MVE_VQDMLAH_qrs16 = 1430,
	ARM_MVE_VQDMLAH_qrs32 = 1431,
	ARM_MVE_VQDMLAH_qrs8 = 1432,
	ARM_MVE_VQDMLASH_qrs16 = 1433,
	ARM_MVE_VQDMLASH_qrs32 = 1434,
	ARM_MVE_VQDMLASH_qrs8 = 1435,
	ARM_MVE_VQDMLSDHXs16 = 1436,
	ARM_MVE_VQDMLSDHXs32 = 1437,
	ARM_MVE_VQDMLSDHXs8 = 1438,
	ARM_MVE_VQDMLSDHs16 = 1439,
	ARM_MVE_VQDMLSDHs32 = 1440,
	ARM_MVE_VQDMLSDHs8 = 1441,
	ARM_MVE_VQDMULH_qr_s16 = 1442,
	ARM_MVE_VQDMULH_qr_s32 = 1443,
	ARM_MVE_VQDMULH_qr_s8 = 1444,
	ARM_MVE_VQDMULHi16 = 1445,
	ARM_MVE_VQDMULHi32 = 1446,
	ARM_MVE_VQDMULHi8 = 1447,
	ARM_MVE_VQDMULL_qr_s16bh = 1448,
	ARM_MVE_VQDMULL_qr_s16th = 1449,
	ARM_MVE_VQDMULL_qr_s32bh = 1450,
	ARM_MVE_VQDMULL_qr_s32th = 1451,
	ARM_MVE_VQDMULLs16bh = 1452,
	ARM_MVE_VQDMULLs16th = 1453,
	ARM_MVE_VQDMULLs32bh = 1454,
	ARM_MVE_VQDMULLs32th = 1455,
	ARM_MVE_VQMOVNs16bh = 1456,
	ARM_MVE_VQMOVNs16th = 1457,
	ARM_MVE_VQMOVNs32bh = 1458,
	ARM_MVE_VQMOVNs32th = 1459,
	ARM_MVE_VQMOVNu16bh = 1460,
	ARM_MVE_VQMOVNu16th = 1461,
	ARM_MVE_VQMOVNu32bh = 1462,
	ARM_MVE_VQMOVNu32th = 1463,
	ARM_MVE_VQMOVUNs16bh = 1464,
	ARM_MVE_VQMOVUNs16th = 1465,
	ARM_MVE_VQMOVUNs32bh = 1466,
	ARM_MVE_VQMOVUNs32th = 1467,
	ARM_MVE_VQNEGs16 = 1468,
	ARM_MVE_VQNEGs32 = 1469,
	ARM_MVE_VQNEGs8 = 1470,
	ARM_MVE_VQRDMLADHXs16 = 1471,
	ARM_MVE_VQRDMLADHXs32 = 1472,
	ARM_MVE_VQRDMLADHXs8 = 1473,
	ARM_MVE_VQRDMLADHs16 = 1474,
	ARM_MVE_VQRDMLADHs32 = 1475,
	ARM_MVE_VQRDMLADHs8 = 1476,
	ARM_MVE_VQRDMLAH_qrs16 = 1477,
	ARM_MVE_VQRDMLAH_qrs32 = 1478,
	ARM_MVE_VQRDMLAH_qrs8 = 1479,
	ARM_MVE_VQRDMLASH_qrs16 = 1480,
	ARM_MVE_VQRDMLASH_qrs32 = 1481,
	ARM_MVE_VQRDMLASH_qrs8 = 1482,
	ARM_MVE_VQRDMLSDHXs16 = 1483,
	ARM_MVE_VQRDMLSDHXs32 = 1484,
	ARM_MVE_VQRDMLSDHXs8 = 1485,
	ARM_MVE_VQRDMLSDHs16 = 1486,
	ARM_MVE_VQRDMLSDHs32 = 1487,
	ARM_MVE_VQRDMLSDHs8 = 1488,
	ARM_MVE_VQRDMULH_qr_s16 = 1489,
	ARM_MVE_VQRDMULH_qr_s32 = 1490,
	ARM_MVE_VQRDMULH_qr_s8 = 1491,
	ARM_MVE_VQRDMULHi16 = 1492,
	ARM_MVE_VQRDMULHi32 = 1493,
	ARM_MVE_VQRDMULHi8 = 1494,
	ARM_MVE_VQRSHL_by_vecs16 = 1495,
	ARM_MVE_VQRSHL_by_vecs32 = 1496,
	ARM_MVE_VQRSHL_by_vecs8 = 1497,
	ARM_MVE_VQRSHL_by_vecu16 = 1498,
	ARM_MVE_VQRSHL_by_vecu32 = 1499,
	ARM_MVE_VQRSHL_by_vecu8 = 1500,
	ARM_MVE_VQRSHL_qrs16 = 1501,
	ARM_MVE_VQRSHL_qrs32 = 1502,
	ARM_MVE_VQRSHL_qrs8 = 1503,
	ARM_MVE_VQRSHL_qru16 = 1504,
	ARM_MVE_VQRSHL_qru32 = 1505,
	ARM_MVE_VQRSHL_qru8 = 1506,
	ARM_MVE_VQRSHRNbhs16 = 1507,
	ARM_MVE_VQRSHRNbhs32 = 1508,
	ARM_MVE_VQRSHRNbhu16 = 1509,
	ARM_MVE_VQRSHRNbhu32 = 1510,
	ARM_MVE_VQRSHRNths16 = 1511,
	ARM_MVE_VQRSHRNths32 = 1512,
	ARM_MVE_VQRSHRNthu16 = 1513,
	ARM_MVE_VQRSHRNthu32 = 1514,
	ARM_MVE_VQRSHRUNs16bh = 1515,
	ARM_MVE_VQRSHRUNs16th = 1516,
	ARM_MVE_VQRSHRUNs32bh = 1517,
	ARM_MVE_VQRSHRUNs32th = 1518,
	ARM_MVE_VQSHLU_imms16 = 1519,
	ARM_MVE_VQSHLU_imms32 = 1520,
	ARM_MVE_VQSHLU_imms8 = 1521,
	ARM_MVE_VQSHL_by_vecs16 = 1522,
	ARM_MVE_VQSHL_by_vecs32 = 1523,
	ARM_MVE_VQSHL_by_vecs8 = 1524,
	ARM_MVE_VQSHL_by_vecu16 = 1525,
	ARM_MVE_VQSHL_by_vecu32 = 1526,
	ARM_MVE_VQSHL_by_vecu8 = 1527,
	ARM_MVE_VQSHL_qrs16 = 1528,
	ARM_MVE_VQSHL_qrs32 = 1529,
	ARM_MVE_VQSHL_qrs8 = 1530,
	ARM_MVE_VQSHL_qru16 = 1531,
	ARM_MVE_VQSHL_qru32 = 1532,
	ARM_MVE_VQSHL_qru8 = 1533,
	ARM_MVE_VQSHLimms16 = 1534,
	ARM_MVE_VQSHLimms32 = 1535,
	ARM_MVE_VQSHLimms8 = 1536,
	ARM_MVE_VQSHLimmu16 = 1537,
	ARM_MVE_VQSHLimmu32 = 1538,
	ARM_MVE_VQSHLimmu8 = 1539,
	ARM_MVE_VQSHRNbhs16 = 1540,
	ARM_MVE_VQSHRNbhs32 = 1541,
	ARM_MVE_VQSHRNbhu16 = 1542,
	ARM_MVE_VQSHRNbhu32 = 1543,
	ARM_MVE_VQSHRNths16 = 1544,
	ARM_MVE_VQSHRNths32 = 1545,
	ARM_MVE_VQSHRNthu16 = 1546,
	ARM_MVE_VQSHRNthu32 = 1547,
	ARM_MVE_VQSHRUNs16bh = 1548,
	ARM_MVE_VQSHRUNs16th = 1549,
	ARM_MVE_VQSHRUNs32bh = 1550,
	ARM_MVE_VQSHRUNs32th = 1551,
	ARM_MVE_VQSUB_qr_s16 = 1552,
	ARM_MVE_VQSUB_qr_s32 = 1553,
	ARM_MVE_VQSUB_qr_s8 = 1554,
	ARM_MVE_VQSUB_qr_u16 = 1555,
	ARM_MVE_VQSUB_qr_u32 = 1556,
	ARM_MVE_VQSUB_qr_u8 = 1557,
	ARM_MVE_VQSUBs16 = 1558,
	ARM_MVE_VQSUBs32 = 1559,
	ARM_MVE_VQSUBs8 = 1560,
	ARM_MVE_VQSUBu16 = 1561,
	ARM_MVE_VQSUBu32 = 1562,
	ARM_MVE_VQSUBu8 = 1563,
	ARM_MVE_VREV16_8 = 1564,
	ARM_MVE_VREV32_16 = 1565,
	ARM_MVE_VREV32_8 = 1566,
	ARM_MVE_VREV64_16 = 1567,
	ARM_MVE_VREV64_32 = 1568,
	ARM_MVE_VREV64_8 = 1569,
	ARM_MVE_VRHADDs16 = 1570,
	ARM_MVE_VRHADDs32 = 1571,
	ARM_MVE_VRHADDs8 = 1572,
	ARM_MVE_VRHADDu16 = 1573,
	ARM_MVE_VRHADDu32 = 1574,
	ARM_MVE_VRHADDu8 = 1575,
	ARM_MVE_VRINTf16A = 1576,
	ARM_MVE_VRINTf16M = 1577,
	ARM_MVE_VRINTf16N = 1578,
	ARM_MVE_VRINTf16P = 1579,
	ARM_MVE_VRINTf16X = 1580,
	ARM_MVE_VRINTf16Z = 1581,
	ARM_MVE_VRINTf32A = 1582,
	ARM_MVE_VRINTf32M = 1583,
	ARM_MVE_VRINTf32N = 1584,
	ARM_MVE_VRINTf32P = 1585,
	ARM_MVE_VRINTf32X = 1586,
	ARM_MVE_VRINTf32Z = 1587,
	ARM_MVE_VRMLALDAVHas32 = 1588,
	ARM_MVE_VRMLALDAVHau32 = 1589,
	ARM_MVE_VRMLALDAVHaxs32 = 1590,
	ARM_MVE_VRMLALDAVHs32 = 1591,
	ARM_MVE_VRMLALDAVHu32 = 1592,
	ARM_MVE_VRMLALDAVHxs32 = 1593,
	ARM_MVE_VRMLSLDAVHas32 = 1594,
	ARM_MVE_VRMLSLDAVHaxs32 = 1595,
	ARM_MVE_VRMLSLDAVHs32 = 1596,
	ARM_MVE_VRMLSLDAVHxs32 = 1597,
	ARM_MVE_VRMULHs16 = 1598,
	ARM_MVE_VRMULHs32 = 1599,
	ARM_MVE_VRMULHs8 = 1600,
	ARM_MVE_VRMULHu16 = 1601,
	ARM_MVE_VRMULHu32 = 1602,
	ARM_MVE_VRMULHu8 = 1603,
	ARM_MVE_VRSHL_by_vecs16 = 1604,
	ARM_MVE_VRSHL_by_vecs32 = 1605,
	ARM_MVE_VRSHL_by_vecs8 = 1606,
	ARM_MVE_VRSHL_by_vecu16 = 1607,
	ARM_MVE_VRSHL_by_vecu32 = 1608,
	ARM_MVE_VRSHL_by_vecu8 = 1609,
	ARM_MVE_VRSHL_qrs16 = 1610,
	ARM_MVE_VRSHL_qrs32 = 1611,
	ARM_MVE_VRSHL_qrs8 = 1612,
	ARM_MVE_VRSHL_qru16 = 1613,
	ARM_MVE_VRSHL_qru32 = 1614,
	ARM_MVE_VRSHL_qru8 = 1615,
	ARM_MVE_VRSHRNi16bh = 1616,
	ARM_MVE_VRSHRNi16th = 1617,
	ARM_MVE_VRSHRNi32bh = 1618,
	ARM_MVE_VRSHRNi32th = 1619,
	ARM_MVE_VRSHR_imms16 = 1620,
	ARM_MVE_VRSHR_imms32 = 1621,
	ARM_MVE_VRSHR_imms8 = 1622,
	ARM_MVE_VRSHR_immu16 = 1623,
	ARM_MVE_VRSHR_immu32 = 1624,
	ARM_MVE_VRSHR_immu8 = 1625,
	ARM_MVE_VSBC = 1626,
	ARM_MVE_VSBCI = 1627,
	ARM_MVE_VSHLC = 1628,
	ARM_MVE_VSHLL_imms16bh = 1629,
	ARM_MVE_VSHLL_imms16th = 1630,
	ARM_MVE_VSHLL_imms8bh = 1631,
	ARM_MVE_VSHLL_imms8th = 1632,
	ARM_MVE_VSHLL_immu16bh = 1633,
	ARM_MVE_VSHLL_immu16th = 1634,
	ARM_MVE_VSHLL_immu8bh = 1635,
	ARM_MVE_VSHLL_immu8th = 1636,
	ARM_MVE_VSHLL_lws16bh = 1637,
	ARM_MVE_VSHLL_lws16th = 1638,
	ARM_MVE_VSHLL_lws8bh = 1639,
	ARM_MVE_VSHLL_lws8th = 1640,
	ARM_MVE_VSHLL_lwu16bh = 1641,
	ARM_MVE_VSHLL_lwu16th = 1642,
	ARM_MVE_VSHLL_lwu8bh = 1643,
	ARM_MVE_VSHLL_lwu8th = 1644,
	ARM_MVE_VSHL_by_vecs16 = 1645,
	ARM_MVE_VSHL_by_vecs32 = 1646,
	ARM_MVE_VSHL_by_vecs8 = 1647,
	ARM_MVE_VSHL_by_vecu16 = 1648,
	ARM_MVE_VSHL_by_vecu32 = 1649,
	ARM_MVE_VSHL_by_vecu8 = 1650,
	ARM_MVE_VSHL_immi16 = 1651,
	ARM_MVE_VSHL_immi32 = 1652,
	ARM_MVE_VSHL_immi8 = 1653,
	ARM_MVE_VSHL_qrs16 = 1654,
	ARM_MVE_VSHL_qrs32 = 1655,
	ARM_MVE_VSHL_qrs8 = 1656,
	ARM_MVE_VSHL_qru16 = 1657,
	ARM_MVE_VSHL_qru32 = 1658,
	ARM_MVE_VSHL_qru8 = 1659,
	ARM_MVE_VSHRNi16bh = 1660,
	ARM_MVE_VSHRNi16th = 1661,
	ARM_MVE_VSHRNi32bh = 1662,
	ARM_MVE_VSHRNi32th = 1663,
	ARM_MVE_VSHR_imms16 = 1664,
	ARM_MVE_VSHR_imms32 = 1665,
	ARM_MVE_VSHR_imms8 = 1666,
	ARM_MVE_VSHR_immu16 = 1667,
	ARM_MVE_VSHR_immu32 = 1668,
	ARM_MVE_VSHR_immu8 = 1669,
	ARM_MVE_VSLIimm16 = 1670,
	ARM_MVE_VSLIimm32 = 1671,
	ARM_MVE_VSLIimm8 = 1672,
	ARM_MVE_VSRIimm16 = 1673,
	ARM_MVE_VSRIimm32 = 1674,
	ARM_MVE_VSRIimm8 = 1675,
	ARM_MVE_VST20_16 = 1676,
	ARM_MVE_VST20_16_wb = 1677,
	ARM_MVE_VST20_32 = 1678,
	ARM_MVE_VST20_32_wb = 1679,
	ARM_MVE_VST20_8 = 1680,
	ARM_MVE_VST20_8_wb = 1681,
	ARM_MVE_VST21_16 = 1682,
	ARM_MVE_VST21_16_wb = 1683,
	ARM_MVE_VST21_32 = 1684,
	ARM_MVE_VST21_32_wb = 1685,
	ARM_MVE_VST21_8 = 1686,
	ARM_MVE_VST21_8_wb = 1687,
	ARM_MVE_VST40_16 = 1688,
	ARM_MVE_VST40_16_wb = 1689,
	ARM_MVE_VST40_32 = 1690,
	ARM_MVE_VST40_32_wb = 1691,
	ARM_MVE_VST40_8 = 1692,
	ARM_MVE_VST40_8_wb = 1693,
	ARM_MVE_VST41_16 = 1694,
	ARM_MVE_VST41_16_wb = 1695,
	ARM_MVE_VST41_32 = 1696,
	ARM_MVE_VST41_32_wb = 1697,
	ARM_MVE_VST41_8 = 1698,
	ARM_MVE_VST41_8_wb = 1699,
	ARM_MVE_VST42_16 = 1700,
	ARM_MVE_VST42_16_wb = 1701,
	ARM_MVE_VST42_32 = 1702,
	ARM_MVE_VST42_32_wb = 1703,
	ARM_MVE_VST42_8 = 1704,
	ARM_MVE_VST42_8_wb = 1705,
	ARM_MVE_VST43_16 = 1706,
	ARM_MVE_VST43_16_wb = 1707,
	ARM_MVE_VST43_32 = 1708,
	ARM_MVE_VST43_32_wb = 1709,
	ARM_MVE_VST43_8 = 1710,
	ARM_MVE_VST43_8_wb = 1711,
	ARM_MVE_VSTRB16 = 1712,
	ARM_MVE_VSTRB16_post = 1713,
	ARM_MVE_VSTRB16_pre = 1714,
	ARM_MVE_VSTRB16_rq = 1715,
	ARM_MVE_VSTRB32 = 1716,
	ARM_MVE_VSTRB32_post = 1717,
	ARM_MVE_VSTRB32_pre = 1718,
	ARM_MVE_VSTRB32_rq = 1719,
	ARM_MVE_VSTRB8_rq = 1720,
	ARM_MVE_VSTRBU8 = 1721,
	ARM_MVE_VSTRBU8_post = 1722,
	ARM_MVE_VSTRBU8_pre = 1723,
	ARM_MVE_VSTRD64_qi = 1724,
	ARM_MVE_VSTRD64_qi_pre = 1725,
	ARM_MVE_VSTRD64_rq = 1726,
	ARM_MVE_VSTRD64_rq_u = 1727,
	ARM_MVE_VSTRH16_rq = 1728,
	ARM_MVE_VSTRH16_rq_u = 1729,
	ARM_MVE_VSTRH32 = 1730,
	ARM_MVE_VSTRH32_post = 1731,
	ARM_MVE_VSTRH32_pre = 1732,
	ARM_MVE_VSTRH32_rq = 1733,
	ARM_MVE_VSTRH32_rq_u = 1734,
	ARM_MVE_VSTRHU16 = 1735,
	ARM_MVE_VSTRHU16_post = 1736,
	ARM_MVE_VSTRHU16_pre = 1737,
	ARM_MVE_VSTRW32_qi = 1738,
	ARM_MVE_VSTRW32_qi_pre = 1739,
	ARM_MVE_VSTRW32_rq = 1740,
	ARM_MVE_VSTRW32_rq_u = 1741,
	ARM_MVE_VSTRWU32 = 1742,
	ARM_MVE_VSTRWU32_post = 1743,
	ARM_MVE_VSTRWU32_pre = 1744,
	ARM_MVE_VSUB_qr_f16 = 1745,
	ARM_MVE_VSUB_qr_f32 = 1746,
	ARM_MVE_VSUB_qr_i16 = 1747,
	ARM_MVE_VSUB_qr_i32 = 1748,
	ARM_MVE_VSUB_qr_i8 = 1749,
	ARM_MVE_VSUBf16 = 1750,
	ARM_MVE_VSUBf32 = 1751,
	ARM_MVE_VSUBi16 = 1752,
	ARM_MVE_VSUBi32 = 1753,
	ARM_MVE_VSUBi8 = 1754,
	ARM_MVE_WLSTP_16 = 1755,
	ARM_MVE_WLSTP_32 = 1756,
	ARM_MVE_WLSTP_64 = 1757,
	ARM_MVE_WLSTP_8 = 1758,
	ARM_MVNi = 1759,
	ARM_MVNr = 1760,
	ARM_MVNsi = 1761,
	ARM_MVNsr = 1762,
	ARM_NEON_VMAXNMNDf = 1763,
	ARM_NEON_VMAXNMNDh = 1764,
	ARM_NEON_VMAXNMNQf = 1765,
	ARM_NEON_VMAXNMNQh = 1766,
	ARM_NEON_VMINNMNDf = 1767,
	ARM_NEON_VMINNMNDh = 1768,
	ARM_NEON_VMINNMNQf = 1769,
	ARM_NEON_VMINNMNQh = 1770,
	ARM_ORRri = 1771,
	ARM_ORRrr = 1772,
	ARM_ORRrsi = 1773,
	ARM_ORRrsr = 1774,
	ARM_PKHBT = 1775,
	ARM_PKHTB = 1776,
	ARM_PLDWi12 = 1777,
	ARM_PLDWrs = 1778,
	ARM_PLDi12 = 1779,
	ARM_PLDrs = 1780,
	ARM_PLIi12 = 1781,
	ARM_PLIrs = 1782,
	ARM_QADD = 1783,
	ARM_QADD16 = 1784,
	ARM_QADD8 = 1785,
	ARM_QASX = 1786,
	ARM_QDADD = 1787,
	ARM_QDSUB = 1788,
	ARM_QSAX = 1789,
	ARM_QSUB = 1790,
	ARM_QSUB16 = 1791,
	ARM_QSUB8 = 1792,
	ARM_RBIT = 1793,
	ARM_REV = 1794,
	ARM_REV16 = 1795,
	ARM_REVSH = 1796,
	ARM_RFEDA = 1797,
	ARM_RFEDA_UPD = 1798,
	ARM_RFEDB = 1799,
	ARM_RFEDB_UPD = 1800,
	ARM_RFEIA = 1801,
	ARM_RFEIA_UPD = 1802,
	ARM_RFEIB = 1803,
	ARM_RFEIB_UPD = 1804,
	ARM_RSBri = 1805,
	ARM_RSBrr = 1806,
	ARM_RSBrsi = 1807,
	ARM_RSBrsr = 1808,
	ARM_RSCri = 1809,
	ARM_RSCrr = 1810,
	ARM_RSCrsi = 1811,
	ARM_RSCrsr = 1812,
	ARM_SADD16 = 1813,
	ARM_SADD8 = 1814,
	ARM_SASX = 1815,
	ARM_SB = 1816,
	ARM_SBCri = 1817,
	ARM_SBCrr = 1818,
	ARM_SBCrsi = 1819,
	ARM_SBCrsr = 1820,
	ARM_SBFX = 1821,
	ARM_SDIV = 1822,
	ARM_SEL = 1823,
	ARM_SETEND = 1824,
	ARM_SETPAN = 1825,
	ARM_SHA1C = 1826,
	ARM_SHA1H = 1827,
	ARM_SHA1M = 1828,
	ARM_SHA1P = 1829,
	ARM_SHA1SU0 = 1830,
	ARM_SHA1SU1 = 1831,
	ARM_SHA256H = 1832,
	ARM_SHA256H2 = 1833,
	ARM_SHA256SU0 = 1834,
	ARM_SHA256SU1 = 1835,
	ARM_SHADD16 = 1836,
	ARM_SHADD8 = 1837,
	ARM_SHASX = 1838,
	ARM_SHSAX = 1839,
	ARM_SHSUB16 = 1840,
	ARM_SHSUB8 = 1841,
	ARM_SMC = 1842,
	ARM_SMLABB = 1843,
	ARM_SMLABT = 1844,
	ARM_SMLAD = 1845,
	ARM_SMLADX = 1846,
	ARM_SMLAL = 1847,
	ARM_SMLALBB = 1848,
	ARM_SMLALBT = 1849,
	ARM_SMLALD = 1850,
	ARM_SMLALDX = 1851,
	ARM_SMLALTB = 1852,
	ARM_SMLALTT = 1853,
	ARM_SMLATB = 1854,
	ARM_SMLATT = 1855,
	ARM_SMLAWB = 1856,
	ARM_SMLAWT = 1857,
	ARM_SMLSD = 1858,
	ARM_SMLSDX = 1859,
	ARM_SMLSLD = 1860,
	ARM_SMLSLDX = 1861,
	ARM_SMMLA = 1862,
	ARM_SMMLAR = 1863,
	ARM_SMMLS = 1864,
	ARM_SMMLSR = 1865,
	ARM_SMMUL = 1866,
	ARM_SMMULR = 1867,
	ARM_SMUAD = 1868,
	ARM_SMUADX = 1869,
	ARM_SMULBB = 1870,
	ARM_SMULBT = 1871,
	ARM_SMULL = 1872,
	ARM_SMULTB = 1873,
	ARM_SMULTT = 1874,
	ARM_SMULWB = 1875,
	ARM_SMULWT = 1876,
	ARM_SMUSD = 1877,
	ARM_SMUSDX = 1878,
	ARM_SRSDA = 1879,
	ARM_SRSDA_UPD = 1880,
	ARM_SRSDB = 1881,
	ARM_SRSDB_UPD = 1882,
	ARM_SRSIA = 1883,
	ARM_SRSIA_UPD = 1884,
	ARM_SRSIB = 1885,
	ARM_SRSIB_UPD = 1886,
	ARM_SSAT = 1887,
	ARM_SSAT16 = 1888,
	ARM_SSAX = 1889,
	ARM_SSUB16 = 1890,
	ARM_SSUB8 = 1891,
	ARM_STC2L_OFFSET = 1892,
	ARM_STC2L_OPTION = 1893,
	ARM_STC2L_POST = 1894,
	ARM_STC2L_PRE = 1895,
	ARM_STC2_OFFSET = 1896,
	ARM_STC2_OPTION = 1897,
	ARM_STC2_POST = 1898,
	ARM_STC2_PRE = 1899,
	ARM_STCL_OFFSET = 1900,
	ARM_STCL_OPTION = 1901,
	ARM_STCL_POST = 1902,
	ARM_STCL_PRE = 1903,
	ARM_STC_OFFSET = 1904,
	ARM_STC_OPTION = 1905,
	ARM_STC_POST = 1906,
	ARM_STC_PRE = 1907,
	ARM_STL = 1908,
	ARM_STLB = 1909,
	ARM_STLEX = 1910,
	ARM_STLEXB = 1911,
	ARM_STLEXD = 1912,
	ARM_STLEXH = 1913,
	ARM_STLH = 1914,
	ARM_STMDA = 1915,
	ARM_STMDA_UPD = 1916,
	ARM_STMDB = 1917,
	ARM_STMDB_UPD = 1918,
	ARM_STMIA = 1919,
	ARM_STMIA_UPD = 1920,
	ARM_STMIB = 1921,
	ARM_STMIB_UPD = 1922,
	ARM_STRBT_POST_IMM = 1923,
	ARM_STRBT_POST_REG = 1924,
	ARM_STRB_POST_IMM = 1925,
	ARM_STRB_POST_REG = 1926,
	ARM_STRB_PRE_IMM = 1927,
	ARM_STRB_PRE_REG = 1928,
	ARM_STRBi12 = 1929,
	ARM_STRBrs = 1930,
	ARM_STRD = 1931,
	ARM_STRD_POST = 1932,
	ARM_STRD_PRE = 1933,
	ARM_STREX = 1934,
	ARM_STREXB = 1935,
	ARM_STREXD = 1936,
	ARM_STREXH = 1937,
	ARM_STRH = 1938,
	ARM_STRHTi = 1939,
	ARM_STRHTr = 1940,
	ARM_STRH_POST = 1941,
	ARM_STRH_PRE = 1942,
	ARM_STRT_POST_IMM = 1943,
	ARM_STRT_POST_REG = 1944,
	ARM_STR_POST_IMM = 1945,
	ARM_STR_POST_REG = 1946,
	ARM_STR_PRE_IMM = 1947,
	ARM_STR_PRE_REG = 1948,
	ARM_STRi12 = 1949,
	ARM_STRrs = 1950,
	ARM_SUBri = 1951,
	ARM_SUBrr = 1952,
	ARM_SUBrsi = 1953,
	ARM_SUBrsr = 1954,
	ARM_SVC = 1955,
	ARM_SWP = 1956,
	ARM_SWPB = 1957,
	ARM_SXTAB = 1958,
	ARM_SXTAB16 = 1959,
	ARM_SXTAH = 1960,
	ARM_SXTB = 1961,
	ARM_SXTB16 = 1962,
	ARM_SXTH = 1963,
	ARM_TEQri = 1964,
	ARM_TEQrr = 1965,
	ARM_TEQrsi = 1966,
	ARM_TEQrsr = 1967,
	ARM_TRAP = 1968,
	ARM_TRAPNaCl = 1969,
	ARM_TSB = 1970,
	ARM_TSTri = 1971,
	ARM_TSTrr = 1972,
	ARM_TSTrsi = 1973,
	ARM_TSTrsr = 1974,
	ARM_UADD16 = 1975,
	ARM_UADD8 = 1976,
	ARM_UASX = 1977,
	ARM_UBFX = 1978,
	ARM_UDF = 1979,
	ARM_UDIV = 1980,
	ARM_UHADD16 = 1981,
	ARM_UHADD8 = 1982,
	ARM_UHASX = 1983,
	ARM_UHSAX = 1984,
	ARM_UHSUB16 = 1985,
	ARM_UHSUB8 = 1986,
	ARM_UMAAL = 1987,
	ARM_UMLAL = 1988,
	ARM_UMULL = 1989,
	ARM_UQADD16 = 1990,
	ARM_UQADD8 = 1991,
	ARM_UQASX = 1992,
	ARM_UQSAX = 1993,
	ARM_UQSUB16 = 1994,
	ARM_UQSUB8 = 1995,
	ARM_USAD8 = 1996,
	ARM_USADA8 = 1997,
	ARM_USAT = 1998,
	ARM_USAT16 = 1999,
	ARM_USAX = 2000,
	ARM_USUB16 = 2001,
	ARM_USUB8 = 2002,
	ARM_UXTAB = 2003,
	ARM_UXTAB16 = 2004,
	ARM_UXTAH = 2005,
	ARM_UXTB = 2006,
	ARM_UXTB16 = 2007,
	ARM_UXTH = 2008,
	ARM_VABALsv2i64 = 2009,
	ARM_VABALsv4i32 = 2010,
	ARM_VABALsv8i16 = 2011,
	ARM_VABALuv2i64 = 2012,
	ARM_VABALuv4i32 = 2013,
	ARM_VABALuv8i16 = 2014,
	ARM_VABAsv16i8 = 2015,
	ARM_VABAsv2i32 = 2016,
	ARM_VABAsv4i16 = 2017,
	ARM_VABAsv4i32 = 2018,
	ARM_VABAsv8i16 = 2019,
	ARM_VABAsv8i8 = 2020,
	ARM_VABAuv16i8 = 2021,
	ARM_VABAuv2i32 = 2022,
	ARM_VABAuv4i16 = 2023,
	ARM_VABAuv4i32 = 2024,
	ARM_VABAuv8i16 = 2025,
	ARM_VABAuv8i8 = 2026,
	ARM_VABDLsv2i64 = 2027,
	ARM_VABDLsv4i32 = 2028,
	ARM_VABDLsv8i16 = 2029,
	ARM_VABDLuv2i64 = 2030,
	ARM_VABDLuv4i32 = 2031,
	ARM_VABDLuv8i16 = 2032,
	ARM_VABDfd = 2033,
	ARM_VABDfq = 2034,
	ARM_VABDhd = 2035,
	ARM_VABDhq = 2036,
	ARM_VABDsv16i8 = 2037,
	ARM_VABDsv2i32 = 2038,
	ARM_VABDsv4i16 = 2039,
	ARM_VABDsv4i32 = 2040,
	ARM_VABDsv8i16 = 2041,
	ARM_VABDsv8i8 = 2042,
	ARM_VABDuv16i8 = 2043,
	ARM_VABDuv2i32 = 2044,
	ARM_VABDuv4i16 = 2045,
	ARM_VABDuv4i32 = 2046,
	ARM_VABDuv8i16 = 2047,
	ARM_VABDuv8i8 = 2048,
	ARM_VABSD = 2049,
	ARM_VABSH = 2050,
	ARM_VABSS = 2051,
	ARM_VABSfd = 2052,
	ARM_VABSfq = 2053,
	ARM_VABShd = 2054,
	ARM_VABShq = 2055,
	ARM_VABSv16i8 = 2056,
	ARM_VABSv2i32 = 2057,
	ARM_VABSv4i16 = 2058,
	ARM_VABSv4i32 = 2059,
	ARM_VABSv8i16 = 2060,
	ARM_VABSv8i8 = 2061,
	ARM_VACGEfd = 2062,
	ARM_VACGEfq = 2063,
	ARM_VACGEhd = 2064,
	ARM_VACGEhq = 2065,
	ARM_VACGTfd = 2066,
	ARM_VACGTfq = 2067,
	ARM_VACGThd = 2068,
	ARM_VACGThq = 2069,
	ARM_VADDD = 2070,
	ARM_VADDH = 2071,
	ARM_VADDHNv2i32 = 2072,
	ARM_VADDHNv4i16 = 2073,
	ARM_VADDHNv8i8 = 2074,
	ARM_VADDLsv2i64 = 2075,
	ARM_VADDLsv4i32 = 2076,
	ARM_VADDLsv8i16 = 2077,
	ARM_VADDLuv2i64 = 2078,
	ARM_VADDLuv4i32 = 2079,
	ARM_VADDLuv8i16 = 2080,
	ARM_VADDS = 2081,
	ARM_VADDWsv2i64 = 2082,
	ARM_VADDWsv4i32 = 2083,
	ARM_VADDWsv8i16 = 2084,
	ARM_VADDWuv2i64 = 2085,
	ARM_VADDWuv4i32 = 2086,
	ARM_VADDWuv8i16 = 2087,
	ARM_VADDfd = 2088,
	ARM_VADDfq = 2089,
	ARM_VADDhd = 2090,
	ARM_VADDhq = 2091,
	ARM_VADDv16i8 = 2092,
	ARM_VADDv1i64 = 2093,
	ARM_VADDv2i32 = 2094,
	ARM_VADDv2i64 = 2095,
	ARM_VADDv4i16 = 2096,
	ARM_VADDv4i32 = 2097,
	ARM_VADDv8i16 = 2098,
	ARM_VADDv8i8 = 2099,
	ARM_VANDd = 2100,
	ARM_VANDq = 2101,
	ARM_VBF16MALBQ = 2102,
	ARM_VBF16MALBQI = 2103,
	ARM_VBF16MALTQ = 2104,
	ARM_VBF16MALTQI = 2105,
	ARM_VBICd = 2106,
	ARM_VBICiv2i32 = 2107,
	ARM_VBICiv4i16 = 2108,
	ARM_VBICiv4i32 = 2109,
	ARM_VBICiv8i16 = 2110,
	ARM_VBICq = 2111,
	ARM_VBIFd = 2112,
	ARM_VBIFq = 2113,
	ARM_VBITd = 2114,
	ARM_VBITq = 2115,
	ARM_VBSLd = 2116,
	ARM_VBSLq = 2117,
	ARM_VBSPd = 2118,
	ARM_VBSPq = 2119,
	ARM_VCADDv2f32 = 2120,
	ARM_VCADDv4f16 = 2121,
	ARM_VCADDv4f32 = 2122,
	ARM_VCADDv8f16 = 2123,
	ARM_VCEQfd = 2124,
	ARM_VCEQfq = 2125,
	ARM_VCEQhd = 2126,
	ARM_VCEQhq = 2127,
	ARM_VCEQv16i8 = 2128,
	ARM_VCEQv2i32 = 2129,
	ARM_VCEQv4i16 = 2130,
	ARM_VCEQv4i32 = 2131,
	ARM_VCEQv8i16 = 2132,
	ARM_VCEQv8i8 = 2133,
	ARM_VCEQzv16i8 = 2134,
	ARM_VCEQzv2f32 = 2135,
	ARM_VCEQzv2i32 = 2136,
	ARM_VCEQzv4f16 = 2137,
	ARM_VCEQzv4f32 = 2138,
	ARM_VCEQzv4i16 = 2139,
	ARM_VCEQzv4i32 = 2140,
	ARM_VCEQzv8f16 = 2141,
	ARM_VCEQzv8i16 = 2142,
	ARM_VCEQzv8i8 = 2143,
	ARM_VCGEfd = 2144,
	ARM_VCGEfq = 2145,
	ARM_VCGEhd = 2146,
	ARM_VCGEhq = 2147,
	ARM_VCGEsv16i8 = 2148,
	ARM_VCGEsv2i32 = 2149,
	ARM_VCGEsv4i16 = 2150,
	ARM_VCGEsv4i32 = 2151,
	ARM_VCGEsv8i16 = 2152,
	ARM_VCGEsv8i8 = 2153,
	ARM_VCGEuv16i8 = 2154,
	ARM_VCGEuv2i32 = 2155,
	ARM_VCGEuv4i16 = 2156,
	ARM_VCGEuv4i32 = 2157,
	ARM_VCGEuv8i16 = 2158,
	ARM_VCGEuv8i8 = 2159,
	ARM_VCGEzv16i8 = 2160,
	ARM_VCGEzv2f32 = 2161,
	ARM_VCGEzv2i32 = 2162,
	ARM_VCGEzv4f16 = 2163,
	ARM_VCGEzv4f32 = 2164,
	ARM_VCGEzv4i16 = 2165,
	ARM_VCGEzv4i32 = 2166,
	ARM_VCGEzv8f16 = 2167,
	ARM_VCGEzv8i16 = 2168,
	ARM_VCGEzv8i8 = 2169,
	ARM_VCGTfd = 2170,
	ARM_VCGTfq = 2171,
	ARM_VCGThd = 2172,
	ARM_VCGThq = 2173,
	ARM_VCGTsv16i8 = 2174,
	ARM_VCGTsv2i32 = 2175,
	ARM_VCGTsv4i16 = 2176,
	ARM_VCGTsv4i32 = 2177,
	ARM_VCGTsv8i16 = 2178,
	ARM_VCGTsv8i8 = 2179,
	ARM_VCGTuv16i8 = 2180,
	ARM_VCGTuv2i32 = 2181,
	ARM_VCGTuv4i16 = 2182,
	ARM_VCGTuv4i32 = 2183,
	ARM_VCGTuv8i16 = 2184,
	ARM_VCGTuv8i8 = 2185,
	ARM_VCGTzv16i8 = 2186,
	ARM_VCGTzv2f32 = 2187,
	ARM_VCGTzv2i32 = 2188,
	ARM_VCGTzv4f16 = 2189,
	ARM_VCGTzv4f32 = 2190,
	ARM_VCGTzv4i16 = 2191,
	ARM_VCGTzv4i32 = 2192,
	ARM_VCGTzv8f16 = 2193,
	ARM_VCGTzv8i16 = 2194,
	ARM_VCGTzv8i8 = 2195,
	ARM_VCLEzv16i8 = 2196,
	ARM_VCLEzv2f32 = 2197,
	ARM_VCLEzv2i32 = 2198,
	ARM_VCLEzv4f16 = 2199,
	ARM_VCLEzv4f32 = 2200,
	ARM_VCLEzv4i16 = 2201,
	ARM_VCLEzv4i32 = 2202,
	ARM_VCLEzv8f16 = 2203,
	ARM_VCLEzv8i16 = 2204,
	ARM_VCLEzv8i8 = 2205,
	ARM_VCLSv16i8 = 2206,
	ARM_VCLSv2i32 = 2207,
	ARM_VCLSv4i16 = 2208,
	ARM_VCLSv4i32 = 2209,
	ARM_VCLSv8i16 = 2210,
	ARM_VCLSv8i8 = 2211,
	ARM_VCLTzv16i8 = 2212,
	ARM_VCLTzv2f32 = 2213,
	ARM_VCLTzv2i32 = 2214,
	ARM_VCLTzv4f16 = 2215,
	ARM_VCLTzv4f32 = 2216,
	ARM_VCLTzv4i16 = 2217,
	ARM_VCLTzv4i32 = 2218,
	ARM_VCLTzv8f16 = 2219,
	ARM_VCLTzv8i16 = 2220,
	ARM_VCLTzv8i8 = 2221,
	ARM_VCLZv16i8 = 2222,
	ARM_VCLZv2i32 = 2223,
	ARM_VCLZv4i16 = 2224,
	ARM_VCLZv4i32 = 2225,
	ARM_VCLZv8i16 = 2226,
	ARM_VCLZv8i8 = 2227,
	ARM_VCMLAv2f32 = 2228,
	ARM_VCMLAv2f32_indexed = 2229,
	ARM_VCMLAv4f16 = 2230,
	ARM_VCMLAv4f16_indexed = 2231,
	ARM_VCMLAv4f32 = 2232,
	ARM_VCMLAv4f32_indexed = 2233,
	ARM_VCMLAv8f16 = 2234,
	ARM_VCMLAv8f16_indexed = 2235,
	ARM_VCMPD = 2236,
	ARM_VCMPED = 2237,
	ARM_VCMPEH = 2238,
	ARM_VCMPES = 2239,
	ARM_VCMPEZD = 2240,
	ARM_VCMPEZH = 2241,
	ARM_VCMPEZS = 2242,
	ARM_VCMPH = 2243,
	ARM_VCMPS = 2244,
	ARM_VCMPZD = 2245,
	ARM_VCMPZH = 2246,
	ARM_VCMPZS = 2247,
	ARM_VCNTd = 2248,
	ARM_VCNTq = 2249,
	ARM_VCVTANSDf = 2250,
	ARM_VCVTANSDh = 2251,
	ARM_VCVTANSQf = 2252,
	ARM_VCVTANSQh = 2253,
	ARM_VCVTANUDf = 2254,
	ARM_VCVTANUDh = 2255,
	ARM_VCVTANUQf = 2256,
	ARM_VCVTANUQh = 2257,
	ARM_VCVTASD = 2258,
	ARM_VCVTASH = 2259,
	ARM_VCVTASS = 2260,
	ARM_VCVTAUD = 2261,
	ARM_VCVTAUH = 2262,
	ARM_VCVTAUS = 2263,
	ARM_VCVTBDH = 2264,
	ARM_VCVTBHD = 2265,
	ARM_VCVTBHS = 2266,
	ARM_VCVTBSH = 2267,
	ARM_VCVTDS = 2268,
	ARM_VCVTMNSDf = 2269,
	ARM_VCVTMNSDh = 2270,
	ARM_VCVTMNSQf = 2271,
	ARM_VCVTMNSQh = 2272,
	ARM_VCVTMNUDf = 2273,
	ARM_VCVTMNUDh = 2274,
	ARM_VCVTMNUQf = 2275,
	ARM_VCVTMNUQh = 2276,
	ARM_VCVTMSD = 2277,
	ARM_VCVTMSH = 2278,
	ARM_VCVTMSS = 2279,
	ARM_VCVTMUD = 2280,
	ARM_VCVTMUH = 2281,
	ARM_VCVTMUS = 2282,
	ARM_VCVTNNSDf = 2283,
	ARM_VCVTNNSDh = 2284,
	ARM_VCVTNNSQf = 2285,
	ARM_VCVTNNSQh = 2286,
	ARM_VCVTNNUDf = 2287,
	ARM_VCVTNNUDh = 2288,
	ARM_VCVTNNUQf = 2289,
	ARM_VCVTNNUQh = 2290,
	ARM_VCVTNSD = 2291,
	ARM_VCVTNSH = 2292,
	ARM_VCVTNSS = 2293,
	ARM_VCVTNUD = 2294,
	ARM_VCVTNUH = 2295,
	ARM_VCVTNUS = 2296,
	ARM_VCVTPNSDf = 2297,
	ARM_VCVTPNSDh = 2298,
	ARM_VCVTPNSQf = 2299,
	ARM_VCVTPNSQh = 2300,
	ARM_VCVTPNUDf = 2301,
	ARM_VCVTPNUDh = 2302,
	ARM_VCVTPNUQf = 2303,
	ARM_VCVTPNUQh = 2304,
	ARM_VCVTPSD = 2305,
	ARM_VCVTPSH = 2306,
	ARM_VCVTPSS = 2307,
	ARM_VCVTPUD = 2308,
	ARM_VCVTPUH = 2309,
	ARM_VCVTPUS = 2310,
	ARM_VCVTSD = 2311,
	ARM_VCVTTDH = 2312,
	ARM_VCVTTHD = 2313,
	ARM_VCVTTHS = 2314,
	ARM_VCVTTSH = 2315,
	ARM_VCVTf2h = 2316,
	ARM_VCVTf2sd = 2317,
	ARM_VCVTf2sq = 2318,
	ARM_VCVTf2ud = 2319,
	ARM_VCVTf2uq = 2320,
	ARM_VCVTf2xsd = 2321,
	ARM_VCVTf2xsq = 2322,
	ARM_VCVTf2xud = 2323,
	ARM_VCVTf2xuq = 2324,
	ARM_VCVTh2f = 2325,
	ARM_VCVTh2sd = 2326,
	ARM_VCVTh2sq = 2327,
	ARM_VCVTh2ud = 2328,
	ARM_VCVTh2uq = 2329,
	ARM_VCVTh2xsd = 2330,
	ARM_VCVTh2xsq = 2331,
	ARM_VCVTh2xud = 2332,
	ARM_VCVTh2xuq = 2333,
	ARM_VCVTs2fd = 2334,
	ARM_VCVTs2fq = 2335,
	ARM_VCVTs2hd = 2336,
	ARM_VCVTs2hq = 2337,
	ARM_VCVTu2fd = 2338,
	ARM_VCVTu2fq = 2339,
	ARM_VCVTu2hd = 2340,
	ARM_VCVTu2hq = 2341,
	ARM_VCVTxs2fd = 2342,
	ARM_VCVTxs2fq = 2343,
	ARM_VCVTxs2hd = 2344,
	ARM_VCVTxs2hq = 2345,
	ARM_VCVTxu2fd = 2346,
	ARM_VCVTxu2fq = 2347,
	ARM_VCVTxu2hd = 2348,
	ARM_VCVTxu2hq = 2349,
	ARM_VDIVD = 2350,
	ARM_VDIVH = 2351,
	ARM_VDIVS = 2352,
	ARM_VDUP16d = 2353,
	ARM_VDUP16q = 2354,
	ARM_VDUP32d = 2355,
	ARM_VDUP32q = 2356,
	ARM_VDUP8d = 2357,
	ARM_VDUP8q = 2358,
	ARM_VDUPLN16d = 2359,
	ARM_VDUPLN16q = 2360,
	ARM_VDUPLN32d = 2361,
	ARM_VDUPLN32q = 2362,
	ARM_VDUPLN8d = 2363,
	ARM_VDUPLN8q = 2364,
	ARM_VEORd = 2365,
	ARM_VEORq = 2366,
	ARM_VEXTd16 = 2367,
	ARM_VEXTd32 = 2368,
	ARM_VEXTd8 = 2369,
	ARM_VEXTq16 = 2370,
	ARM_VEXTq32 = 2371,
	ARM_VEXTq64 = 2372,
	ARM_VEXTq8 = 2373,
	ARM_VFMAD = 2374,
	ARM_VFMAH = 2375,
	ARM_VFMALD = 2376,
	ARM_VFMALDI = 2377,
	ARM_VFMALQ = 2378,
	ARM_VFMALQI = 2379,
	ARM_VFMAS = 2380,
	ARM_VFMAfd = 2381,
	ARM_VFMAfq = 2382,
	ARM_VFMAhd = 2383,
	ARM_VFMAhq = 2384,
	ARM_VFMSD = 2385,
	ARM_VFMSH = 2386,
	ARM_VFMSLD = 2387,
	ARM_VFMSLDI = 2388,
	ARM_VFMSLQ = 2389,
	ARM_VFMSLQI = 2390,
	ARM_VFMSS = 2391,
	ARM_VFMSfd = 2392,
	ARM_VFMSfq = 2393,
	ARM_VFMShd = 2394,
	ARM_VFMShq = 2395,
	ARM_VFNMAD = 2396,
	ARM_VFNMAH = 2397,
	ARM_VFNMAS = 2398,
	ARM_VFNMSD = 2399,
	ARM_VFNMSH = 2400,
	ARM_VFNMSS = 2401,
	ARM_VFP_VMAXNMD = 2402,
	ARM_VFP_VMAXNMH = 2403,
	ARM_VFP_VMAXNMS = 2404,
	ARM_VFP_VMINNMD = 2405,
	ARM_VFP_VMINNMH = 2406,
	ARM_VFP_VMINNMS = 2407,
	ARM_VGETLNi32 = 2408,
	ARM_VGETLNs16 = 2409,
	ARM_VGETLNs8 = 2410,
	ARM_VGETLNu16 = 2411,
	ARM_VGETLNu8 = 2412,
	ARM_VHADDsv16i8 = 2413,
	ARM_VHADDsv2i32 = 2414,
	ARM_VHADDsv4i16 = 2415,
	ARM_VHADDsv4i32 = 2416,
	ARM_VHADDsv8i16 = 2417,
	ARM_VHADDsv8i8 = 2418,
	ARM_VHADDuv16i8 = 2419,
	ARM_VHADDuv2i32 = 2420,
	ARM_VHADDuv4i16 = 2421,
	ARM_VHADDuv4i32 = 2422,
	ARM_VHADDuv8i16 = 2423,
	ARM_VHADDuv8i8 = 2424,
	ARM_VHSUBsv16i8 = 2425,
	ARM_VHSUBsv2i32 = 2426,
	ARM_VHSUBsv4i16 = 2427,
	ARM_VHSUBsv4i32 = 2428,
	ARM_VHSUBsv8i16 = 2429,
	ARM_VHSUBsv8i8 = 2430,
	ARM_VHSUBuv16i8 = 2431,
	ARM_VHSUBuv2i32 = 2432,
	ARM_VHSUBuv4i16 = 2433,
	ARM_VHSUBuv4i32 = 2434,
	ARM_VHSUBuv8i16 = 2435,
	ARM_VHSUBuv8i8 = 2436,
	ARM_VINSH = 2437,
	ARM_VJCVT = 2438,
	ARM_VLD1DUPd16 = 2439,
	ARM_VLD1DUPd16wb_fixed = 2440,
	ARM_VLD1DUPd16wb_register = 2441,
	ARM_VLD1DUPd32 = 2442,
	ARM_VLD1DUPd32wb_fixed = 2443,
	ARM_VLD1DUPd32wb_register = 2444,
	ARM_VLD1DUPd8 = 2445,
	ARM_VLD1DUPd8wb_fixed = 2446,
	ARM_VLD1DUPd8wb_register = 2447,
	ARM_VLD1DUPq16 = 2448,
	ARM_VLD1DUPq16wb_fixed = 2449,
	ARM_VLD1DUPq16wb_register = 2450,
	ARM_VLD1DUPq32 = 2451,
	ARM_VLD1DUPq32wb_fixed = 2452,
	ARM_VLD1DUPq32wb_register = 2453,
	ARM_VLD1DUPq8 = 2454,
	ARM_VLD1DUPq8wb_fixed = 2455,
	ARM_VLD1DUPq8wb_register = 2456,
	ARM_VLD1LNd16 = 2457,
	ARM_VLD1LNd16_UPD = 2458,
	ARM_VLD1LNd32 = 2459,
	ARM_VLD1LNd32_UPD = 2460,
	ARM_VLD1LNd8 = 2461,
	ARM_VLD1LNd8_UPD = 2462,
	ARM_VLD1LNq16Pseudo = 2463,
	ARM_VLD1LNq16Pseudo_UPD = 2464,
	ARM_VLD1LNq32Pseudo = 2465,
	ARM_VLD1LNq32Pseudo_UPD = 2466,
	ARM_VLD1LNq8Pseudo = 2467,
	ARM_VLD1LNq8Pseudo_UPD = 2468,
	ARM_VLD1d16 = 2469,
	ARM_VLD1d16Q = 2470,
	ARM_VLD1d16QPseudo = 2471,
	ARM_VLD1d16QPseudoWB_fixed = 2472,
	ARM_VLD1d16QPseudoWB_register = 2473,
	ARM_VLD1d16Qwb_fixed = 2474,
	ARM_VLD1d16Qwb_register = 2475,
	ARM_VLD1d16T = 2476,
	ARM_VLD1d16TPseudo = 2477,
	ARM_VLD1d16TPseudoWB_fixed = 2478,
	ARM_VLD1d16TPseudoWB_register = 2479,
	ARM_VLD1d16Twb_fixed = 2480,
	ARM_VLD1d16Twb_register = 2481,
	ARM_VLD1d16wb_fixed = 2482,
	ARM_VLD1d16wb_register = 2483,
	ARM_VLD1d32 = 2484,
	ARM_VLD1d32Q = 2485,
	ARM_VLD1d32QPseudo = 2486,
	ARM_VLD1d32QPseudoWB_fixed = 2487,
	ARM_VLD1d32QPseudoWB_register = 2488,
	ARM_VLD1d32Qwb_fixed = 2489,
	ARM_VLD1d32Qwb_register = 2490,
	ARM_VLD1d32T = 2491,
	ARM_VLD1d32TPseudo = 2492,
	ARM_VLD1d32TPseudoWB_fixed = 2493,
	ARM_VLD1d32TPseudoWB_register = 2494,
	ARM_VLD1d32Twb_fixed = 2495,
	ARM_VLD1d32Twb_register = 2496,
	ARM_VLD1d32wb_fixed = 2497,
	ARM_VLD1d32wb_register = 2498,
	ARM_VLD1d64 = 2499,
	ARM_VLD1d64Q = 2500,
	ARM_VLD1d64QPseudo = 2501,
	ARM_VLD1d64QPseudoWB_fixed = 2502,
	ARM_VLD1d64QPseudoWB_register = 2503,
	ARM_VLD1d64Qwb_fixed = 2504,
	ARM_VLD1d64Qwb_register = 2505,
	ARM_VLD1d64T = 2506,
	ARM_VLD1d64TPseudo = 2507,
	ARM_VLD1d64TPseudoWB_fixed = 2508,
	ARM_VLD1d64TPseudoWB_register = 2509,
	ARM_VLD1d64Twb_fixed = 2510,
	ARM_VLD1d64Twb_register = 2511,
	ARM_VLD1d64wb_fixed = 2512,
	ARM_VLD1d64wb_register = 2513,
	ARM_VLD1d8 = 2514,
	ARM_VLD1d8Q = 2515,
	ARM_VLD1d8QPseudo = 2516,
	ARM_VLD1d8QPseudoWB_fixed = 2517,
	ARM_VLD1d8QPseudoWB_register = 2518,
	ARM_VLD1d8Qwb_fixed = 2519,
	ARM_VLD1d8Qwb_register = 2520,
	ARM_VLD1d8T = 2521,
	ARM_VLD1d8TPseudo = 2522,
	ARM_VLD1d8TPseudoWB_fixed = 2523,
	ARM_VLD1d8TPseudoWB_register = 2524,
	ARM_VLD1d8Twb_fixed = 2525,
	ARM_VLD1d8Twb_register = 2526,
	ARM_VLD1d8wb_fixed = 2527,
	ARM_VLD1d8wb_register = 2528,
	ARM_VLD1q16 = 2529,
	ARM_VLD1q16HighQPseudo = 2530,
	ARM_VLD1q16HighQPseudo_UPD = 2531,
	ARM_VLD1q16HighTPseudo = 2532,
	ARM_VLD1q16HighTPseudo_UPD = 2533,
	ARM_VLD1q16LowQPseudo_UPD = 2534,
	ARM_VLD1q16LowTPseudo_UPD = 2535,
	ARM_VLD1q16wb_fixed = 2536,
	ARM_VLD1q16wb_register = 2537,
	ARM_VLD1q32 = 2538,
	ARM_VLD1q32HighQPseudo = 2539,
	ARM_VLD1q32HighQPseudo_UPD = 2540,
	ARM_VLD1q32HighTPseudo = 2541,
	ARM_VLD1q32HighTPseudo_UPD = 2542,
	ARM_VLD1q32LowQPseudo_UPD = 2543,
	ARM_VLD1q32LowTPseudo_UPD = 2544,
	ARM_VLD1q32wb_fixed = 2545,
	ARM_VLD1q32wb_register = 2546,
	ARM_VLD1q64 = 2547,
	ARM_VLD1q64HighQPseudo = 2548,
	ARM_VLD1q64HighQPseudo_UPD = 2549,
	ARM_VLD1q64HighTPseudo = 2550,
	ARM_VLD1q64HighTPseudo_UPD = 2551,
	ARM_VLD1q64LowQPseudo_UPD = 2552,
	ARM_VLD1q64LowTPseudo_UPD = 2553,
	ARM_VLD1q64wb_fixed = 2554,
	ARM_VLD1q64wb_register = 2555,
	ARM_VLD1q8 = 2556,
	ARM_VLD1q8HighQPseudo = 2557,
	ARM_VLD1q8HighQPseudo_UPD = 2558,
	ARM_VLD1q8HighTPseudo = 2559,
	ARM_VLD1q8HighTPseudo_UPD = 2560,
	ARM_VLD1q8LowQPseudo_UPD = 2561,
	ARM_VLD1q8LowTPseudo_UPD = 2562,
	ARM_VLD1q8wb_fixed = 2563,
	ARM_VLD1q8wb_register = 2564,
	ARM_VLD2DUPd16 = 2565,
	ARM_VLD2DUPd16wb_fixed = 2566,
	ARM_VLD2DUPd16wb_register = 2567,
	ARM_VLD2DUPd16x2 = 2568,
	ARM_VLD2DUPd16x2wb_fixed = 2569,
	ARM_VLD2DUPd16x2wb_register = 2570,
	ARM_VLD2DUPd32 = 2571,
	ARM_VLD2DUPd32wb_fixed = 2572,
	ARM_VLD2DUPd32wb_register = 2573,
	ARM_VLD2DUPd32x2 = 2574,
	ARM_VLD2DUPd32x2wb_fixed = 2575,
	ARM_VLD2DUPd32x2wb_register = 2576,
	ARM_VLD2DUPd8 = 2577,
	ARM_VLD2DUPd8wb_fixed = 2578,
	ARM_VLD2DUPd8wb_register = 2579,
	ARM_VLD2DUPd8x2 = 2580,
	ARM_VLD2DUPd8x2wb_fixed = 2581,
	ARM_VLD2DUPd8x2wb_register = 2582,
	ARM_VLD2DUPq16EvenPseudo = 2583,
	ARM_VLD2DUPq16OddPseudo = 2584,
	ARM_VLD2DUPq16OddPseudoWB_fixed = 2585,
	ARM_VLD2DUPq16OddPseudoWB_register = 2586,
	ARM_VLD2DUPq32EvenPseudo = 2587,
	ARM_VLD2DUPq32OddPseudo = 2588,
	ARM_VLD2DUPq32OddPseudoWB_fixed = 2589,
	ARM_VLD2DUPq32OddPseudoWB_register = 2590,
	ARM_VLD2DUPq8EvenPseudo = 2591,
	ARM_VLD2DUPq8OddPseudo = 2592,
	ARM_VLD2DUPq8OddPseudoWB_fixed = 2593,
	ARM_VLD2DUPq8OddPseudoWB_register = 2594,
	ARM_VLD2LNd16 = 2595,
	ARM_VLD2LNd16Pseudo = 2596,
	ARM_VLD2LNd16Pseudo_UPD = 2597,
	ARM_VLD2LNd16_UPD = 2598,
	ARM_VLD2LNd32 = 2599,
	ARM_VLD2LNd32Pseudo = 2600,
	ARM_VLD2LNd32Pseudo_UPD = 2601,
	ARM_VLD2LNd32_UPD = 2602,
	ARM_VLD2LNd8 = 2603,
	ARM_VLD2LNd8Pseudo = 2604,
	ARM_VLD2LNd8Pseudo_UPD = 2605,
	ARM_VLD2LNd8_UPD = 2606,
	ARM_VLD2LNq16 = 2607,
	ARM_VLD2LNq16Pseudo = 2608,
	ARM_VLD2LNq16Pseudo_UPD = 2609,
	ARM_VLD2LNq16_UPD = 2610,
	ARM_VLD2LNq32 = 2611,
	ARM_VLD2LNq32Pseudo = 2612,
	ARM_VLD2LNq32Pseudo_UPD = 2613,
	ARM_VLD2LNq32_UPD = 2614,
	ARM_VLD2b16 = 2615,
	ARM_VLD2b16wb_fixed = 2616,
	ARM_VLD2b16wb_register = 2617,
	ARM_VLD2b32 = 2618,
	ARM_VLD2b32wb_fixed = 2619,
	ARM_VLD2b32wb_register = 2620,
	ARM_VLD2b8 = 2621,
	ARM_VLD2b8wb_fixed = 2622,
	ARM_VLD2b8wb_register = 2623,
	ARM_VLD2d16 = 2624,
	ARM_VLD2d16wb_fixed = 2625,
	ARM_VLD2d16wb_register = 2626,
	ARM_VLD2d32 = 2627,
	ARM_VLD2d32wb_fixed = 2628,
	ARM_VLD2d32wb_register = 2629,
	ARM_VLD2d8 = 2630,
	ARM_VLD2d8wb_fixed = 2631,
	ARM_VLD2d8wb_register = 2632,
	ARM_VLD2q16 = 2633,
	ARM_VLD2q16Pseudo = 2634,
	ARM_VLD2q16PseudoWB_fixed = 2635,
	ARM_VLD2q16PseudoWB_register = 2636,
	ARM_VLD2q16wb_fixed = 2637,
	ARM_VLD2q16wb_register = 2638,
	ARM_VLD2q32 = 2639,
	ARM_VLD2q32Pseudo = 2640,
	ARM_VLD2q32PseudoWB_fixed = 2641,
	ARM_VLD2q32PseudoWB_register = 2642,
	ARM_VLD2q32wb_fixed = 2643,
	ARM_VLD2q32wb_register = 2644,
	ARM_VLD2q8 = 2645,
	ARM_VLD2q8Pseudo = 2646,
	ARM_VLD2q8PseudoWB_fixed = 2647,
	ARM_VLD2q8PseudoWB_register = 2648,
	ARM_VLD2q8wb_fixed = 2649,
	ARM_VLD2q8wb_register = 2650,
	ARM_VLD3DUPd16 = 2651,
	ARM_VLD3DUPd16Pseudo = 2652,
	ARM_VLD3DUPd16Pseudo_UPD = 2653,
	ARM_VLD3DUPd16_UPD = 2654,
	ARM_VLD3DUPd32 = 2655,
	ARM_VLD3DUPd32Pseudo = 2656,
	ARM_VLD3DUPd32Pseudo_UPD = 2657,
	ARM_VLD3DUPd32_UPD = 2658,
	ARM_VLD3DUPd8 = 2659,
	ARM_VLD3DUPd8Pseudo = 2660,
	ARM_VLD3DUPd8Pseudo_UPD = 2661,
	ARM_VLD3DUPd8_UPD = 2662,
	ARM_VLD3DUPq16 = 2663,
	ARM_VLD3DUPq16EvenPseudo = 2664,
	ARM_VLD3DUPq16OddPseudo = 2665,
	ARM_VLD3DUPq16OddPseudo_UPD = 2666,
	ARM_VLD3DUPq16_UPD = 2667,
	ARM_VLD3DUPq32 = 2668,
	ARM_VLD3DUPq32EvenPseudo = 2669,
	ARM_VLD3DUPq32OddPseudo = 2670,
	ARM_VLD3DUPq32OddPseudo_UPD = 2671,
	ARM_VLD3DUPq32_UPD = 2672,
	ARM_VLD3DUPq8 = 2673,
	ARM_VLD3DUPq8EvenPseudo = 2674,
	ARM_VLD3DUPq8OddPseudo = 2675,
	ARM_VLD3DUPq8OddPseudo_UPD = 2676,
	ARM_VLD3DUPq8_UPD = 2677,
	ARM_VLD3LNd16 = 2678,
	ARM_VLD3LNd16Pseudo = 2679,
	ARM_VLD3LNd16Pseudo_UPD = 2680,
	ARM_VLD3LNd16_UPD = 2681,
	ARM_VLD3LNd32 = 2682,
	ARM_VLD3LNd32Pseudo = 2683,
	ARM_VLD3LNd32Pseudo_UPD = 2684,
	ARM_VLD3LNd32_UPD = 2685,
	ARM_VLD3LNd8 = 2686,
	ARM_VLD3LNd8Pseudo = 2687,
	ARM_VLD3LNd8Pseudo_UPD = 2688,
	ARM_VLD3LNd8_UPD = 2689,
	ARM_VLD3LNq16 = 2690,
	ARM_VLD3LNq16Pseudo = 2691,
	ARM_VLD3LNq16Pseudo_UPD = 2692,
	ARM_VLD3LNq16_UPD = 2693,
	ARM_VLD3LNq32 = 2694,
	ARM_VLD3LNq32Pseudo = 2695,
	ARM_VLD3LNq32Pseudo_UPD = 2696,
	ARM_VLD3LNq32_UPD = 2697,
	ARM_VLD3d16 = 2698,
	ARM_VLD3d16Pseudo = 2699,
	ARM_VLD3d16Pseudo_UPD = 2700,
	ARM_VLD3d16_UPD = 2701,
	ARM_VLD3d32 = 2702,
	ARM_VLD3d32Pseudo = 2703,
	ARM_VLD3d32Pseudo_UPD = 2704,
	ARM_VLD3d32_UPD = 2705,
	ARM_VLD3d8 = 2706,
	ARM_VLD3d8Pseudo = 2707,
	ARM_VLD3d8Pseudo_UPD = 2708,
	ARM_VLD3d8_UPD = 2709,
	ARM_VLD3q16 = 2710,
	ARM_VLD3q16Pseudo_UPD = 2711,
	ARM_VLD3q16_UPD = 2712,
	ARM_VLD3q16oddPseudo = 2713,
	ARM_VLD3q16oddPseudo_UPD = 2714,
	ARM_VLD3q32 = 2715,
	ARM_VLD3q32Pseudo_UPD = 2716,
	ARM_VLD3q32_UPD = 2717,
	ARM_VLD3q32oddPseudo = 2718,
	ARM_VLD3q32oddPseudo_UPD = 2719,
	ARM_VLD3q8 = 2720,
	ARM_VLD3q8Pseudo_UPD = 2721,
	ARM_VLD3q8_UPD = 2722,
	ARM_VLD3q8oddPseudo = 2723,
	ARM_VLD3q8oddPseudo_UPD = 2724,
	ARM_VLD4DUPd16 = 2725,
	ARM_VLD4DUPd16Pseudo = 2726,
	ARM_VLD4DUPd16Pseudo_UPD = 2727,
	ARM_VLD4DUPd16_UPD = 2728,
	ARM_VLD4DUPd32 = 2729,
	ARM_VLD4DUPd32Pseudo = 2730,
	ARM_VLD4DUPd32Pseudo_UPD = 2731,
	ARM_VLD4DUPd32_UPD = 2732,
	ARM_VLD4DUPd8 = 2733,
	ARM_VLD4DUPd8Pseudo = 2734,
	ARM_VLD4DUPd8Pseudo_UPD = 2735,
	ARM_VLD4DUPd8_UPD = 2736,
	ARM_VLD4DUPq16 = 2737,
	ARM_VLD4DUPq16EvenPseudo = 2738,
	ARM_VLD4DUPq16OddPseudo = 2739,
	ARM_VLD4DUPq16OddPseudo_UPD = 2740,
	ARM_VLD4DUPq16_UPD = 2741,
	ARM_VLD4DUPq32 = 2742,
	ARM_VLD4DUPq32EvenPseudo = 2743,
	ARM_VLD4DUPq32OddPseudo = 2744,
	ARM_VLD4DUPq32OddPseudo_UPD = 2745,
	ARM_VLD4DUPq32_UPD = 2746,
	ARM_VLD4DUPq8 = 2747,
	ARM_VLD4DUPq8EvenPseudo = 2748,
	ARM_VLD4DUPq8OddPseudo = 2749,
	ARM_VLD4DUPq8OddPseudo_UPD = 2750,
	ARM_VLD4DUPq8_UPD = 2751,
	ARM_VLD4LNd16 = 2752,
	ARM_VLD4LNd16Pseudo = 2753,
	ARM_VLD4LNd16Pseudo_UPD = 2754,
	ARM_VLD4LNd16_UPD = 2755,
	ARM_VLD4LNd32 = 2756,
	ARM_VLD4LNd32Pseudo = 2757,
	ARM_VLD4LNd32Pseudo_UPD = 2758,
	ARM_VLD4LNd32_UPD = 2759,
	ARM_VLD4LNd8 = 2760,
	ARM_VLD4LNd8Pseudo = 2761,
	ARM_VLD4LNd8Pseudo_UPD = 2762,
	ARM_VLD4LNd8_UPD = 2763,
	ARM_VLD4LNq16 = 2764,
	ARM_VLD4LNq16Pseudo = 2765,
	ARM_VLD4LNq16Pseudo_UPD = 2766,
	ARM_VLD4LNq16_UPD = 2767,
	ARM_VLD4LNq32 = 2768,
	ARM_VLD4LNq32Pseudo = 2769,
	ARM_VLD4LNq32Pseudo_UPD = 2770,
	ARM_VLD4LNq32_UPD = 2771,
	ARM_VLD4d16 = 2772,
	ARM_VLD4d16Pseudo = 2773,
	ARM_VLD4d16Pseudo_UPD = 2774,
	ARM_VLD4d16_UPD = 2775,
	ARM_VLD4d32 = 2776,
	ARM_VLD4d32Pseudo = 2777,
	ARM_VLD4d32Pseudo_UPD = 2778,
	ARM_VLD4d32_UPD = 2779,
	ARM_VLD4d8 = 2780,
	ARM_VLD4d8Pseudo = 2781,
	ARM_VLD4d8Pseudo_UPD = 2782,
	ARM_VLD4d8_UPD = 2783,
	ARM_VLD4q16 = 2784,
	ARM_VLD4q16Pseudo_UPD = 2785,
	ARM_VLD4q16_UPD = 2786,
	ARM_VLD4q16oddPseudo = 2787,
	ARM_VLD4q16oddPseudo_UPD = 2788,
	ARM_VLD4q32 = 2789,
	ARM_VLD4q32Pseudo_UPD = 2790,
	ARM_VLD4q32_UPD = 2791,
	ARM_VLD4q32oddPseudo = 2792,
	ARM_VLD4q32oddPseudo_UPD = 2793,
	ARM_VLD4q8 = 2794,
	ARM_VLD4q8Pseudo_UPD = 2795,
	ARM_VLD4q8_UPD = 2796,
	ARM_VLD4q8oddPseudo = 2797,
	ARM_VLD4q8oddPseudo_UPD = 2798,
	ARM_VLDMDDB_UPD = 2799,
	ARM_VLDMDIA = 2800,
	ARM_VLDMDIA_UPD = 2801,
	ARM_VLDMQIA = 2802,
	ARM_VLDMSDB_UPD = 2803,
	ARM_VLDMSIA = 2804,
	ARM_VLDMSIA_UPD = 2805,
	ARM_VLDRD = 2806,
	ARM_VLDRH = 2807,
	ARM_VLDRS = 2808,
	ARM_VLDR_FPCXTNS_off = 2809,
	ARM_VLDR_FPCXTNS_post = 2810,
	ARM_VLDR_FPCXTNS_pre = 2811,
	ARM_VLDR_FPCXTS_off = 2812,
	ARM_VLDR_FPCXTS_post = 2813,
	ARM_VLDR_FPCXTS_pre = 2814,
	ARM_VLDR_FPSCR_NZCVQC_off = 2815,
	ARM_VLDR_FPSCR_NZCVQC_post = 2816,
	ARM_VLDR_FPSCR_NZCVQC_pre = 2817,
	ARM_VLDR_FPSCR_off = 2818,
	ARM_VLDR_FPSCR_post = 2819,
	ARM_VLDR_FPSCR_pre = 2820,
	ARM_VLDR_P0_off = 2821,
	ARM_VLDR_P0_post = 2822,
	ARM_VLDR_P0_pre = 2823,
	ARM_VLDR_VPR_off = 2824,
	ARM_VLDR_VPR_post = 2825,
	ARM_VLDR_VPR_pre = 2826,
	ARM_VLLDM = 2827,
	ARM_VLSTM = 2828,
	ARM_VMAXfd = 2829,
	ARM_VMAXfq = 2830,
	ARM_VMAXhd = 2831,
	ARM_VMAXhq = 2832,
	ARM_VMAXsv16i8 = 2833,
	ARM_VMAXsv2i32 = 2834,
	ARM_VMAXsv4i16 = 2835,
	ARM_VMAXsv4i32 = 2836,
	ARM_VMAXsv8i16 = 2837,
	ARM_VMAXsv8i8 = 2838,
	ARM_VMAXuv16i8 = 2839,
	ARM_VMAXuv2i32 = 2840,
	ARM_VMAXuv4i16 = 2841,
	ARM_VMAXuv4i32 = 2842,
	ARM_VMAXuv8i16 = 2843,
	ARM_VMAXuv8i8 = 2844,
	ARM_VMINfd = 2845,
	ARM_VMINfq = 2846,
	ARM_VMINhd = 2847,
	ARM_VMINhq = 2848,
	ARM_VMINsv16i8 = 2849,
	ARM_VMINsv2i32 = 2850,
	ARM_VMINsv4i16 = 2851,
	ARM_VMINsv4i32 = 2852,
	ARM_VMINsv8i16 = 2853,
	ARM_VMINsv8i8 = 2854,
	ARM_VMINuv16i8 = 2855,
	ARM_VMINuv2i32 = 2856,
	ARM_VMINuv4i16 = 2857,
	ARM_VMINuv4i32 = 2858,
	ARM_VMINuv8i16 = 2859,
	ARM_VMINuv8i8 = 2860,
	ARM_VMLAD = 2861,
	ARM_VMLAH = 2862,
	ARM_VMLALslsv2i32 = 2863,
	ARM_VMLALslsv4i16 = 2864,
	ARM_VMLALsluv2i32 = 2865,
	ARM_VMLALsluv4i16 = 2866,
	ARM_VMLALsv2i64 = 2867,
	ARM_VMLALsv4i32 = 2868,
	ARM_VMLALsv8i16 = 2869,
	ARM_VMLALuv2i64 = 2870,
	ARM_VMLALuv4i32 = 2871,
	ARM_VMLALuv8i16 = 2872,
	ARM_VMLAS = 2873,
	ARM_VMLAfd = 2874,
	ARM_VMLAfq = 2875,
	ARM_VMLAhd = 2876,
	ARM_VMLAhq = 2877,
	ARM_VMLAslfd = 2878,
	ARM_VMLAslfq = 2879,
	ARM_VMLAslhd = 2880,
	ARM_VMLAslhq = 2881,
	ARM_VMLAslv2i32 = 2882,
	ARM_VMLAslv4i16 = 2883,
	ARM_VMLAslv4i32 = 2884,
	ARM_VMLAslv8i16 = 2885,
	ARM_VMLAv16i8 = 2886,
	ARM_VMLAv2i32 = 2887,
	ARM_VMLAv4i16 = 2888,
	ARM_VMLAv4i32 = 2889,
	ARM_VMLAv8i16 = 2890,
	ARM_VMLAv8i8 = 2891,
	ARM_VMLSD = 2892,
	ARM_VMLSH = 2893,
	ARM_VMLSLslsv2i32 = 2894,
	ARM_VMLSLslsv4i16 = 2895,
	ARM_VMLSLsluv2i32 = 2896,
	ARM_VMLSLsluv4i16 = 2897,
	ARM_VMLSLsv2i64 = 2898,
	ARM_VMLSLsv4i32 = 2899,
	ARM_VMLSLsv8i16 = 2900,
	ARM_VMLSLuv2i64 = 2901,
	ARM_VMLSLuv4i32 = 2902,
	ARM_VMLSLuv8i16 = 2903,
	ARM_VMLSS = 2904,
	ARM_VMLSfd = 2905,
	ARM_VMLSfq = 2906,
	ARM_VMLShd = 2907,
	ARM_VMLShq = 2908,
	ARM_VMLSslfd = 2909,
	ARM_VMLSslfq = 2910,
	ARM_VMLSslhd = 2911,
	ARM_VMLSslhq = 2912,
	ARM_VMLSslv2i32 = 2913,
	ARM_VMLSslv4i16 = 2914,
	ARM_VMLSslv4i32 = 2915,
	ARM_VMLSslv8i16 = 2916,
	ARM_VMLSv16i8 = 2917,
	ARM_VMLSv2i32 = 2918,
	ARM_VMLSv4i16 = 2919,
	ARM_VMLSv4i32 = 2920,
	ARM_VMLSv8i16 = 2921,
	ARM_VMLSv8i8 = 2922,
	ARM_VMMLA = 2923,
	ARM_VMOVD = 2924,
	ARM_VMOVDRR = 2925,
	ARM_VMOVH = 2926,
	ARM_VMOVHR = 2927,
	ARM_VMOVLsv2i64 = 2928,
	ARM_VMOVLsv4i32 = 2929,
	ARM_VMOVLsv8i16 = 2930,
	ARM_VMOVLuv2i64 = 2931,
	ARM_VMOVLuv4i32 = 2932,
	ARM_VMOVLuv8i16 = 2933,
	ARM_VMOVNv2i32 = 2934,
	ARM_VMOVNv4i16 = 2935,
	ARM_VMOVNv8i8 = 2936,
	ARM_VMOVRH = 2937,
	ARM_VMOVRRD = 2938,
	ARM_VMOVRRS = 2939,
	ARM_VMOVRS = 2940,
	ARM_VMOVS = 2941,
	ARM_VMOVSR = 2942,
	ARM_VMOVSRR = 2943,
	ARM_VMOVv16i8 = 2944,
	ARM_VMOVv1i64 = 2945,
	ARM_VMOVv2f32 = 2946,
	ARM_VMOVv2i32 = 2947,
	ARM_VMOVv2i64 = 2948,
	ARM_VMOVv4f32 = 2949,
	ARM_VMOVv4i16 = 2950,
	ARM_VMOVv4i32 = 2951,
	ARM_VMOVv8i16 = 2952,
	ARM_VMOVv8i8 = 2953,
	ARM_VMRS = 2954,
	ARM_VMRS_FPCXTNS = 2955,
	ARM_VMRS_FPCXTS = 2956,
	ARM_VMRS_FPEXC = 2957,
	ARM_VMRS_FPINST = 2958,
	ARM_VMRS_FPINST2 = 2959,
	ARM_VMRS_FPSCR_NZCVQC = 2960,
	ARM_VMRS_FPSID = 2961,
	ARM_VMRS_MVFR0 = 2962,
	ARM_VMRS_MVFR1 = 2963,
	ARM_VMRS_MVFR2 = 2964,
	ARM_VMRS_P0 = 2965,
	ARM_VMRS_VPR = 2966,
	ARM_VMSR = 2967,
	ARM_VMSR_FPCXTNS = 2968,
	ARM_VMSR_FPCXTS = 2969,
	ARM_VMSR_FPEXC = 2970,
	ARM_VMSR_FPINST = 2971,
	ARM_VMSR_FPINST2 = 2972,
	ARM_VMSR_FPSCR_NZCVQC = 2973,
	ARM_VMSR_FPSID = 2974,
	ARM_VMSR_P0 = 2975,
	ARM_VMSR_VPR = 2976,
	ARM_VMULD = 2977,
	ARM_VMULH = 2978,
	ARM_VMULLp64 = 2979,
	ARM_VMULLp8 = 2980,
	ARM_VMULLslsv2i32 = 2981,
	ARM_VMULLslsv4i16 = 2982,
	ARM_VMULLsluv2i32 = 2983,
	ARM_VMULLsluv4i16 = 2984,
	ARM_VMULLsv2i64 = 2985,
	ARM_VMULLsv4i32 = 2986,
	ARM_VMULLsv8i16 = 2987,
	ARM_VMULLuv2i64 = 2988,
	ARM_VMULLuv4i32 = 2989,
	ARM_VMULLuv8i16 = 2990,
	ARM_VMULS = 2991,
	ARM_VMULfd = 2992,
	ARM_VMULfq = 2993,
	ARM_VMULhd = 2994,
	ARM_VMULhq = 2995,
	ARM_VMULpd = 2996,
	ARM_VMULpq = 2997,
	ARM_VMULslfd = 2998,
	ARM_VMULslfq = 2999,
	ARM_VMULslhd = 3000,
	ARM_VMULslhq = 3001,
	ARM_VMULslv2i32 = 3002,
	ARM_VMULslv4i16 = 3003,
	ARM_VMULslv4i32 = 3004,
	ARM_VMULslv8i16 = 3005,
	ARM_VMULv16i8 = 3006,
	ARM_VMULv2i32 = 3007,
	ARM_VMULv4i16 = 3008,
	ARM_VMULv4i32 = 3009,
	ARM_VMULv8i16 = 3010,
	ARM_VMULv8i8 = 3011,
	ARM_VMVNd = 3012,
	ARM_VMVNq = 3013,
	ARM_VMVNv2i32 = 3014,
	ARM_VMVNv4i16 = 3015,
	ARM_VMVNv4i32 = 3016,
	ARM_VMVNv8i16 = 3017,
	ARM_VNEGD = 3018,
	ARM_VNEGH = 3019,
	ARM_VNEGS = 3020,
	ARM_VNEGf32q = 3021,
	ARM_VNEGfd = 3022,
	ARM_VNEGhd = 3023,
	ARM_VNEGhq = 3024,
	ARM_VNEGs16d = 3025,
	ARM_VNEGs16q = 3026,
	ARM_VNEGs32d = 3027,
	ARM_VNEGs32q = 3028,
	ARM_VNEGs8d = 3029,
	ARM_VNEGs8q = 3030,
	ARM_VNMLAD = 3031,
	ARM_VNMLAH = 3032,
	ARM_VNMLAS = 3033,
	ARM_VNMLSD = 3034,
	ARM_VNMLSH = 3035,
	ARM_VNMLSS = 3036,
	ARM_VNMULD = 3037,
	ARM_VNMULH = 3038,
	ARM_VNMULS = 3039,
	ARM_VORNd = 3040,
	ARM_VORNq = 3041,
	ARM_VORRd = 3042,
	ARM_VORRiv2i32 = 3043,
	ARM_VORRiv4i16 = 3044,
	ARM_VORRiv4i32 = 3045,
	ARM_VORRiv8i16 = 3046,
	ARM_VORRq = 3047,
	ARM_VPADALsv16i8 = 3048,
	ARM_VPADALsv2i32 = 3049,
	ARM_VPADALsv4i16 = 3050,
	ARM_VPADALsv4i32 = 3051,
	ARM_VPADALsv8i16 = 3052,
	ARM_VPADALsv8i8 = 3053,
	ARM_VPADALuv16i8 = 3054,
	ARM_VPADALuv2i32 = 3055,
	ARM_VPADALuv4i16 = 3056,
	ARM_VPADALuv4i32 = 3057,
	ARM_VPADALuv8i16 = 3058,
	ARM_VPADALuv8i8 = 3059,
	ARM_VPADDLsv16i8 = 3060,
	ARM_VPADDLsv2i32 = 3061,
	ARM_VPADDLsv4i16 = 3062,
	ARM_VPADDLsv4i32 = 3063,
	ARM_VPADDLsv8i16 = 3064,
	ARM_VPADDLsv8i8 = 3065,
	ARM_VPADDLuv16i8 = 3066,
	ARM_VPADDLuv2i32 = 3067,
	ARM_VPADDLuv4i16 = 3068,
	ARM_VPADDLuv4i32 = 3069,
	ARM_VPADDLuv8i16 = 3070,
	ARM_VPADDLuv8i8 = 3071,
	ARM_VPADDf = 3072,
	ARM_VPADDh = 3073,
	ARM_VPADDi16 = 3074,
	ARM_VPADDi32 = 3075,
	ARM_VPADDi8 = 3076,
	ARM_VPMAXf = 3077,
	ARM_VPMAXh = 3078,
	ARM_VPMAXs16 = 3079,
	ARM_VPMAXs32 = 3080,
	ARM_VPMAXs8 = 3081,
	ARM_VPMAXu16 = 3082,
	ARM_VPMAXu32 = 3083,
	ARM_VPMAXu8 = 3084,
	ARM_VPMINf = 3085,
	ARM_VPMINh = 3086,
	ARM_VPMINs16 = 3087,
	ARM_VPMINs32 = 3088,
	ARM_VPMINs8 = 3089,
	ARM_VPMINu16 = 3090,
	ARM_VPMINu32 = 3091,
	ARM_VPMINu8 = 3092,
	ARM_VQABSv16i8 = 3093,
	ARM_VQABSv2i32 = 3094,
	ARM_VQABSv4i16 = 3095,
	ARM_VQABSv4i32 = 3096,
	ARM_VQABSv8i16 = 3097,
	ARM_VQABSv8i8 = 3098,
	ARM_VQADDsv16i8 = 3099,
	ARM_VQADDsv1i64 = 3100,
	ARM_VQADDsv2i32 = 3101,
	ARM_VQADDsv2i64 = 3102,
	ARM_VQADDsv4i16 = 3103,
	ARM_VQADDsv4i32 = 3104,
	ARM_VQADDsv8i16 = 3105,
	ARM_VQADDsv8i8 = 3106,
	ARM_VQADDuv16i8 = 3107,
	ARM_VQADDuv1i64 = 3108,
	ARM_VQADDuv2i32 = 3109,
	ARM_VQADDuv2i64 = 3110,
	ARM_VQADDuv4i16 = 3111,
	ARM_VQADDuv4i32 = 3112,
	ARM_VQADDuv8i16 = 3113,
	ARM_VQADDuv8i8 = 3114,
	ARM_VQDMLALslv2i32 = 3115,
	ARM_VQDMLALslv4i16 = 3116,
	ARM_VQDMLALv2i64 = 3117,
	ARM_VQDMLALv4i32 = 3118,
	ARM_VQDMLSLslv2i32 = 3119,
	ARM_VQDMLSLslv4i16 = 3120,
	ARM_VQDMLSLv2i64 = 3121,
	ARM_VQDMLSLv4i32 = 3122,
	ARM_VQDMULHslv2i32 = 3123,
	ARM_VQDMULHslv4i16 = 3124,
	ARM_VQDMULHslv4i32 = 3125,
	ARM_VQDMULHslv8i16 = 3126,
	ARM_VQDMULHv2i32 = 3127,
	ARM_VQDMULHv4i16 = 3128,
	ARM_VQDMULHv4i32 = 3129,
	ARM_VQDMULHv8i16 = 3130,
	ARM_VQDMULLslv2i32 = 3131,
	ARM_VQDMULLslv4i16 = 3132,
	ARM_VQDMULLv2i64 = 3133,
	ARM_VQDMULLv4i32 = 3134,
	ARM_VQMOVNsuv2i32 = 3135,
	ARM_VQMOVNsuv4i16 = 3136,
	ARM_VQMOVNsuv8i8 = 3137,
	ARM_VQMOVNsv2i32 = 3138,
	ARM_VQMOVNsv4i16 = 3139,
	ARM_VQMOVNsv8i8 = 3140,
	ARM_VQMOVNuv2i32 = 3141,
	ARM_VQMOVNuv4i16 = 3142,
	ARM_VQMOVNuv8i8 = 3143,
	ARM_VQNEGv16i8 = 3144,
	ARM_VQNEGv2i32 = 3145,
	ARM_VQNEGv4i16 = 3146,
	ARM_VQNEGv4i32 = 3147,
	ARM_VQNEGv8i16 = 3148,
	ARM_VQNEGv8i8 = 3149,
	ARM_VQRDMLAHslv2i32 = 3150,
	ARM_VQRDMLAHslv4i16 = 3151,
	ARM_VQRDMLAHslv4i32 = 3152,
	ARM_VQRDMLAHslv8i16 = 3153,
	ARM_VQRDMLAHv2i32 = 3154,
	ARM_VQRDMLAHv4i16 = 3155,
	ARM_VQRDMLAHv4i32 = 3156,
	ARM_VQRDMLAHv8i16 = 3157,
	ARM_VQRDMLSHslv2i32 = 3158,
	ARM_VQRDMLSHslv4i16 = 3159,
	ARM_VQRDMLSHslv4i32 = 3160,
	ARM_VQRDMLSHslv8i16 = 3161,
	ARM_VQRDMLSHv2i32 = 3162,
	ARM_VQRDMLSHv4i16 = 3163,
	ARM_VQRDMLSHv4i32 = 3164,
	ARM_VQRDMLSHv8i16 = 3165,
	ARM_VQRDMULHslv2i32 = 3166,
	ARM_VQRDMULHslv4i16 = 3167,
	ARM_VQRDMULHslv4i32 = 3168,
	ARM_VQRDMULHslv8i16 = 3169,
	ARM_VQRDMULHv2i32 = 3170,
	ARM_VQRDMULHv4i16 = 3171,
	ARM_VQRDMULHv4i32 = 3172,
	ARM_VQRDMULHv8i16 = 3173,
	ARM_VQRSHLsv16i8 = 3174,
	ARM_VQRSHLsv1i64 = 3175,
	ARM_VQRSHLsv2i32 = 3176,
	ARM_VQRSHLsv2i64 = 3177,
	ARM_VQRSHLsv4i16 = 3178,
	ARM_VQRSHLsv4i32 = 3179,
	ARM_VQRSHLsv8i16 = 3180,
	ARM_VQRSHLsv8i8 = 3181,
	ARM_VQRSHLuv16i8 = 3182,
	ARM_VQRSHLuv1i64 = 3183,
	ARM_VQRSHLuv2i32 = 3184,
	ARM_VQRSHLuv2i64 = 3185,
	ARM_VQRSHLuv4i16 = 3186,
	ARM_VQRSHLuv4i32 = 3187,
	ARM_VQRSHLuv8i16 = 3188,
	ARM_VQRSHLuv8i8 = 3189,
	ARM_VQRSHRNsv2i32 = 3190,
	ARM_VQRSHRNsv4i16 = 3191,
	ARM_VQRSHRNsv8i8 = 3192,
	ARM_VQRSHRNuv2i32 = 3193,
	ARM_VQRSHRNuv4i16 = 3194,
	ARM_VQRSHRNuv8i8 = 3195,
	ARM_VQRSHRUNv2i32 = 3196,
	ARM_VQRSHRUNv4i16 = 3197,
	ARM_VQRSHRUNv8i8 = 3198,
	ARM_VQSHLsiv16i8 = 3199,
	ARM_VQSHLsiv1i64 = 3200,
	ARM_VQSHLsiv2i32 = 3201,
	ARM_VQSHLsiv2i64 = 3202,
	ARM_VQSHLsiv4i16 = 3203,
	ARM_VQSHLsiv4i32 = 3204,
	ARM_VQSHLsiv8i16 = 3205,
	ARM_VQSHLsiv8i8 = 3206,
	ARM_VQSHLsuv16i8 = 3207,
	ARM_VQSHLsuv1i64 = 3208,
	ARM_VQSHLsuv2i32 = 3209,
	ARM_VQSHLsuv2i64 = 3210,
	ARM_VQSHLsuv4i16 = 3211,
	ARM_VQSHLsuv4i32 = 3212,
	ARM_VQSHLsuv8i16 = 3213,
	ARM_VQSHLsuv8i8 = 3214,
	ARM_VQSHLsv16i8 = 3215,
	ARM_VQSHLsv1i64 = 3216,
	ARM_VQSHLsv2i32 = 3217,
	ARM_VQSHLsv2i64 = 3218,
	ARM_VQSHLsv4i16 = 3219,
	ARM_VQSHLsv4i32 = 3220,
	ARM_VQSHLsv8i16 = 3221,
	ARM_VQSHLsv8i8 = 3222,
	ARM_VQSHLuiv16i8 = 3223,
	ARM_VQSHLuiv1i64 = 3224,
	ARM_VQSHLuiv2i32 = 3225,
	ARM_VQSHLuiv2i64 = 3226,
	ARM_VQSHLuiv4i16 = 3227,
	ARM_VQSHLuiv4i32 = 3228,
	ARM_VQSHLuiv8i16 = 3229,
	ARM_VQSHLuiv8i8 = 3230,
	ARM_VQSHLuv16i8 = 3231,
	ARM_VQSHLuv1i64 = 3232,
	ARM_VQSHLuv2i32 = 3233,
	ARM_VQSHLuv2i64 = 3234,
	ARM_VQSHLuv4i16 = 3235,
	ARM_VQSHLuv4i32 = 3236,
	ARM_VQSHLuv8i16 = 3237,
	ARM_VQSHLuv8i8 = 3238,
	ARM_VQSHRNsv2i32 = 3239,
	ARM_VQSHRNsv4i16 = 3240,
	ARM_VQSHRNsv8i8 = 3241,
	ARM_VQSHRNuv2i32 = 3242,
	ARM_VQSHRNuv4i16 = 3243,
	ARM_VQSHRNuv8i8 = 3244,
	ARM_VQSHRUNv2i32 = 3245,
	ARM_VQSHRUNv4i16 = 3246,
	ARM_VQSHRUNv8i8 = 3247,
	ARM_VQSUBsv16i8 = 3248,
	ARM_VQSUBsv1i64 = 3249,
	ARM_VQSUBsv2i32 = 3250,
	ARM_VQSUBsv2i64 = 3251,
	ARM_VQSUBsv4i16 = 3252,
	ARM_VQSUBsv4i32 = 3253,
	ARM_VQSUBsv8i16 = 3254,
	ARM_VQSUBsv8i8 = 3255,
	ARM_VQSUBuv16i8 = 3256,
	ARM_VQSUBuv1i64 = 3257,
	ARM_VQSUBuv2i32 = 3258,
	ARM_VQSUBuv2i64 = 3259,
	ARM_VQSUBuv4i16 = 3260,
	ARM_VQSUBuv4i32 = 3261,
	ARM_VQSUBuv8i16 = 3262,
	ARM_VQSUBuv8i8 = 3263,
	ARM_VRADDHNv2i32 = 3264,
	ARM_VRADDHNv4i16 = 3265,
	ARM_VRADDHNv8i8 = 3266,
	ARM_VRECPEd = 3267,
	ARM_VRECPEfd = 3268,
	ARM_VRECPEfq = 3269,
	ARM_VRECPEhd = 3270,
	ARM_VRECPEhq = 3271,
	ARM_VRECPEq = 3272,
	ARM_VRECPSfd = 3273,
	ARM_VRECPSfq = 3274,
	ARM_VRECPShd = 3275,
	ARM_VRECPShq = 3276,
	ARM_VREV16d8 = 3277,
	ARM_VREV16q8 = 3278,
	ARM_VREV32d16 = 3279,
	ARM_VREV32d8 = 3280,
	ARM_VREV32q16 = 3281,
	ARM_VREV32q8 = 3282,
	ARM_VREV64d16 = 3283,
	ARM_VREV64d32 = 3284,
	ARM_VREV64d8 = 3285,
	ARM_VREV64q16 = 3286,
	ARM_VREV64q32 = 3287,
	ARM_VREV64q8 = 3288,
	ARM_VRHADDsv16i8 = 3289,
	ARM_VRHADDsv2i32 = 3290,
	ARM_VRHADDsv4i16 = 3291,
	ARM_VRHADDsv4i32 = 3292,
	ARM_VRHADDsv8i16 = 3293,
	ARM_VRHADDsv8i8 = 3294,
	ARM_VRHADDuv16i8 = 3295,
	ARM_VRHADDuv2i32 = 3296,
	ARM_VRHADDuv4i16 = 3297,
	ARM_VRHADDuv4i32 = 3298,
	ARM_VRHADDuv8i16 = 3299,
	ARM_VRHADDuv8i8 = 3300,
	ARM_VRINTAD = 3301,
	ARM_VRINTAH = 3302,
	ARM_VRINTANDf = 3303,
	ARM_VRINTANDh = 3304,
	ARM_VRINTANQf = 3305,
	ARM_VRINTANQh = 3306,
	ARM_VRINTAS = 3307,
	ARM_VRINTMD = 3308,
	ARM_VRINTMH = 3309,
	ARM_VRINTMNDf = 3310,
	ARM_VRINTMNDh = 3311,
	ARM_VRINTMNQf = 3312,
	ARM_VRINTMNQh = 3313,
	ARM_VRINTMS = 3314,
	ARM_VRINTND = 3315,
	ARM_VRINTNH = 3316,
	ARM_VRINTNNDf = 3317,
	ARM_VRINTNNDh = 3318,
	ARM_VRINTNNQf = 3319,
	ARM_VRINTNNQh = 3320,
	ARM_VRINTNS = 3321,
	ARM_VRINTPD = 3322,
	ARM_VRINTPH = 3323,
	ARM_VRINTPNDf = 3324,
	ARM_VRINTPNDh = 3325,
	ARM_VRINTPNQf = 3326,
	ARM_VRINTPNQh = 3327,
	ARM_VRINTPS = 3328,
	ARM_VRINTRD = 3329,
	ARM_VRINTRH = 3330,
	ARM_VRINTRS = 3331,
	ARM_VRINTXD = 3332,
	ARM_VRINTXH = 3333,
	ARM_VRINTXNDf = 3334,
	ARM_VRINTXNDh = 3335,
	ARM_VRINTXNQf = 3336,
	ARM_VRINTXNQh = 3337,
	ARM_VRINTXS = 3338,
	ARM_VRINTZD = 3339,
	ARM_VRINTZH = 3340,
	ARM_VRINTZNDf = 3341,
	ARM_VRINTZNDh = 3342,
	ARM_VRINTZNQf = 3343,
	ARM_VRINTZNQh = 3344,
	ARM_VRINTZS = 3345,
	ARM_VRSHLsv16i8 = 3346,
	ARM_VRSHLsv1i64 = 3347,
	ARM_VRSHLsv2i32 = 3348,
	ARM_VRSHLsv2i64 = 3349,
	ARM_VRSHLsv4i16 = 3350,
	ARM_VRSHLsv4i32 = 3351,
	ARM_VRSHLsv8i16 = 3352,
	ARM_VRSHLsv8i8 = 3353,
	ARM_VRSHLuv16i8 = 3354,
	ARM_VRSHLuv1i64 = 3355,
	ARM_VRSHLuv2i32 = 3356,
	ARM_VRSHLuv2i64 = 3357,
	ARM_VRSHLuv4i16 = 3358,
	ARM_VRSHLuv4i32 = 3359,
	ARM_VRSHLuv8i16 = 3360,
	ARM_VRSHLuv8i8 = 3361,
	ARM_VRSHRNv2i32 = 3362,
	ARM_VRSHRNv4i16 = 3363,
	ARM_VRSHRNv8i8 = 3364,
	ARM_VRSHRsv16i8 = 3365,
	ARM_VRSHRsv1i64 = 3366,
	ARM_VRSHRsv2i32 = 3367,
	ARM_VRSHRsv2i64 = 3368,
	ARM_VRSHRsv4i16 = 3369,
	ARM_VRSHRsv4i32 = 3370,
	ARM_VRSHRsv8i16 = 3371,
	ARM_VRSHRsv8i8 = 3372,
	ARM_VRSHRuv16i8 = 3373,
	ARM_VRSHRuv1i64 = 3374,
	ARM_VRSHRuv2i32 = 3375,
	ARM_VRSHRuv2i64 = 3376,
	ARM_VRSHRuv4i16 = 3377,
	ARM_VRSHRuv4i32 = 3378,
	ARM_VRSHRuv8i16 = 3379,
	ARM_VRSHRuv8i8 = 3380,
	ARM_VRSQRTEd = 3381,
	ARM_VRSQRTEfd = 3382,
	ARM_VRSQRTEfq = 3383,
	ARM_VRSQRTEhd = 3384,
	ARM_VRSQRTEhq = 3385,
	ARM_VRSQRTEq = 3386,
	ARM_VRSQRTSfd = 3387,
	ARM_VRSQRTSfq = 3388,
	ARM_VRSQRTShd = 3389,
	ARM_VRSQRTShq = 3390,
	ARM_VRSRAsv16i8 = 3391,
	ARM_VRSRAsv1i64 = 3392,
	ARM_VRSRAsv2i32 = 3393,
	ARM_VRSRAsv2i64 = 3394,
	ARM_VRSRAsv4i16 = 3395,
	ARM_VRSRAsv4i32 = 3396,
	ARM_VRSRAsv8i16 = 3397,
	ARM_VRSRAsv8i8 = 3398,
	ARM_VRSRAuv16i8 = 3399,
	ARM_VRSRAuv1i64 = 3400,
	ARM_VRSRAuv2i32 = 3401,
	ARM_VRSRAuv2i64 = 3402,
	ARM_VRSRAuv4i16 = 3403,
	ARM_VRSRAuv4i32 = 3404,
	ARM_VRSRAuv8i16 = 3405,
	ARM_VRSRAuv8i8 = 3406,
	ARM_VRSUBHNv2i32 = 3407,
	ARM_VRSUBHNv4i16 = 3408,
	ARM_VRSUBHNv8i8 = 3409,
	ARM_VSCCLRMD = 3410,
	ARM_VSCCLRMS = 3411,
	ARM_VSDOTD = 3412,
	ARM_VSDOTDI = 3413,
	ARM_VSDOTQ = 3414,
	ARM_VSDOTQI = 3415,
	ARM_VSELEQD = 3416,
	ARM_VSELEQH = 3417,
	ARM_VSELEQS = 3418,
	ARM_VSELGED = 3419,
	ARM_VSELGEH = 3420,
	ARM_VSELGES = 3421,
	ARM_VSELGTD = 3422,
	ARM_VSELGTH = 3423,
	ARM_VSELGTS = 3424,
	ARM_VSELVSD = 3425,
	ARM_VSELVSH = 3426,
	ARM_VSELVSS = 3427,
	ARM_VSETLNi16 = 3428,
	ARM_VSETLNi32 = 3429,
	ARM_VSETLNi8 = 3430,
	ARM_VSHLLi16 = 3431,
	ARM_VSHLLi32 = 3432,
	ARM_VSHLLi8 = 3433,
	ARM_VSHLLsv2i64 = 3434,
	ARM_VSHLLsv4i32 = 3435,
	ARM_VSHLLsv8i16 = 3436,
	ARM_VSHLLuv2i64 = 3437,
	ARM_VSHLLuv4i32 = 3438,
	ARM_VSHLLuv8i16 = 3439,
	ARM_VSHLiv16i8 = 3440,
	ARM_VSHLiv1i64 = 3441,
	ARM_VSHLiv2i32 = 3442,
	ARM_VSHLiv2i64 = 3443,
	ARM_VSHLiv4i16 = 3444,
	ARM_VSHLiv4i32 = 3445,
	ARM_VSHLiv8i16 = 3446,
	ARM_VSHLiv8i8 = 3447,
	ARM_VSHLsv16i8 = 3448,
	ARM_VSHLsv1i64 = 3449,
	ARM_VSHLsv2i32 = 3450,
	ARM_VSHLsv2i64 = 3451,
	ARM_VSHLsv4i16 = 3452,
	ARM_VSHLsv4i32 = 3453,
	ARM_VSHLsv8i16 = 3454,
	ARM_VSHLsv8i8 = 3455,
	ARM_VSHLuv16i8 = 3456,
	ARM_VSHLuv1i64 = 3457,
	ARM_VSHLuv2i32 = 3458,
	ARM_VSHLuv2i64 = 3459,
	ARM_VSHLuv4i16 = 3460,
	ARM_VSHLuv4i32 = 3461,
	ARM_VSHLuv8i16 = 3462,
	ARM_VSHLuv8i8 = 3463,
	ARM_VSHRNv2i32 = 3464,
	ARM_VSHRNv4i16 = 3465,
	ARM_VSHRNv8i8 = 3466,
	ARM_VSHRsv16i8 = 3467,
	ARM_VSHRsv1i64 = 3468,
	ARM_VSHRsv2i32 = 3469,
	ARM_VSHRsv2i64 = 3470,
	ARM_VSHRsv4i16 = 3471,
	ARM_VSHRsv4i32 = 3472,
	ARM_VSHRsv8i16 = 3473,
	ARM_VSHRsv8i8 = 3474,
	ARM_VSHRuv16i8 = 3475,
	ARM_VSHRuv1i64 = 3476,
	ARM_VSHRuv2i32 = 3477,
	ARM_VSHRuv2i64 = 3478,
	ARM_VSHRuv4i16 = 3479,
	ARM_VSHRuv4i32 = 3480,
	ARM_VSHRuv8i16 = 3481,
	ARM_VSHRuv8i8 = 3482,
	ARM_VSHTOD = 3483,
	ARM_VSHTOH = 3484,
	ARM_VSHTOS = 3485,
	ARM_VSITOD = 3486,
	ARM_VSITOH = 3487,
	ARM_VSITOS = 3488,
	ARM_VSLIv16i8 = 3489,
	ARM_VSLIv1i64 = 3490,
	ARM_VSLIv2i32 = 3491,
	ARM_VSLIv2i64 = 3492,
	ARM_VSLIv4i16 = 3493,
	ARM_VSLIv4i32 = 3494,
	ARM_VSLIv8i16 = 3495,
	ARM_VSLIv8i8 = 3496,
	ARM_VSLTOD = 3497,
	ARM_VSLTOH = 3498,
	ARM_VSLTOS = 3499,
	ARM_VSMMLA = 3500,
	ARM_VSQRTD = 3501,
	ARM_VSQRTH = 3502,
	ARM_VSQRTS = 3503,
	ARM_VSRAsv16i8 = 3504,
	ARM_VSRAsv1i64 = 3505,
	ARM_VSRAsv2i32 = 3506,
	ARM_VSRAsv2i64 = 3507,
	ARM_VSRAsv4i16 = 3508,
	ARM_VSRAsv4i32 = 3509,
	ARM_VSRAsv8i16 = 3510,
	ARM_VSRAsv8i8 = 3511,
	ARM_VSRAuv16i8 = 3512,
	ARM_VSRAuv1i64 = 3513,
	ARM_VSRAuv2i32 = 3514,
	ARM_VSRAuv2i64 = 3515,
	ARM_VSRAuv4i16 = 3516,
	ARM_VSRAuv4i32 = 3517,
	ARM_VSRAuv8i16 = 3518,
	ARM_VSRAuv8i8 = 3519,
	ARM_VSRIv16i8 = 3520,
	ARM_VSRIv1i64 = 3521,
	ARM_VSRIv2i32 = 3522,
	ARM_VSRIv2i64 = 3523,
	ARM_VSRIv4i16 = 3524,
	ARM_VSRIv4i32 = 3525,
	ARM_VSRIv8i16 = 3526,
	ARM_VSRIv8i8 = 3527,
	ARM_VST1LNd16 = 3528,
	ARM_VST1LNd16_UPD = 3529,
	ARM_VST1LNd32 = 3530,
	ARM_VST1LNd32_UPD = 3531,
	ARM_VST1LNd8 = 3532,
	ARM_VST1LNd8_UPD = 3533,
	ARM_VST1LNq16Pseudo = 3534,
	ARM_VST1LNq16Pseudo_UPD = 3535,
	ARM_VST1LNq32Pseudo = 3536,
	ARM_VST1LNq32Pseudo_UPD = 3537,
	ARM_VST1LNq8Pseudo = 3538,
	ARM_VST1LNq8Pseudo_UPD = 3539,
	ARM_VST1d16 = 3540,
	ARM_VST1d16Q = 3541,
	ARM_VST1d16QPseudo = 3542,
	ARM_VST1d16QPseudoWB_fixed = 3543,
	ARM_VST1d16QPseudoWB_register = 3544,
	ARM_VST1d16Qwb_fixed = 3545,
	ARM_VST1d16Qwb_register = 3546,
	ARM_VST1d16T = 3547,
	ARM_VST1d16TPseudo = 3548,
	ARM_VST1d16TPseudoWB_fixed = 3549,
	ARM_VST1d16TPseudoWB_register = 3550,
	ARM_VST1d16Twb_fixed = 3551,
	ARM_VST1d16Twb_register = 3552,
	ARM_VST1d16wb_fixed = 3553,
	ARM_VST1d16wb_register = 3554,
	ARM_VST1d32 = 3555,
	ARM_VST1d32Q = 3556,
	ARM_VST1d32QPseudo = 3557,
	ARM_VST1d32QPseudoWB_fixed = 3558,
	ARM_VST1d32QPseudoWB_register = 3559,
	ARM_VST1d32Qwb_fixed = 3560,
	ARM_VST1d32Qwb_register = 3561,
	ARM_VST1d32T = 3562,
	ARM_VST1d32TPseudo = 3563,
	ARM_VST1d32TPseudoWB_fixed = 3564,
	ARM_VST1d32TPseudoWB_register = 3565,
	ARM_VST1d32Twb_fixed = 3566,
	ARM_VST1d32Twb_register = 3567,
	ARM_VST1d32wb_fixed = 3568,
	ARM_VST1d32wb_register = 3569,
	ARM_VST1d64 = 3570,
	ARM_VST1d64Q = 3571,
	ARM_VST1d64QPseudo = 3572,
	ARM_VST1d64QPseudoWB_fixed = 3573,
	ARM_VST1d64QPseudoWB_register = 3574,
	ARM_VST1d64Qwb_fixed = 3575,
	ARM_VST1d64Qwb_register = 3576,
	ARM_VST1d64T = 3577,
	ARM_VST1d64TPseudo = 3578,
	ARM_VST1d64TPseudoWB_fixed = 3579,
	ARM_VST1d64TPseudoWB_register = 3580,
	ARM_VST1d64Twb_fixed = 3581,
	ARM_VST1d64Twb_register = 3582,
	ARM_VST1d64wb_fixed = 3583,
	ARM_VST1d64wb_register = 3584,
	ARM_VST1d8 = 3585,
	ARM_VST1d8Q = 3586,
	ARM_VST1d8QPseudo = 3587,
	ARM_VST1d8QPseudoWB_fixed = 3588,
	ARM_VST1d8QPseudoWB_register = 3589,
	ARM_VST1d8Qwb_fixed = 3590,
	ARM_VST1d8Qwb_register = 3591,
	ARM_VST1d8T = 3592,
	ARM_VST1d8TPseudo = 3593,
	ARM_VST1d8TPseudoWB_fixed = 3594,
	ARM_VST1d8TPseudoWB_register = 3595,
	ARM_VST1d8Twb_fixed = 3596,
	ARM_VST1d8Twb_register = 3597,
	ARM_VST1d8wb_fixed = 3598,
	ARM_VST1d8wb_register = 3599,
	ARM_VST1q16 = 3600,
	ARM_VST1q16HighQPseudo = 3601,
	ARM_VST1q16HighQPseudo_UPD = 3602,
	ARM_VST1q16HighTPseudo = 3603,
	ARM_VST1q16HighTPseudo_UPD = 3604,
	ARM_VST1q16LowQPseudo_UPD = 3605,
	ARM_VST1q16LowTPseudo_UPD = 3606,
	ARM_VST1q16wb_fixed = 3607,
	ARM_VST1q16wb_register = 3608,
	ARM_VST1q32 = 3609,
	ARM_VST1q32HighQPseudo = 3610,
	ARM_VST1q32HighQPseudo_UPD = 3611,
	ARM_VST1q32HighTPseudo = 3612,
	ARM_VST1q32HighTPseudo_UPD = 3613,
	ARM_VST1q32LowQPseudo_UPD = 3614,
	ARM_VST1q32LowTPseudo_UPD = 3615,
	ARM_VST1q32wb_fixed = 3616,
	ARM_VST1q32wb_register = 3617,
	ARM_VST1q64 = 3618,
	ARM_VST1q64HighQPseudo = 3619,
	ARM_VST1q64HighQPseudo_UPD = 3620,
	ARM_VST1q64HighTPseudo = 3621,
	ARM_VST1q64HighTPseudo_UPD = 3622,
	ARM_VST1q64LowQPseudo_UPD = 3623,
	ARM_VST1q64LowTPseudo_UPD = 3624,
	ARM_VST1q64wb_fixed = 3625,
	ARM_VST1q64wb_register = 3626,
	ARM_VST1q8 = 3627,
	ARM_VST1q8HighQPseudo = 3628,
	ARM_VST1q8HighQPseudo_UPD = 3629,
	ARM_VST1q8HighTPseudo = 3630,
	ARM_VST1q8HighTPseudo_UPD = 3631,
	ARM_VST1q8LowQPseudo_UPD = 3632,
	ARM_VST1q8LowTPseudo_UPD = 3633,
	ARM_VST1q8wb_fixed = 3634,
	ARM_VST1q8wb_register = 3635,
	ARM_VST2LNd16 = 3636,
	ARM_VST2LNd16Pseudo = 3637,
	ARM_VST2LNd16Pseudo_UPD = 3638,
	ARM_VST2LNd16_UPD = 3639,
	ARM_VST2LNd32 = 3640,
	ARM_VST2LNd32Pseudo = 3641,
	ARM_VST2LNd32Pseudo_UPD = 3642,
	ARM_VST2LNd32_UPD = 3643,
	ARM_VST2LNd8 = 3644,
	ARM_VST2LNd8Pseudo = 3645,
	ARM_VST2LNd8Pseudo_UPD = 3646,
	ARM_VST2LNd8_UPD = 3647,
	ARM_VST2LNq16 = 3648,
	ARM_VST2LNq16Pseudo = 3649,
	ARM_VST2LNq16Pseudo_UPD = 3650,
	ARM_VST2LNq16_UPD = 3651,
	ARM_VST2LNq32 = 3652,
	ARM_VST2LNq32Pseudo = 3653,
	ARM_VST2LNq32Pseudo_UPD = 3654,
	ARM_VST2LNq32_UPD = 3655,
	ARM_VST2b16 = 3656,
	ARM_VST2b16wb_fixed = 3657,
	ARM_VST2b16wb_register = 3658,
	ARM_VST2b32 = 3659,
	ARM_VST2b32wb_fixed = 3660,
	ARM_VST2b32wb_register = 3661,
	ARM_VST2b8 = 3662,
	ARM_VST2b8wb_fixed = 3663,
	ARM_VST2b8wb_register = 3664,
	ARM_VST2d16 = 3665,
	ARM_VST2d16wb_fixed = 3666,
	ARM_VST2d16wb_register = 3667,
	ARM_VST2d32 = 3668,
	ARM_VST2d32wb_fixed = 3669,
	ARM_VST2d32wb_register = 3670,
	ARM_VST2d8 = 3671,
	ARM_VST2d8wb_fixed = 3672,
	ARM_VST2d8wb_register = 3673,
	ARM_VST2q16 = 3674,
	ARM_VST2q16Pseudo = 3675,
	ARM_VST2q16PseudoWB_fixed = 3676,
	ARM_VST2q16PseudoWB_register = 3677,
	ARM_VST2q16wb_fixed = 3678,
	ARM_VST2q16wb_register = 3679,
	ARM_VST2q32 = 3680,
	ARM_VST2q32Pseudo = 3681,
	ARM_VST2q32PseudoWB_fixed = 3682,
	ARM_VST2q32PseudoWB_register = 3683,
	ARM_VST2q32wb_fixed = 3684,
	ARM_VST2q32wb_register = 3685,
	ARM_VST2q8 = 3686,
	ARM_VST2q8Pseudo = 3687,
	ARM_VST2q8PseudoWB_fixed = 3688,
	ARM_VST2q8PseudoWB_register = 3689,
	ARM_VST2q8wb_fixed = 3690,
	ARM_VST2q8wb_register = 3691,
	ARM_VST3LNd16 = 3692,
	ARM_VST3LNd16Pseudo = 3693,
	ARM_VST3LNd16Pseudo_UPD = 3694,
	ARM_VST3LNd16_UPD = 3695,
	ARM_VST3LNd32 = 3696,
	ARM_VST3LNd32Pseudo = 3697,
	ARM_VST3LNd32Pseudo_UPD = 3698,
	ARM_VST3LNd32_UPD = 3699,
	ARM_VST3LNd8 = 3700,
	ARM_VST3LNd8Pseudo = 3701,
	ARM_VST3LNd8Pseudo_UPD = 3702,
	ARM_VST3LNd8_UPD = 3703,
	ARM_VST3LNq16 = 3704,
	ARM_VST3LNq16Pseudo = 3705,
	ARM_VST3LNq16Pseudo_UPD = 3706,
	ARM_VST3LNq16_UPD = 3707,
	ARM_VST3LNq32 = 3708,
	ARM_VST3LNq32Pseudo = 3709,
	ARM_VST3LNq32Pseudo_UPD = 3710,
	ARM_VST3LNq32_UPD = 3711,
	ARM_VST3d16 = 3712,
	ARM_VST3d16Pseudo = 3713,
	ARM_VST3d16Pseudo_UPD = 3714,
	ARM_VST3d16_UPD = 3715,
	ARM_VST3d32 = 3716,
	ARM_VST3d32Pseudo = 3717,
	ARM_VST3d32Pseudo_UPD = 3718,
	ARM_VST3d32_UPD = 3719,
	ARM_VST3d8 = 3720,
	ARM_VST3d8Pseudo = 3721,
	ARM_VST3d8Pseudo_UPD = 3722,
	ARM_VST3d8_UPD = 3723,
	ARM_VST3q16 = 3724,
	ARM_VST3q16Pseudo_UPD = 3725,
	ARM_VST3q16_UPD = 3726,
	ARM_VST3q16oddPseudo = 3727,
	ARM_VST3q16oddPseudo_UPD = 3728,
	ARM_VST3q32 = 3729,
	ARM_VST3q32Pseudo_UPD = 3730,
	ARM_VST3q32_UPD = 3731,
	ARM_VST3q32oddPseudo = 3732,
	ARM_VST3q32oddPseudo_UPD = 3733,
	ARM_VST3q8 = 3734,
	ARM_VST3q8Pseudo_UPD = 3735,
	ARM_VST3q8_UPD = 3736,
	ARM_VST3q8oddPseudo = 3737,
	ARM_VST3q8oddPseudo_UPD = 3738,
	ARM_VST4LNd16 = 3739,
	ARM_VST4LNd16Pseudo = 3740,
	ARM_VST4LNd16Pseudo_UPD = 3741,
	ARM_VST4LNd16_UPD = 3742,
	ARM_VST4LNd32 = 3743,
	ARM_VST4LNd32Pseudo = 3744,
	ARM_VST4LNd32Pseudo_UPD = 3745,
	ARM_VST4LNd32_UPD = 3746,
	ARM_VST4LNd8 = 3747,
	ARM_VST4LNd8Pseudo = 3748,
	ARM_VST4LNd8Pseudo_UPD = 3749,
	ARM_VST4LNd8_UPD = 3750,
	ARM_VST4LNq16 = 3751,
	ARM_VST4LNq16Pseudo = 3752,
	ARM_VST4LNq16Pseudo_UPD = 3753,
	ARM_VST4LNq16_UPD = 3754,
	ARM_VST4LNq32 = 3755,
	ARM_VST4LNq32Pseudo = 3756,
	ARM_VST4LNq32Pseudo_UPD = 3757,
	ARM_VST4LNq32_UPD = 3758,
	ARM_VST4d16 = 3759,
	ARM_VST4d16Pseudo = 3760,
	ARM_VST4d16Pseudo_UPD = 3761,
	ARM_VST4d16_UPD = 3762,
	ARM_VST4d32 = 3763,
	ARM_VST4d32Pseudo = 3764,
	ARM_VST4d32Pseudo_UPD = 3765,
	ARM_VST4d32_UPD = 3766,
	ARM_VST4d8 = 3767,
	ARM_VST4d8Pseudo = 3768,
	ARM_VST4d8Pseudo_UPD = 3769,
	ARM_VST4d8_UPD = 3770,
	ARM_VST4q16 = 3771,
	ARM_VST4q16Pseudo_UPD = 3772,
	ARM_VST4q16_UPD = 3773,
	ARM_VST4q16oddPseudo = 3774,
	ARM_VST4q16oddPseudo_UPD = 3775,
	ARM_VST4q32 = 3776,
	ARM_VST4q32Pseudo_UPD = 3777,
	ARM_VST4q32_UPD = 3778,
	ARM_VST4q32oddPseudo = 3779,
	ARM_VST4q32oddPseudo_UPD = 3780,
	ARM_VST4q8 = 3781,
	ARM_VST4q8Pseudo_UPD = 3782,
	ARM_VST4q8_UPD = 3783,
	ARM_VST4q8oddPseudo = 3784,
	ARM_VST4q8oddPseudo_UPD = 3785,
	ARM_VSTMDDB_UPD = 3786,
	ARM_VSTMDIA = 3787,
	ARM_VSTMDIA_UPD = 3788,
	ARM_VSTMQIA = 3789,
	ARM_VSTMSDB_UPD = 3790,
	ARM_VSTMSIA = 3791,
	ARM_VSTMSIA_UPD = 3792,
	ARM_VSTRD = 3793,
	ARM_VSTRH = 3794,
	ARM_VSTRS = 3795,
	ARM_VSTR_FPCXTNS_off = 3796,
	ARM_VSTR_FPCXTNS_post = 3797,
	ARM_VSTR_FPCXTNS_pre = 3798,
	ARM_VSTR_FPCXTS_off = 3799,
	ARM_VSTR_FPCXTS_post = 3800,
	ARM_VSTR_FPCXTS_pre = 3801,
	ARM_VSTR_FPSCR_NZCVQC_off = 3802,
	ARM_VSTR_FPSCR_NZCVQC_post = 3803,
	ARM_VSTR_FPSCR_NZCVQC_pre = 3804,
	ARM_VSTR_FPSCR_off = 3805,
	ARM_VSTR_FPSCR_post = 3806,
	ARM_VSTR_FPSCR_pre = 3807,
	ARM_VSTR_P0_off = 3808,
	ARM_VSTR_P0_post = 3809,
	ARM_VSTR_P0_pre = 3810,
	ARM_VSTR_VPR_off = 3811,
	ARM_VSTR_VPR_post = 3812,
	ARM_VSTR_VPR_pre = 3813,
	ARM_VSUBD = 3814,
	ARM_VSUBH = 3815,
	ARM_VSUBHNv2i32 = 3816,
	ARM_VSUBHNv4i16 = 3817,
	ARM_VSUBHNv8i8 = 3818,
	ARM_VSUBLsv2i64 = 3819,
	ARM_VSUBLsv4i32 = 3820,
	ARM_VSUBLsv8i16 = 3821,
	ARM_VSUBLuv2i64 = 3822,
	ARM_VSUBLuv4i32 = 3823,
	ARM_VSUBLuv8i16 = 3824,
	ARM_VSUBS = 3825,
	ARM_VSUBWsv2i64 = 3826,
	ARM_VSUBWsv4i32 = 3827,
	ARM_VSUBWsv8i16 = 3828,
	ARM_VSUBWuv2i64 = 3829,
	ARM_VSUBWuv4i32 = 3830,
	ARM_VSUBWuv8i16 = 3831,
	ARM_VSUBfd = 3832,
	ARM_VSUBfq = 3833,
	ARM_VSUBhd = 3834,
	ARM_VSUBhq = 3835,
	ARM_VSUBv16i8 = 3836,
	ARM_VSUBv1i64 = 3837,
	ARM_VSUBv2i32 = 3838,
	ARM_VSUBv2i64 = 3839,
	ARM_VSUBv4i16 = 3840,
	ARM_VSUBv4i32 = 3841,
	ARM_VSUBv8i16 = 3842,
	ARM_VSUBv8i8 = 3843,
	ARM_VSUDOTDI = 3844,
	ARM_VSUDOTQI = 3845,
	ARM_VSWPd = 3846,
	ARM_VSWPq = 3847,
	ARM_VTBL1 = 3848,
	ARM_VTBL2 = 3849,
	ARM_VTBL3 = 3850,
	ARM_VTBL3Pseudo = 3851,
	ARM_VTBL4 = 3852,
	ARM_VTBL4Pseudo = 3853,
	ARM_VTBX1 = 3854,
	ARM_VTBX2 = 3855,
	ARM_VTBX3 = 3856,
	ARM_VTBX3Pseudo = 3857,
	ARM_VTBX4 = 3858,
	ARM_VTBX4Pseudo = 3859,
	ARM_VTOSHD = 3860,
	ARM_VTOSHH = 3861,
	ARM_VTOSHS = 3862,
	ARM_VTOSIRD = 3863,
	ARM_VTOSIRH = 3864,
	ARM_VTOSIRS = 3865,
	ARM_VTOSIZD = 3866,
	ARM_VTOSIZH = 3867,
	ARM_VTOSIZS = 3868,
	ARM_VTOSLD = 3869,
	ARM_VTOSLH = 3870,
	ARM_VTOSLS = 3871,
	ARM_VTOUHD = 3872,
	ARM_VTOUHH = 3873,
	ARM_VTOUHS = 3874,
	ARM_VTOUIRD = 3875,
	ARM_VTOUIRH = 3876,
	ARM_VTOUIRS = 3877,
	ARM_VTOUIZD = 3878,
	ARM_VTOUIZH = 3879,
	ARM_VTOUIZS = 3880,
	ARM_VTOULD = 3881,
	ARM_VTOULH = 3882,
	ARM_VTOULS = 3883,
	ARM_VTRNd16 = 3884,
	ARM_VTRNd32 = 3885,
	ARM_VTRNd8 = 3886,
	ARM_VTRNq16 = 3887,
	ARM_VTRNq32 = 3888,
	ARM_VTRNq8 = 3889,
	ARM_VTSTv16i8 = 3890,
	ARM_VTSTv2i32 = 3891,
	ARM_VTSTv4i16 = 3892,
	ARM_VTSTv4i32 = 3893,
	ARM_VTSTv8i16 = 3894,
	ARM_VTSTv8i8 = 3895,
	ARM_VUDOTD = 3896,
	ARM_VUDOTDI = 3897,
	ARM_VUDOTQ = 3898,
	ARM_VUDOTQI = 3899,
	ARM_VUHTOD = 3900,
	ARM_VUHTOH = 3901,
	ARM_VUHTOS = 3902,
	ARM_VUITOD = 3903,
	ARM_VUITOH = 3904,
	ARM_VUITOS = 3905,
	ARM_VULTOD = 3906,
	ARM_VULTOH = 3907,
	ARM_VULTOS = 3908,
	ARM_VUMMLA = 3909,
	ARM_VUSDOTD = 3910,
	ARM_VUSDOTDI = 3911,
	ARM_VUSDOTQ = 3912,
	ARM_VUSDOTQI = 3913,
	ARM_VUSMMLA = 3914,
	ARM_VUZPd16 = 3915,
	ARM_VUZPd8 = 3916,
	ARM_VUZPq16 = 3917,
	ARM_VUZPq32 = 3918,
	ARM_VUZPq8 = 3919,
	ARM_VZIPd16 = 3920,
	ARM_VZIPd8 = 3921,
	ARM_VZIPq16 = 3922,
	ARM_VZIPq32 = 3923,
	ARM_VZIPq8 = 3924,
	ARM_sysLDMDA = 3925,
	ARM_sysLDMDA_UPD = 3926,
	ARM_sysLDMDB = 3927,
	ARM_sysLDMDB_UPD = 3928,
	ARM_sysLDMIA = 3929,
	ARM_sysLDMIA_UPD = 3930,
	ARM_sysLDMIB = 3931,
	ARM_sysLDMIB_UPD = 3932,
	ARM_sysSTMDA = 3933,
	ARM_sysSTMDA_UPD = 3934,
	ARM_sysSTMDB = 3935,
	ARM_sysSTMDB_UPD = 3936,
	ARM_sysSTMIA = 3937,
	ARM_sysSTMIA_UPD = 3938,
	ARM_sysSTMIB = 3939,
	ARM_sysSTMIB_UPD = 3940,
	ARM_t2ADCri = 3941,
	ARM_t2ADCrr = 3942,
	ARM_t2ADCrs = 3943,
	ARM_t2ADDri = 3944,
	ARM_t2ADDri12 = 3945,
	ARM_t2ADDrr = 3946,
	ARM_t2ADDrs = 3947,
	ARM_t2ADDspImm = 3948,
	ARM_t2ADDspImm12 = 3949,
	ARM_t2ADR = 3950,
	ARM_t2ANDri = 3951,
	ARM_t2ANDrr = 3952,
	ARM_t2ANDrs = 3953,
	ARM_t2ASRri = 3954,
	ARM_t2ASRrr = 3955,
	ARM_t2AUT = 3956,
	ARM_t2AUTG = 3957,
	ARM_t2B = 3958,
	ARM_t2BFC = 3959,
	ARM_t2BFI = 3960,
	ARM_t2BFLi = 3961,
	ARM_t2BFLr = 3962,
	ARM_t2BFi = 3963,
	ARM_t2BFic = 3964,
	ARM_t2BFr = 3965,
	ARM_t2BICri = 3966,
	ARM_t2BICrr = 3967,
	ARM_t2BICrs = 3968,
	ARM_t2BTI = 3969,
	ARM_t2BXAUT = 3970,
	ARM_t2BXJ = 3971,
	ARM_t2Bcc = 3972,
	ARM_t2CDP = 3973,
	ARM_t2CDP2 = 3974,
	ARM_t2CLREX = 3975,
	ARM_t2CLRM = 3976,
	ARM_t2CLZ = 3977,
	ARM_t2CMNri = 3978,
	ARM_t2CMNzrr = 3979,
	ARM_t2CMNzrs = 3980,
	ARM_t2CMPri = 3981,
	ARM_t2CMPrr = 3982,
	ARM_t2CMPrs = 3983,
	ARM_t2CPS1p = 3984,
	ARM_t2CPS2p = 3985,
	ARM_t2CPS3p = 3986,
	ARM_t2CRC32B = 3987,
	ARM_t2CRC32CB = 3988,
	ARM_t2CRC32CH = 3989,
	ARM_t2CRC32CW = 3990,
	ARM_t2CRC32H = 3991,
	ARM_t2CRC32W = 3992,
	ARM_t2CSEL = 3993,
	ARM_t2CSINC = 3994,
	ARM_t2CSINV = 3995,
	ARM_t2CSNEG = 3996,
	ARM_t2DBG = 3997,
	ARM_t2DCPS1 = 3998,
	ARM_t2DCPS2 = 3999,
	ARM_t2DCPS3 = 4000,
	ARM_t2DLS = 4001,
	ARM_t2DMB = 4002,
	ARM_t2DSB = 4003,
	ARM_t2EORri = 4004,
	ARM_t2EORrr = 4005,
	ARM_t2EORrs = 4006,
	ARM_t2HINT = 4007,
	ARM_t2HVC = 4008,
	ARM_t2ISB = 4009,
	ARM_t2IT = 4010,
	ARM_t2Int_eh_sjlj_setjmp = 4011,
	ARM_t2Int_eh_sjlj_setjmp_nofp = 4012,
	ARM_t2LDA = 4013,
	ARM_t2LDAB = 4014,
	ARM_t2LDAEX = 4015,
	ARM_t2LDAEXB = 4016,
	ARM_t2LDAEXD = 4017,
	ARM_t2LDAEXH = 4018,
	ARM_t2LDAH = 4019,
	ARM_t2LDC2L_OFFSET = 4020,
	ARM_t2LDC2L_OPTION = 4021,
	ARM_t2LDC2L_POST = 4022,
	ARM_t2LDC2L_PRE = 4023,
	ARM_t2LDC2_OFFSET = 4024,
	ARM_t2LDC2_OPTION = 4025,
	ARM_t2LDC2_POST = 4026,
	ARM_t2LDC2_PRE = 4027,
	ARM_t2LDCL_OFFSET = 4028,
	ARM_t2LDCL_OPTION = 4029,
	ARM_t2LDCL_POST = 4030,
	ARM_t2LDCL_PRE = 4031,
	ARM_t2LDC_OFFSET = 4032,
	ARM_t2LDC_OPTION = 4033,
	ARM_t2LDC_POST = 4034,
	ARM_t2LDC_PRE = 4035,
	ARM_t2LDMDB = 4036,
	ARM_t2LDMDB_UPD = 4037,
	ARM_t2LDMIA = 4038,
	ARM_t2LDMIA_UPD = 4039,
	ARM_t2LDRBT = 4040,
	ARM_t2LDRB_POST = 4041,
	ARM_t2LDRB_PRE = 4042,
	ARM_t2LDRBi12 = 4043,
	ARM_t2LDRBi8 = 4044,
	ARM_t2LDRBpci = 4045,
	ARM_t2LDRBs = 4046,
	ARM_t2LDRD_POST = 4047,
	ARM_t2LDRD_PRE = 4048,
	ARM_t2LDRDi8 = 4049,
	ARM_t2LDREX = 4050,
	ARM_t2LDREXB = 4051,
	ARM_t2LDREXD = 4052,
	ARM_t2LDREXH = 4053,
	ARM_t2LDRHT = 4054,
	ARM_t2LDRH_POST = 4055,
	ARM_t2LDRH_PRE = 4056,
	ARM_t2LDRHi12 = 4057,
	ARM_t2LDRHi8 = 4058,
	ARM_t2LDRHpci = 4059,
	ARM_t2LDRHs = 4060,
	ARM_t2LDRSBT = 4061,
	ARM_t2LDRSB_POST = 4062,
	ARM_t2LDRSB_PRE = 4063,
	ARM_t2LDRSBi12 = 4064,
	ARM_t2LDRSBi8 = 4065,
	ARM_t2LDRSBpci = 4066,
	ARM_t2LDRSBs = 4067,
	ARM_t2LDRSHT = 4068,
	ARM_t2LDRSH_POST = 4069,
	ARM_t2LDRSH_PRE = 4070,
	ARM_t2LDRSHi12 = 4071,
	ARM_t2LDRSHi8 = 4072,
	ARM_t2LDRSHpci = 4073,
	ARM_t2LDRSHs = 4074,
	ARM_t2LDRT = 4075,
	ARM_t2LDR_POST = 4076,
	ARM_t2LDR_PRE = 4077,
	ARM_t2LDRi12 = 4078,
	ARM_t2LDRi8 = 4079,
	ARM_t2LDRpci = 4080,
	ARM_t2LDRs = 4081,
	ARM_t2LE = 4082,
	ARM_t2LEUpdate = 4083,
	ARM_t2LSLri = 4084,
	ARM_t2LSLrr = 4085,
	ARM_t2LSRri = 4086,
	ARM_t2LSRrr = 4087,
	ARM_t2MCR = 4088,
	ARM_t2MCR2 = 4089,
	ARM_t2MCRR = 4090,
	ARM_t2MCRR2 = 4091,
	ARM_t2MLA = 4092,
	ARM_t2MLS = 4093,
	ARM_t2MOVTi16 = 4094,
	ARM_t2MOVi = 4095,
	ARM_t2MOVi16 = 4096,
	ARM_t2MOVr = 4097,
	ARM_t2MOVsra_flag = 4098,
	ARM_t2MOVsrl_flag = 4099,
	ARM_t2MRC = 4100,
	ARM_t2MRC2 = 4101,
	ARM_t2MRRC = 4102,
	ARM_t2MRRC2 = 4103,
	ARM_t2MRS_AR = 4104,
	ARM_t2MRS_M = 4105,
	ARM_t2MRSbanked = 4106,
	ARM_t2MRSsys_AR = 4107,
	ARM_t2MSR_AR = 4108,
	ARM_t2MSR_M = 4109,
	ARM_t2MSRbanked = 4110,
	ARM_t2MUL = 4111,
	ARM_t2MVNi = 4112,
	ARM_t2MVNr = 4113,
	ARM_t2MVNs = 4114,
	ARM_t2ORNri = 4115,
	ARM_t2ORNrr = 4116,
	ARM_t2ORNrs = 4117,
	ARM_t2ORRri = 4118,
	ARM_t2ORRrr = 4119,
	ARM_t2ORRrs = 4120,
	ARM_t2PAC = 4121,
	ARM_t2PACBTI = 4122,
	ARM_t2PACG = 4123,
	ARM_t2PKHBT = 4124,
	ARM_t2PKHTB = 4125,
	ARM_t2PLDWi12 = 4126,
	ARM_t2PLDWi8 = 4127,
	ARM_t2PLDWs = 4128,
	ARM_t2PLDi12 = 4129,
	ARM_t2PLDi8 = 4130,
	ARM_t2PLDpci = 4131,
	ARM_t2PLDs = 4132,
	ARM_t2PLIi12 = 4133,
	ARM_t2PLIi8 = 4134,
	ARM_t2PLIpci = 4135,
	ARM_t2PLIs = 4136,
	ARM_t2QADD = 4137,
	ARM_t2QADD16 = 4138,
	ARM_t2QADD8 = 4139,
	ARM_t2QASX = 4140,
	ARM_t2QDADD = 4141,
	ARM_t2QDSUB = 4142,
	ARM_t2QSAX = 4143,
	ARM_t2QSUB = 4144,
	ARM_t2QSUB16 = 4145,
	ARM_t2QSUB8 = 4146,
	ARM_t2RBIT = 4147,
	ARM_t2REV = 4148,
	ARM_t2REV16 = 4149,
	ARM_t2REVSH = 4150,
	ARM_t2RFEDB = 4151,
	ARM_t2RFEDBW = 4152,
	ARM_t2RFEIA = 4153,
	ARM_t2RFEIAW = 4154,
	ARM_t2RORri = 4155,
	ARM_t2RORrr = 4156,
	ARM_t2RRX = 4157,
	ARM_t2RSBri = 4158,
	ARM_t2RSBrr = 4159,
	ARM_t2RSBrs = 4160,
	ARM_t2SADD16 = 4161,
	ARM_t2SADD8 = 4162,
	ARM_t2SASX = 4163,
	ARM_t2SB = 4164,
	ARM_t2SBCri = 4165,
	ARM_t2SBCrr = 4166,
	ARM_t2SBCrs = 4167,
	ARM_t2SBFX = 4168,
	ARM_t2SDIV = 4169,
	ARM_t2SEL = 4170,
	ARM_t2SETPAN = 4171,
	ARM_t2SG = 4172,
	ARM_t2SHADD16 = 4173,
	ARM_t2SHADD8 = 4174,
	ARM_t2SHASX = 4175,
	ARM_t2SHSAX = 4176,
	ARM_t2SHSUB16 = 4177,
	ARM_t2SHSUB8 = 4178,
	ARM_t2SMC = 4179,
	ARM_t2SMLABB = 4180,
	ARM_t2SMLABT = 4181,
	ARM_t2SMLAD = 4182,
	ARM_t2SMLADX = 4183,
	ARM_t2SMLAL = 4184,
	ARM_t2SMLALBB = 4185,
	ARM_t2SMLALBT = 4186,
	ARM_t2SMLALD = 4187,
	ARM_t2SMLALDX = 4188,
	ARM_t2SMLALTB = 4189,
	ARM_t2SMLALTT = 4190,
	ARM_t2SMLATB = 4191,
	ARM_t2SMLATT = 4192,
	ARM_t2SMLAWB = 4193,
	ARM_t2SMLAWT = 4194,
	ARM_t2SMLSD = 4195,
	ARM_t2SMLSDX = 4196,
	ARM_t2SMLSLD = 4197,
	ARM_t2SMLSLDX = 4198,
	ARM_t2SMMLA = 4199,
	ARM_t2SMMLAR = 4200,
	ARM_t2SMMLS = 4201,
	ARM_t2SMMLSR = 4202,
	ARM_t2SMMUL = 4203,
	ARM_t2SMMULR = 4204,
	ARM_t2SMUAD = 4205,
	ARM_t2SMUADX = 4206,
	ARM_t2SMULBB = 4207,
	ARM_t2SMULBT = 4208,
	ARM_t2SMULL = 4209,
	ARM_t2SMULTB = 4210,
	ARM_t2SMULTT = 4211,
	ARM_t2SMULWB = 4212,
	ARM_t2SMULWT = 4213,
	ARM_t2SMUSD = 4214,
	ARM_t2SMUSDX = 4215,
	ARM_t2SRSDB = 4216,
	ARM_t2SRSDB_UPD = 4217,
	ARM_t2SRSIA = 4218,
	ARM_t2SRSIA_UPD = 4219,
	ARM_t2SSAT = 4220,
	ARM_t2SSAT16 = 4221,
	ARM_t2SSAX = 4222,
	ARM_t2SSUB16 = 4223,
	ARM_t2SSUB8 = 4224,
	ARM_t2STC2L_OFFSET = 4225,
	ARM_t2STC2L_OPTION = 4226,
	ARM_t2STC2L_POST = 4227,
	ARM_t2STC2L_PRE = 4228,
	ARM_t2STC2_OFFSET = 4229,
	ARM_t2STC2_OPTION = 4230,
	ARM_t2STC2_POST = 4231,
	ARM_t2STC2_PRE = 4232,
	ARM_t2STCL_OFFSET = 4233,
	ARM_t2STCL_OPTION = 4234,
	ARM_t2STCL_POST = 4235,
	ARM_t2STCL_PRE = 4236,
	ARM_t2STC_OFFSET = 4237,
	ARM_t2STC_OPTION = 4238,
	ARM_t2STC_POST = 4239,
	ARM_t2STC_PRE = 4240,
	ARM_t2STL = 4241,
	ARM_t2STLB = 4242,
	ARM_t2STLEX = 4243,
	ARM_t2STLEXB = 4244,
	ARM_t2STLEXD = 4245,
	ARM_t2STLEXH = 4246,
	ARM_t2STLH = 4247,
	ARM_t2STMDB = 4248,
	ARM_t2STMDB_UPD = 4249,
	ARM_t2STMIA = 4250,
	ARM_t2STMIA_UPD = 4251,
	ARM_t2STRBT = 4252,
	ARM_t2STRB_POST = 4253,
	ARM_t2STRB_PRE = 4254,
	ARM_t2STRBi12 = 4255,
	ARM_t2STRBi8 = 4256,
	ARM_t2STRBs = 4257,
	ARM_t2STRD_POST = 4258,
	ARM_t2STRD_PRE = 4259,
	ARM_t2STRDi8 = 4260,
	ARM_t2STREX = 4261,
	ARM_t2STREXB = 4262,
	ARM_t2STREXD = 4263,
	ARM_t2STREXH = 4264,
	ARM_t2STRHT = 4265,
	ARM_t2STRH_POST = 4266,
	ARM_t2STRH_PRE = 4267,
	ARM_t2STRHi12 = 4268,
	ARM_t2STRHi8 = 4269,
	ARM_t2STRHs = 4270,
	ARM_t2STRT = 4271,
	ARM_t2STR_POST = 4272,
	ARM_t2STR_PRE = 4273,
	ARM_t2STRi12 = 4274,
	ARM_t2STRi8 = 4275,
	ARM_t2STRs = 4276,
	ARM_t2SUBS_PC_LR = 4277,
	ARM_t2SUBri = 4278,
	ARM_t2SUBri12 = 4279,
	ARM_t2SUBrr = 4280,
	ARM_t2SUBrs = 4281,
	ARM_t2SUBspImm = 4282,
	ARM_t2SUBspImm12 = 4283,
	ARM_t2SXTAB = 4284,
	ARM_t2SXTAB16 = 4285,
	ARM_t2SXTAH = 4286,
	ARM_t2SXTB = 4287,
	ARM_t2SXTB16 = 4288,
	ARM_t2SXTH = 4289,
	ARM_t2TBB = 4290,
	ARM_t2TBH = 4291,
	ARM_t2TEQri = 4292,
	ARM_t2TEQrr = 4293,
	ARM_t2TEQrs = 4294,
	ARM_t2TSB = 4295,
	ARM_t2TSTri = 4296,
	ARM_t2TSTrr = 4297,
	ARM_t2TSTrs = 4298,
	ARM_t2TT = 4299,
	ARM_t2TTA = 4300,
	ARM_t2TTAT = 4301,
	ARM_t2TTT = 4302,
	ARM_t2UADD16 = 4303,
	ARM_t2UADD8 = 4304,
	ARM_t2UASX = 4305,
	ARM_t2UBFX = 4306,
	ARM_t2UDF = 4307,
	ARM_t2UDIV = 4308,
	ARM_t2UHADD16 = 4309,
	ARM_t2UHADD8 = 4310,
	ARM_t2UHASX = 4311,
	ARM_t2UHSAX = 4312,
	ARM_t2UHSUB16 = 4313,
	ARM_t2UHSUB8 = 4314,
	ARM_t2UMAAL = 4315,
	ARM_t2UMLAL = 4316,
	ARM_t2UMULL = 4317,
	ARM_t2UQADD16 = 4318,
	ARM_t2UQADD8 = 4319,
	ARM_t2UQASX = 4320,
	ARM_t2UQSAX = 4321,
	ARM_t2UQSUB16 = 4322,
	ARM_t2UQSUB8 = 4323,
	ARM_t2USAD8 = 4324,
	ARM_t2USADA8 = 4325,
	ARM_t2USAT = 4326,
	ARM_t2USAT16 = 4327,
	ARM_t2USAX = 4328,
	ARM_t2USUB16 = 4329,
	ARM_t2USUB8 = 4330,
	ARM_t2UXTAB = 4331,
	ARM_t2UXTAB16 = 4332,
	ARM_t2UXTAH = 4333,
	ARM_t2UXTB = 4334,
	ARM_t2UXTB16 = 4335,
	ARM_t2UXTH = 4336,
	ARM_t2WLS = 4337,
	ARM_tADC = 4338,
	ARM_tADDhirr = 4339,
	ARM_tADDi3 = 4340,
	ARM_tADDi8 = 4341,
	ARM_tADDrSP = 4342,
	ARM_tADDrSPi = 4343,
	ARM_tADDrr = 4344,
	ARM_tADDspi = 4345,
	ARM_tADDspr = 4346,
	ARM_tADR = 4347,
	ARM_tAND = 4348,
	ARM_tASRri = 4349,
	ARM_tASRrr = 4350,
	ARM_tB = 4351,
	ARM_tBIC = 4352,
	ARM_tBKPT = 4353,
	ARM_tBL = 4354,
	ARM_tBLXNSr = 4355,
	ARM_tBLXi = 4356,
	ARM_tBLXr = 4357,
	ARM_tBX = 4358,
	ARM_tBXNS = 4359,
	ARM_tBcc = 4360,
	ARM_tCBNZ = 4361,
	ARM_tCBZ = 4362,
	ARM_tCMNz = 4363,
	ARM_tCMPhir = 4364,
	ARM_tCMPi8 = 4365,
	ARM_tCMPr = 4366,
	ARM_tCPS = 4367,
	ARM_tEOR = 4368,
	ARM_tHINT = 4369,
	ARM_tHLT = 4370,
	ARM_tInt_WIN_eh_sjlj_longjmp = 4371,
	ARM_tInt_eh_sjlj_longjmp = 4372,
	ARM_tInt_eh_sjlj_setjmp = 4373,
	ARM_tLDMIA = 4374,
	ARM_tLDRBi = 4375,
	ARM_tLDRBr = 4376,
	ARM_tLDRHi = 4377,
	ARM_tLDRHr = 4378,
	ARM_tLDRSB = 4379,
	ARM_tLDRSH = 4380,
	ARM_tLDRi = 4381,
	ARM_tLDRpci = 4382,
	ARM_tLDRr = 4383,
	ARM_tLDRspi = 4384,
	ARM_tLSLri = 4385,
	ARM_tLSLrr = 4386,
	ARM_tLSRri = 4387,
	ARM_tLSRrr = 4388,
	ARM_tMOVSr = 4389,
	ARM_tMOVi8 = 4390,
	ARM_tMOVr = 4391,
	ARM_tMUL = 4392,
	ARM_tMVN = 4393,
	ARM_tORR = 4394,
	ARM_tPICADD = 4395,
	ARM_tPOP = 4396,
	ARM_tPUSH = 4397,
	ARM_tREV = 4398,
	ARM_tREV16 = 4399,
	ARM_tREVSH = 4400,
	ARM_tROR = 4401,
	ARM_tRSB = 4402,
	ARM_tSBC = 4403,
	ARM_tSETEND = 4404,
	ARM_tSTMIA_UPD = 4405,
	ARM_tSTRBi = 4406,
	ARM_tSTRBr = 4407,
	ARM_tSTRHi = 4408,
	ARM_tSTRHr = 4409,
	ARM_tSTRi = 4410,
	ARM_tSTRr = 4411,
	ARM_tSTRspi = 4412,
	ARM_tSUBi3 = 4413,
	ARM_tSUBi8 = 4414,
	ARM_tSUBrr = 4415,
	ARM_tSUBspi = 4416,
	ARM_tSVC = 4417,
	ARM_tSXTB = 4418,
	ARM_tSXTH = 4419,
	ARM_tTRAP = 4420,
	ARM_tTST = 4421,
	ARM_tUDF = 4422,
	ARM_tUXTB = 4423,
	ARM_tUXTH = 4424,
	ARM_t__brkdiv0 = 4425,
	INSTRUCTION_LIST_END = 4426
};

#endif // GET_INSTRINFO_ENUM

#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC

static const MCOperandInfo OperandInfo2[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo3[] = {
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
};
static const MCOperandInfo OperandInfo4[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
};
static const MCOperandInfo OperandInfo5[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
};
static const MCOperandInfo OperandInfo6[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
};
static const MCOperandInfo OperandInfo7[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo8[] = {
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
};
static const MCOperandInfo OperandInfo9[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, CONSTRAINT_MCOI_TIED_TO(0) },
};
static const MCOperandInfo OperandInfo10[] = {
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
};
static const MCOperandInfo OperandInfo11[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
};
static const MCOperandInfo OperandInfo12[] = {
	{ 0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo13[] = {
	{ 0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
};
static const MCOperandInfo OperandInfo14[] = {
	{ 0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
};
static const MCOperandInfo OperandInfo15[] = {
	{ 0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo16[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ 0, 0 | (1 << MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo17[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 },
};
static const MCOperandInfo OperandInfo18[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
};
static const MCOperandInfo OperandInfo19[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
};
static const MCOperandInfo OperandInfo20[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
};
static const MCOperandInfo OperandInfo21[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo22[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 },
};
static const MCOperandInfo OperandInfo23[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
};
static const MCOperandInfo OperandInfo24[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 },
};
static const MCOperandInfo OperandInfo25[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
};
static const MCOperandInfo OperandInfo26[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
};
static const MCOperandInfo OperandInfo27[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_2, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo28[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_2, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo29[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_2, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
};
static const MCOperandInfo OperandInfo30[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
};
static const MCOperandInfo OperandInfo31[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
};
static const MCOperandInfo OperandInfo32[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo33[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
};
static const MCOperandInfo OperandInfo34[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
};
static const MCOperandInfo OperandInfo35[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
};
static const MCOperandInfo OperandInfo36[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
};
static const MCOperandInfo OperandInfo37[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 },
};
static const MCOperandInfo OperandInfo38[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
};
static const MCOperandInfo OperandInfo39[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_2, 0 },
};
static const MCOperandInfo OperandInfo40[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_2, 0 },
};
static const MCOperandInfo OperandInfo41[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo42[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
};
static const MCOperandInfo OperandInfo43[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_2, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 },
};
static const MCOperandInfo OperandInfo44[] = {
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_0, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
	{ -1, 0, MCOI_OPERAND_GENERIC_1, 0 },
};
static const MCOperandInfo OperandInfo45[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo46[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo47[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo48[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo49[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo50[] = {
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo51[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo52[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo53[] = {
	{ -1, 0, MCOI_OPERAND_PCREL, 0 },
};
static const MCOperandInfo OperandInfo54[] = {
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_PCREL, 0 },
};
static const MCOperandInfo OperandInfo55[] = {
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_PCREL, 0 },
};
static const MCOperandInfo OperandInfo56[] = {
	{ ARM_GPRnoipRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo57[] = {
	{ ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_PCREL, 0 },
};
static const MCOperandInfo OperandInfo58[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo59[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
};
static const MCOperandInfo OperandInfo60[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
};
static const MCOperandInfo OperandInfo61[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
};
static const MCOperandInfo OperandInfo62[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
};
static const MCOperandInfo OperandInfo63[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo64[] = {
	{ ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo65[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
};
static const MCOperandInfo OperandInfo66[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo67[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo68[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo69[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo70[] = {
	{ ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
};
static const MCOperandInfo OperandInfo71[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
};
static const MCOperandInfo OperandInfo72[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo73[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo74[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo75[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo76[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo77[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo78[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo79[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo80[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo81[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo82[] = {
	{ ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo83[] = {
	{ ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo84[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo85[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo86[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo87[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo88[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo89[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo90[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo91[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo92[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo93[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo94[] = {
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo95[] = {
	{ ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo96[] = {
	{ ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
};
static const MCOperandInfo OperandInfo97[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo98[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo99[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo100[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo101[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo102[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo103[] = {
	{ ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo104[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo105[] = {
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo106[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo107[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo108[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo109[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo110[] = {
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_PCREL, 0 },
};
static const MCOperandInfo OperandInfo111[] = {
	{ ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo112[] = {
	{ ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo113[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo114[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
};
static const MCOperandInfo OperandInfo115[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo116[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo117[] = {
	{ ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo118[] = {
	{ ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_PCREL, 0 },
};
static const MCOperandInfo OperandInfo119[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo120[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo121[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo122[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo123[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo124[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo125[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo126[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo127[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo128[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo129[] = {
	{ ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_PCREL, 0 },
};
static const MCOperandInfo OperandInfo130[] = {
	{ ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_PCREL, 0 },
};
static const MCOperandInfo OperandInfo131[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo132[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo133[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
};
static const MCOperandInfo OperandInfo134[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo135[] = {
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRnoipRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo136[] = {
	{ ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_PCREL, 0 },
};
static const MCOperandInfo OperandInfo137[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo138[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
};
static const MCOperandInfo OperandInfo139[] = {
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo140[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo141[] = {
	{ -1, 0, MCOI_OPERAND_PCREL, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo142[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo143[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo144[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo145[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo146[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo147[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo148[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo149[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo150[] = {
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo151[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo152[] = {
	{ ARM_tGPRwithpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
};
static const MCOperandInfo OperandInfo153[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo154[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo155[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo156[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo157[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo158[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo159[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo160[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo161[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo162[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo163[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo164[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo165[] = {
	{ ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo166[] = {
	{ ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo167[] = {
	{ ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo168[] = {
	{ ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo169[] = {
	{ ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo170[] = {
	{ ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo171[] = {
	{ ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo172[] = {
	{ ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo173[] = {
	{ ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo174[] = {
	{ ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo175[] = {
	{ ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo176[] = {
	{ ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo177[] = {
	{ ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo178[] = {
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo179[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo180[] = {
	{ ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo181[] = {
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo182[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
};
static const MCOperandInfo OperandInfo183[] = {
	{ ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo184[] = {
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo185[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo186[] = {
	{ ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo187[] = {
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo188[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
};
static const MCOperandInfo OperandInfo189[] = {
	{ ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo190[] = {
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo191[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo192[] = {
	{ ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo193[] = {
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo194[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
};
static const MCOperandInfo OperandInfo195[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo196[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo197[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo198[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo199[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo200[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo201[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo202[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo203[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo204[] = {
	{ ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo205[] = {
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo206[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo207[] = {
	{ ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo208[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
};
static const MCOperandInfo OperandInfo209[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo210[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
};
static const MCOperandInfo OperandInfo211[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo212[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo213[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo214[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo215[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo216[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo217[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo218[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo219[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(2) },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo220[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo221[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo222[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo223[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo224[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo225[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo226[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo227[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo228[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo229[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo230[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo231[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo232[] = {
	{ ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo233[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo234[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo235[] = {
	{ ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo236[] = {
	{ ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo237[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo238[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo239[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo240[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo241[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo242[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo243[] = {
	{ ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo244[] = {
	{ ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo245[] = {
	{ ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo246[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo247[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
};
static const MCOperandInfo OperandInfo248[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
};
static const MCOperandInfo OperandInfo249[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_cl_FPSCR_NZCVRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_cl_FPSCR_NZCVRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
};
static const MCOperandInfo OperandInfo250[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_cl_FPSCR_NZCVRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
};
static const MCOperandInfo OperandInfo251[] = {
	{ ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo252[] = {
	{ ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo253[] = {
	{ ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo254[] = {
	{ ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo255[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
};
static const MCOperandInfo OperandInfo256[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo257[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
};
static const MCOperandInfo OperandInfo258[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
};
static const MCOperandInfo OperandInfo259[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo260[] = {
	{ ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo261[] = {
	{ ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRwithZRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo262[] = {
	{ ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo263[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo264[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
};
static const MCOperandInfo OperandInfo265[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
};
static const MCOperandInfo OperandInfo266[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
};
static const MCOperandInfo OperandInfo267[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
};
static const MCOperandInfo OperandInfo268[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo269[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo270[] = {
	{ ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
};
static const MCOperandInfo OperandInfo271[] = {
	{ ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(1) },
};
static const MCOperandInfo OperandInfo272[] = {
	{ ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
};
static const MCOperandInfo OperandInfo273[] = {
	{ ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(1) },
};
static const MCOperandInfo OperandInfo274[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo275[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo276[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo277[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo278[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo279[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo280[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo281[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo282[] = {
	{ ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo283[] = {
	{ ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo284[] = {
	{ ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo285[] = {
	{ ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo286[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo287[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo288[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo289[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo290[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
};
static const MCOperandInfo OperandInfo291[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
};
static const MCOperandInfo OperandInfo292[] = {
	{ ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo293[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo294[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo295[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRwithZRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo296[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo297[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
};
static const MCOperandInfo OperandInfo298[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo299[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo300[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 },
	{ ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) },
};
static const MCOperandInfo OperandInfo301[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo302[] = {
	{ ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
};
static const MCOperandInfo OperandInfo303[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
};
static const MCOperandInfo OperandInfo304[] = {
	{ ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
};
static const MCOperandInfo OperandInfo305[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
};
static const MCOperandInfo OperandInfo306[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo307[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo308[] = {
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 },
	{ ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 },
};
static const MCOperandInfo OperandInfo309[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo310[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo311[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo312[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo313[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
};
static const MCOperandInfo OperandInfo314[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
};
static const MCOperandInfo OperandInfo315[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo316[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
};
static const MCOperandInfo OperandInfo317[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo318[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo319[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo320[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo321[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo322[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo323[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo324[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo325[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo326[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo327[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo328[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo329[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo330[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo331[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo332[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo333[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo334[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo335[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo336[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo337[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo338[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo339[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo340[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo341[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo342[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo343[] = {
	{ ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo344[] = {
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo345[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo346[] = {
	{ ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo347[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo348[] = {
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo349[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo350[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo351[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo352[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo353[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo354[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo355[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo356[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo357[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo358[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo359[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo360[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo361[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo362[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo363[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo364[] = {
	{ ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo365[] = {
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo366[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo367[] = {
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo368[] = {
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo369[] = {
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo370[] = {
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo371[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo372[] = {
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo373[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo374[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo375[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo376[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo377[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo378[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo379[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo380[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo381[] = {
	{ ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo382[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo383[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_SPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo384[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo385[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo386[] = {
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo387[] = {
	{ ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo388[] = {
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo389[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo390[] = {
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo391[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo392[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo393[] = {
	{ ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo394[] = {
	{ ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo395[] = {
	{ ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo396[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo397[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo398[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo399[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo400[] = {
	{ ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo401[] = {
	{ ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo402[] = {
	{ ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo403[] = {
	{ ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo404[] = {
	{ ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo405[] = {
	{ ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo406[] = {
	{ ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo407[] = {
	{ ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo408[] = {
	{ ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo409[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo410[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(2) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo411[] = {
	{ ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo412[] = {
	{ ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo413[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo414[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(3) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo415[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(2) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo416[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(3) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(2) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo417[] = {
	{ ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo418[] = {
	{ ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo419[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo420[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(4) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo421[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(2) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(3) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo422[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(4) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(2) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(3) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo423[] = {
	{ ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo424[] = {
	{ ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo425[] = {
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo426[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo427[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo428[] = {
	{ ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo429[] = {
	{ ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo430[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo431[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo432[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo433[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo434[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo435[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo436[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo437[] = {
	{ ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo438[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo439[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo440[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo441[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo442[] = {
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo443[] = {
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo444[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo445[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_cl_FPSCR_NZCVRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo446[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo447[] = {
	{ ARM_cl_FPSCR_NZCVRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo448[] = {
	{ ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo449[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo450[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo451[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo452[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo453[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo454[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo455[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo456[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo457[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo458[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo459[] = {
	{ ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo460[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo461[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo462[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo463[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo464[] = {
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo465[] = {
	{ ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo466[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo467[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo468[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo469[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo470[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo471[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo472[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo473[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo474[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo475[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo476[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo477[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo478[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo479[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo480[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo481[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo482[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo483[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo484[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo485[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo486[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo487[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo488[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo489[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo490[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo491[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo492[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo493[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo494[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo495[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo496[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo497[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo498[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo499[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo500[] = {
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo501[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo502[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo503[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo504[] = {
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo505[] = {
	{ ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo506[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo507[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo508[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo509[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo510[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo511[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo512[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo513[] = {
	{ ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo514[] = {
	{ ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo515[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo516[] = {
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo517[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo518[] = {
	{ -1, 0, MCOI_OPERAND_PCREL, 0 },
	{ -1, 0, MCOI_OPERAND_PCREL, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo519[] = {
	{ -1, 0, MCOI_OPERAND_PCREL, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo520[] = {
	{ -1, 0, MCOI_OPERAND_PCREL, 0 },
	{ -1, 0, MCOI_OPERAND_PCREL, 0 },
	{ -1, 0, MCOI_OPERAND_PCREL, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo521[] = {
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo522[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo523[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo524[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo525[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRwithZRnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRwithZRnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo526[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo527[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo528[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo529[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo530[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo531[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(2) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo532[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo533[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo534[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo535[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo536[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo537[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo538[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo539[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo540[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo541[] = {
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo542[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo543[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo544[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
};
static const MCOperandInfo OperandInfo545[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo546[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo547[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo548[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo549[] = {
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo550[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo551[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(1) },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo552[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo553[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo554[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo555[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo556[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo557[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo558[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo559[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo560[] = {
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_EARLY_CLOBBER },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo561[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo562[] = {
	{ ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo563[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo564[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo565[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo566[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo567[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo568[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo569[] = {
	{ ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_IMMEDIATE, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo570[] = {
	{ ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo571[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_PCREL, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo572[] = {
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo573[] = {
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
};
static const MCOperandInfo OperandInfo574[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_PCREL, 0 },
};
static const MCOperandInfo OperandInfo575[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo576[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo577[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo578[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo579[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo580[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0, MCOI_OPERAND_MEMORY, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo581[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo582[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo583[] = {
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_CCRRegClassID, 0 | (1 << MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN,
	  0 },
	{ ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
	{ -1, 0 | (1 << MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 },
};
static const MCOperandInfo OperandInfo584[] = {
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 },
	{ ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER,
	  CONSTRAINT_MCOI_TIED_TO(0) },
	{ -1, 0, MCOI_OPERAND_UNKNOWN, 0 },
};

static const MCInstrDesc ARMInsts[] = {
	{ 1, OperandInfo2 },	// Inst #0 = PHI
	{ 0, 0 },		// Inst #1 = INLINEASM
	{ 0, 0 },		// Inst #2 = INLINEASM_BR
	{ 1, OperandInfo3 },	// Inst #3 = CFI_INSTRUCTION
	{ 1, OperandInfo3 },	// Inst #4 = EH_LABEL
	{ 1, OperandInfo3 },	// Inst #5 = GC_LABEL
	{ 1, OperandInfo3 },	// Inst #6 = ANNOTATION_LABEL
	{ 0, 0 },		// Inst #7 = KILL
	{ 3, OperandInfo4 },	// Inst #8 = EXTRACT_SUBREG
	{ 4, OperandInfo5 },	// Inst #9 = INSERT_SUBREG
	{ 1, OperandInfo2 },	// Inst #10 = IMPLICIT_DEF
	{ 4, OperandInfo6 },	// Inst #11 = SUBREG_TO_REG
	{ 3, OperandInfo4 },	// Inst #12 = COPY_TO_REGCLASS
	{ 0, 0 },		// Inst #13 = DBG_VALUE
	{ 0, 0 },		// Inst #14 = DBG_VALUE_LIST
	{ 0, 0 },		// Inst #15 = DBG_INSTR_REF
	{ 0, 0 },		// Inst #16 = DBG_PHI
	{ 1, OperandInfo2 },	// Inst #17 = DBG_LABEL
	{ 2, OperandInfo7 },	// Inst #18 = REG_SEQUENCE
	{ 2, OperandInfo7 },	// Inst #19 = COPY
	{ 0, 0 },		// Inst #20 = BUNDLE
	{ 1, OperandInfo3 },	// Inst #21 = LIFETIME_START
	{ 1, OperandInfo3 },	// Inst #22 = LIFETIME_END
	{ 4, OperandInfo8 },	// Inst #23 = PSEUDO_PROBE
	{ 2, OperandInfo9 },	// Inst #24 = ARITH_FENCE
	{ 2, OperandInfo10 },	// Inst #25 = STACKMAP
	{ 0, 0 },		// Inst #26 = FENTRY_CALL
	{ 6, OperandInfo11 },	// Inst #27 = PATCHPOINT
	{ 1, OperandInfo12 },	// Inst #28 = LOAD_STACK_GUARD
	{ 1, OperandInfo3 },	// Inst #29 = PREALLOCATED_SETUP
	{ 3, OperandInfo13 },	// Inst #30 = PREALLOCATED_ARG
	{ 0, 0 },		// Inst #31 = STATEPOINT
	{ 2, OperandInfo14 },	// Inst #32 = LOCAL_ESCAPE
	{ 1, OperandInfo2 },	// Inst #33 = FAULTING_OP
	{ 0, 0 },		// Inst #34 = PATCHABLE_OP
	{ 0, 0 },		// Inst #35 = PATCHABLE_FUNCTION_ENTER
	{ 0, 0 },		// Inst #36 = PATCHABLE_RET
	{ 0, 0 },		// Inst #37 = PATCHABLE_FUNCTION_EXIT
	{ 0, 0 },		// Inst #38 = PATCHABLE_TAIL_CALL
	{ 2, OperandInfo15 },	// Inst #39 = PATCHABLE_EVENT_CALL
	{ 3, OperandInfo16 },	// Inst #40 = PATCHABLE_TYPED_EVENT_CALL
	{ 0, 0 },		// Inst #41 = ICALL_BRANCH_FUNNEL
	{ 0, 0 },		// Inst #42 = MEMBARRIER
	{ 3, OperandInfo17 },	// Inst #43 = G_ASSERT_SEXT
	{ 3, OperandInfo17 },	// Inst #44 = G_ASSERT_ZEXT
	{ 3, OperandInfo17 },	// Inst #45 = G_ASSERT_ALIGN
	{ 3, OperandInfo18 },	// Inst #46 = G_ADD
	{ 3, OperandInfo18 },	// Inst #47 = G_SUB
	{ 3, OperandInfo18 },	// Inst #48 = G_MUL
	{ 3, OperandInfo18 },	// Inst #49 = G_SDIV
	{ 3, OperandInfo18 },	// Inst #50 = G_UDIV
	{ 3, OperandInfo18 },	// Inst #51 = G_SREM
	{ 3, OperandInfo18 },	// Inst #52 = G_UREM
	{ 4, OperandInfo19 },	// Inst #53 = G_SDIVREM
	{ 4, OperandInfo19 },	// Inst #54 = G_UDIVREM
	{ 3, OperandInfo18 },	// Inst #55 = G_AND
	{ 3, OperandInfo18 },	// Inst #56 = G_OR
	{ 3, OperandInfo18 },	// Inst #57 = G_XOR
	{ 1, OperandInfo20 },	// Inst #58 = G_IMPLICIT_DEF
	{ 1, OperandInfo20 },	// Inst #59 = G_PHI
	{ 2, OperandInfo21 },	// Inst #60 = G_FRAME_INDEX
	{ 2, OperandInfo21 },	// Inst #61 = G_GLOBAL_VALUE
	{ 3, OperandInfo22 },	// Inst #62 = G_EXTRACT
	{ 2, OperandInfo23 },	// Inst #63 = G_UNMERGE_VALUES
	{ 4, OperandInfo24 },	// Inst #64 = G_INSERT
	{ 2, OperandInfo23 },	// Inst #65 = G_MERGE_VALUES
	{ 2, OperandInfo23 },	// Inst #66 = G_BUILD_VECTOR
	{ 2, OperandInfo23 },	// Inst #67 = G_BUILD_VECTOR_TRUNC
	{ 2, OperandInfo23 },	// Inst #68 = G_CONCAT_VECTORS
	{ 2, OperandInfo23 },	// Inst #69 = G_PTRTOINT
	{ 2, OperandInfo23 },	// Inst #70 = G_INTTOPTR
	{ 2, OperandInfo23 },	// Inst #71 = G_BITCAST
	{ 2, OperandInfo25 },	// Inst #72 = G_FREEZE
	{ 3, OperandInfo26 },	// Inst #73 = G_INTRINSIC_FPTRUNC_ROUND
	{ 2, OperandInfo25 },	// Inst #74 = G_INTRINSIC_TRUNC
	{ 2, OperandInfo25 },	// Inst #75 = G_INTRINSIC_ROUND
	{ 2, OperandInfo23 },	// Inst #76 = G_INTRINSIC_LRINT
	{ 2, OperandInfo25 },	// Inst #77 = G_INTRINSIC_ROUNDEVEN
	{ 1, OperandInfo20 },	// Inst #78 = G_READCYCLECOUNTER
	{ 2, OperandInfo23 },	// Inst #79 = G_LOAD
	{ 2, OperandInfo23 },	// Inst #80 = G_SEXTLOAD
	{ 2, OperandInfo23 },	// Inst #81 = G_ZEXTLOAD
	{ 5, OperandInfo27 },	// Inst #82 = G_INDEXED_LOAD
	{ 5, OperandInfo27 },	// Inst #83 = G_INDEXED_SEXTLOAD
	{ 5, OperandInfo27 },	// Inst #84 = G_INDEXED_ZEXTLOAD
	{ 2, OperandInfo23 },	// Inst #85 = G_STORE
	{ 5, OperandInfo28 },	// Inst #86 = G_INDEXED_STORE
	{ 5, OperandInfo29 },	// Inst #87 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
	{ 4, OperandInfo30 },	// Inst #88 = G_ATOMIC_CMPXCHG
	{ 3, OperandInfo31 },	// Inst #89 = G_ATOMICRMW_XCHG
	{ 3, OperandInfo31 },	// Inst #90 = G_ATOMICRMW_ADD
	{ 3, OperandInfo31 },	// Inst #91 = G_ATOMICRMW_SUB
	{ 3, OperandInfo31 },	// Inst #92 = G_ATOMICRMW_AND
	{ 3, OperandInfo31 },	// Inst #93 = G_ATOMICRMW_NAND
	{ 3, OperandInfo31 },	// Inst #94 = G_ATOMICRMW_OR
	{ 3, OperandInfo31 },	// Inst #95 = G_ATOMICRMW_XOR
	{ 3, OperandInfo31 },	// Inst #96 = G_ATOMICRMW_MAX
	{ 3, OperandInfo31 },	// Inst #97 = G_ATOMICRMW_MIN
	{ 3, OperandInfo31 },	// Inst #98 = G_ATOMICRMW_UMAX
	{ 3, OperandInfo31 },	// Inst #99 = G_ATOMICRMW_UMIN
	{ 3, OperandInfo31 },	// Inst #100 = G_ATOMICRMW_FADD
	{ 3, OperandInfo31 },	// Inst #101 = G_ATOMICRMW_FSUB
	{ 3, OperandInfo31 },	// Inst #102 = G_ATOMICRMW_FMAX
	{ 3, OperandInfo31 },	// Inst #103 = G_ATOMICRMW_FMIN
	{ 3, OperandInfo31 },	// Inst #104 = G_ATOMICRMW_UINC_WRAP
	{ 3, OperandInfo31 },	// Inst #105 = G_ATOMICRMW_UDEC_WRAP
	{ 2, OperandInfo10 },	// Inst #106 = G_FENCE
	{ 2, OperandInfo21 },	// Inst #107 = G_BRCOND
	{ 1, OperandInfo20 },	// Inst #108 = G_BRINDIRECT
	{ 0, 0 },		// Inst #109 = G_INVOKE_REGION_START
	{ 1, OperandInfo2 },	// Inst #110 = G_INTRINSIC
	{ 1, OperandInfo2 },	// Inst #111 = G_INTRINSIC_W_SIDE_EFFECTS
	{ 2, OperandInfo23 },	// Inst #112 = G_ANYEXT
	{ 2, OperandInfo23 },	// Inst #113 = G_TRUNC
	{ 2, OperandInfo21 },	// Inst #114 = G_CONSTANT
	{ 2, OperandInfo21 },	// Inst #115 = G_FCONSTANT
	{ 1, OperandInfo20 },	// Inst #116 = G_VASTART
	{ 3, OperandInfo32 },	// Inst #117 = G_VAARG
	{ 2, OperandInfo23 },	// Inst #118 = G_SEXT
	{ 3, OperandInfo17 },	// Inst #119 = G_SEXT_INREG
	{ 2, OperandInfo23 },	// Inst #120 = G_ZEXT
	{ 3, OperandInfo33 },	// Inst #121 = G_SHL
	{ 3, OperandInfo33 },	// Inst #122 = G_LSHR
	{ 3, OperandInfo33 },	// Inst #123 = G_ASHR
	{ 4, OperandInfo34 },	// Inst #124 = G_FSHL
	{ 4, OperandInfo34 },	// Inst #125 = G_FSHR
	{ 3, OperandInfo33 },	// Inst #126 = G_ROTR
	{ 3, OperandInfo33 },	// Inst #127 = G_ROTL
	{ 4, OperandInfo35 },	// Inst #128 = G_ICMP
	{ 4, OperandInfo35 },	// Inst #129 = G_FCMP
	{ 4, OperandInfo30 },	// Inst #130 = G_SELECT
	{ 4, OperandInfo30 },	// Inst #131 = G_UADDO
	{ 5, OperandInfo36 },	// Inst #132 = G_UADDE
	{ 4, OperandInfo30 },	// Inst #133 = G_USUBO
	{ 5, OperandInfo36 },	// Inst #134 = G_USUBE
	{ 4, OperandInfo30 },	// Inst #135 = G_SADDO
	{ 5, OperandInfo36 },	// Inst #136 = G_SADDE
	{ 4, OperandInfo30 },	// Inst #137 = G_SSUBO
	{ 5, OperandInfo36 },	// Inst #138 = G_SSUBE
	{ 4, OperandInfo30 },	// Inst #139 = G_UMULO
	{ 4, OperandInfo30 },	// Inst #140 = G_SMULO
	{ 3, OperandInfo18 },	// Inst #141 = G_UMULH
	{ 3, OperandInfo18 },	// Inst #142 = G_SMULH
	{ 3, OperandInfo18 },	// Inst #143 = G_UADDSAT
	{ 3, OperandInfo18 },	// Inst #144 = G_SADDSAT
	{ 3, OperandInfo18 },	// Inst #145 = G_USUBSAT
	{ 3, OperandInfo18 },	// Inst #146 = G_SSUBSAT
	{ 3, OperandInfo33 },	// Inst #147 = G_USHLSAT
	{ 3, OperandInfo33 },	// Inst #148 = G_SSHLSAT
	{ 4, OperandInfo37 },	// Inst #149 = G_SMULFIX
	{ 4, OperandInfo37 },	// Inst #150 = G_UMULFIX
	{ 4, OperandInfo37 },	// Inst #151 = G_SMULFIXSAT
	{ 4, OperandInfo37 },	// Inst #152 = G_UMULFIXSAT
	{ 4, OperandInfo37 },	// Inst #153 = G_SDIVFIX
	{ 4, OperandInfo37 },	// Inst #154 = G_UDIVFIX
	{ 4, OperandInfo37 },	// Inst #155 = G_SDIVFIXSAT
	{ 4, OperandInfo37 },	// Inst #156 = G_UDIVFIXSAT
	{ 3, OperandInfo18 },	// Inst #157 = G_FADD
	{ 3, OperandInfo18 },	// Inst #158 = G_FSUB
	{ 3, OperandInfo18 },	// Inst #159 = G_FMUL
	{ 4, OperandInfo19 },	// Inst #160 = G_FMA
	{ 4, OperandInfo19 },	// Inst #161 = G_FMAD
	{ 3, OperandInfo18 },	// Inst #162 = G_FDIV
	{ 3, OperandInfo18 },	// Inst #163 = G_FREM
	{ 3, OperandInfo18 },	// Inst #164 = G_FPOW
	{ 3, OperandInfo33 },	// Inst #165 = G_FPOWI
	{ 2, OperandInfo25 },	// Inst #166 = G_FEXP
	{ 2, OperandInfo25 },	// Inst #167 = G_FEXP2
	{ 2, OperandInfo25 },	// Inst #168 = G_FLOG
	{ 2, OperandInfo25 },	// Inst #169 = G_FLOG2
	{ 2, OperandInfo25 },	// Inst #170 = G_FLOG10
	{ 2, OperandInfo25 },	// Inst #171 = G_FNEG
	{ 2, OperandInfo23 },	// Inst #172 = G_FPEXT
	{ 2, OperandInfo23 },	// Inst #173 = G_FPTRUNC
	{ 2, OperandInfo23 },	// Inst #174 = G_FPTOSI
	{ 2, OperandInfo23 },	// Inst #175 = G_FPTOUI
	{ 2, OperandInfo23 },	// Inst #176 = G_SITOFP
	{ 2, OperandInfo23 },	// Inst #177 = G_UITOFP
	{ 2, OperandInfo25 },	// Inst #178 = G_FABS
	{ 3, OperandInfo33 },	// Inst #179 = G_FCOPYSIGN
	{ 3, OperandInfo32 },	// Inst #180 = G_IS_FPCLASS
	{ 2, OperandInfo25 },	// Inst #181 = G_FCANONICALIZE
	{ 3, OperandInfo18 },	// Inst #182 = G_FMINNUM
	{ 3, OperandInfo18 },	// Inst #183 = G_FMAXNUM
	{ 3, OperandInfo18 },	// Inst #184 = G_FMINNUM_IEEE
	{ 3, OperandInfo18 },	// Inst #185 = G_FMAXNUM_IEEE
	{ 3, OperandInfo18 },	// Inst #186 = G_FMINIMUM
	{ 3, OperandInfo18 },	// Inst #187 = G_FMAXIMUM
	{ 3, OperandInfo33 },	// Inst #188 = G_PTR_ADD
	{ 3, OperandInfo33 },	// Inst #189 = G_PTRMASK
	{ 3, OperandInfo18 },	// Inst #190 = G_SMIN
	{ 3, OperandInfo18 },	// Inst #191 = G_SMAX
	{ 3, OperandInfo18 },	// Inst #192 = G_UMIN
	{ 3, OperandInfo18 },	// Inst #193 = G_UMAX
	{ 2, OperandInfo25 },	// Inst #194 = G_ABS
	{ 2, OperandInfo23 },	// Inst #195 = G_LROUND
	{ 2, OperandInfo23 },	// Inst #196 = G_LLROUND
	{ 1, OperandInfo2 },	// Inst #197 = G_BR
	{ 3, OperandInfo38 },	// Inst #198 = G_BRJT
	{ 4, OperandInfo39 },	// Inst #199 = G_INSERT_VECTOR_ELT
	{ 3, OperandInfo40 },	// Inst #200 = G_EXTRACT_VECTOR_ELT
	{ 4, OperandInfo41 },	// Inst #201 = G_SHUFFLE_VECTOR
	{ 2, OperandInfo23 },	// Inst #202 = G_CTTZ
	{ 2, OperandInfo23 },	// Inst #203 = G_CTTZ_ZERO_UNDEF
	{ 2, OperandInfo23 },	// Inst #204 = G_CTLZ
	{ 2, OperandInfo23 },	// Inst #205 = G_CTLZ_ZERO_UNDEF
	{ 2, OperandInfo23 },	// Inst #206 = G_CTPOP
	{ 2, OperandInfo25 },	// Inst #207 = G_BSWAP
	{ 2, OperandInfo25 },	// Inst #208 = G_BITREVERSE
	{ 2, OperandInfo25 },	// Inst #209 = G_FCEIL
	{ 2, OperandInfo25 },	// Inst #210 = G_FCOS
	{ 2, OperandInfo25 },	// Inst #211 = G_FSIN
	{ 2, OperandInfo25 },	// Inst #212 = G_FSQRT
	{ 2, OperandInfo25 },	// Inst #213 = G_FFLOOR
	{ 2, OperandInfo25 },	// Inst #214 = G_FRINT
	{ 2, OperandInfo25 },	// Inst #215 = G_FNEARBYINT
	{ 2, OperandInfo23 },	// Inst #216 = G_ADDRSPACE_CAST
	{ 2, OperandInfo21 },	// Inst #217 = G_BLOCK_ADDR
	{ 2, OperandInfo21 },	// Inst #218 = G_JUMP_TABLE
	{ 3, OperandInfo26 },	// Inst #219 = G_DYN_STACKALLOC
	{ 3, OperandInfo18 },	// Inst #220 = G_STRICT_FADD
	{ 3, OperandInfo18 },	// Inst #221 = G_STRICT_FSUB
	{ 3, OperandInfo18 },	// Inst #222 = G_STRICT_FMUL
	{ 3, OperandInfo18 },	// Inst #223 = G_STRICT_FDIV
	{ 3, OperandInfo18 },	// Inst #224 = G_STRICT_FREM
	{ 4, OperandInfo19 },	// Inst #225 = G_STRICT_FMA
	{ 2, OperandInfo25 },	// Inst #226 = G_STRICT_FSQRT
	{ 2, OperandInfo21 },	// Inst #227 = G_READ_REGISTER
	{ 2, OperandInfo42 },	// Inst #228 = G_WRITE_REGISTER
	{ 4, OperandInfo43 },	// Inst #229 = G_MEMCPY
	{ 3, OperandInfo40 },	// Inst #230 = G_MEMCPY_INLINE
	{ 4, OperandInfo43 },	// Inst #231 = G_MEMMOVE
	{ 4, OperandInfo43 },	// Inst #232 = G_MEMSET
	{ 3, OperandInfo22 },	// Inst #233 = G_BZERO
	{ 3, OperandInfo40 },	// Inst #234 = G_VECREDUCE_SEQ_FADD
	{ 3, OperandInfo40 },	// Inst #235 = G_VECREDUCE_SEQ_FMUL
	{ 2, OperandInfo23 },	// Inst #236 = G_VECREDUCE_FADD
	{ 2, OperandInfo23 },	// Inst #237 = G_VECREDUCE_FMUL
	{ 2, OperandInfo23 },	// Inst #238 = G_VECREDUCE_FMAX
	{ 2, OperandInfo23 },	// Inst #239 = G_VECREDUCE_FMIN
	{ 2, OperandInfo23 },	// Inst #240 = G_VECREDUCE_ADD
	{ 2, OperandInfo23 },	// Inst #241 = G_VECREDUCE_MUL
	{ 2, OperandInfo23 },	// Inst #242 = G_VECREDUCE_AND
	{ 2, OperandInfo23 },	// Inst #243 = G_VECREDUCE_OR
	{ 2, OperandInfo23 },	// Inst #244 = G_VECREDUCE_XOR
	{ 2, OperandInfo23 },	// Inst #245 = G_VECREDUCE_SMAX
	{ 2, OperandInfo23 },	// Inst #246 = G_VECREDUCE_SMIN
	{ 2, OperandInfo23 },	// Inst #247 = G_VECREDUCE_UMAX
	{ 2, OperandInfo23 },	// Inst #248 = G_VECREDUCE_UMIN
	{ 4, OperandInfo44 },	// Inst #249 = G_SBFX
	{ 4, OperandInfo44 },	// Inst #250 = G_UBFX
	{ 2, OperandInfo45 },	// Inst #251 = ABS
	{ 5, OperandInfo46 },	// Inst #252 = ADDSri
	{ 5, OperandInfo47 },	// Inst #253 = ADDSrr
	{ 6, OperandInfo48 },	// Inst #254 = ADDSrsi
	{ 7, OperandInfo49 },	// Inst #255 = ADDSrsr
	{ 4, OperandInfo50 },	// Inst #256 = ADJCALLSTACKDOWN
	{ 4, OperandInfo50 },	// Inst #257 = ADJCALLSTACKUP
	{ 6, OperandInfo51 },	// Inst #258 = ASRi
	{ 6, OperandInfo52 },	// Inst #259 = ASRr
	{ 1, OperandInfo53 },	// Inst #260 = B
	{ 4, OperandInfo54 },	// Inst #261 = BCCZi64
	{ 6, OperandInfo55 },	// Inst #262 = BCCi64
	{ 1, OperandInfo56 },	// Inst #263 = BLX_noip
	{ 1, OperandInfo56 },	// Inst #264 = BLX_pred_noip
	{ 2, OperandInfo57 },	// Inst #265 = BL_PUSHLR
	{ 1, OperandInfo53 },	// Inst #266 = BMOVPCB_CALL
	{ 1, OperandInfo58 },	// Inst #267 = BMOVPCRX_CALL
	{ 3, OperandInfo59 },	// Inst #268 = BR_JTadd
	{ 3, OperandInfo60 },	// Inst #269 = BR_JTm_i12
	{ 4, OperandInfo61 },	// Inst #270 = BR_JTm_rs
	{ 2, OperandInfo62 },	// Inst #271 = BR_JTr
	{ 1, OperandInfo58 },	// Inst #272 = BX_CALL
	{ 5, OperandInfo63 },	// Inst #273 = CMP_SWAP_16
	{ 5, OperandInfo63 },	// Inst #274 = CMP_SWAP_32
	{ 5, OperandInfo64 },	// Inst #275 = CMP_SWAP_64
	{ 5, OperandInfo63 },	// Inst #276 = CMP_SWAP_8
	{ 3, OperandInfo4 },	// Inst #277 = CONSTPOOL_ENTRY
	{ 4, OperandInfo65 },	// Inst #278 = COPY_STRUCT_BYVAL_I32
	{ 2, OperandInfo7 },	// Inst #279 = ITasm
	{ 0, 0 },		// Inst #280 = Int_eh_sjlj_dispatchsetup
	{ 2, OperandInfo45 },	// Inst #281 = Int_eh_sjlj_longjmp
	{ 2, OperandInfo45 },	// Inst #282 = Int_eh_sjlj_setjmp
	{ 2, OperandInfo45 },	// Inst #283 = Int_eh_sjlj_setjmp_nofp
	{ 0, 0 },		// Inst #284 = Int_eh_sjlj_setup_dispatch
	{ 3, OperandInfo4 },	// Inst #285 = JUMPTABLE_ADDRS
	{ 3, OperandInfo4 },	// Inst #286 = JUMPTABLE_INSTS
	{ 3, OperandInfo4 },	// Inst #287 = JUMPTABLE_TBB
	{ 3, OperandInfo4 },	// Inst #288 = JUMPTABLE_TBH
	{ 5, OperandInfo66 },	// Inst #289 = LDMIA_RET
	{ 4, OperandInfo67 },	// Inst #290 = LDRBT_POST
	{ 4, OperandInfo68 },	// Inst #291 = LDRConstPool
	{ 4, OperandInfo67 },	// Inst #292 = LDRHTii
	{ 2, OperandInfo62 },	// Inst #293 = LDRLIT_ga_abs
	{ 2, OperandInfo62 },	// Inst #294 = LDRLIT_ga_pcrel
	{ 2, OperandInfo62 },	// Inst #295 = LDRLIT_ga_pcrel_ldr
	{ 4, OperandInfo67 },	// Inst #296 = LDRSBTii
	{ 4, OperandInfo67 },	// Inst #297 = LDRSHTii
	{ 4, OperandInfo67 },	// Inst #298 = LDRT_POST
	{ 4, OperandInfo69 },	// Inst #299 = LEApcrel
	{ 4, OperandInfo69 },	// Inst #300 = LEApcrelJT
	{ 4, OperandInfo70 },	// Inst #301 = LOADDUAL
	{ 6, OperandInfo51 },	// Inst #302 = LSLi
	{ 6, OperandInfo52 },	// Inst #303 = LSLr
	{ 6, OperandInfo51 },	// Inst #304 = LSRi
	{ 6, OperandInfo52 },	// Inst #305 = LSRr
	{ 5, OperandInfo71 },	// Inst #306 = MEMCPY
	{ 7, OperandInfo72 },	// Inst #307 = MLAv5
	{ 5, OperandInfo73 },	// Inst #308 = MOVCCi
	{ 5, OperandInfo73 },	// Inst #309 = MOVCCi16
	{ 5, OperandInfo74 },	// Inst #310 = MOVCCi32imm
	{ 5, OperandInfo75 },	// Inst #311 = MOVCCr
	{ 6, OperandInfo76 },	// Inst #312 = MOVCCsi
	{ 7, OperandInfo77 },	// Inst #313 = MOVCCsr
	{ 1, OperandInfo78 },	// Inst #314 = MOVPCRX
	{ 4, OperandInfo79 },	// Inst #315 = MOVTi16_ga_pcrel
	{ 2, OperandInfo62 },	// Inst #316 = MOV_ga_pcrel
	{ 2, OperandInfo62 },	// Inst #317 = MOV_ga_pcrel_ldr
	{ 3, OperandInfo80 },	// Inst #318 = MOVi16_ga_pcrel
	{ 2, OperandInfo62 },	// Inst #319 = MOVi32imm
	{ 2, OperandInfo45 },	// Inst #320 = MOVsra_flag
	{ 2, OperandInfo45 },	// Inst #321 = MOVsrl_flag
	{ 2, OperandInfo81 },	// Inst #322 = MQPRCopy
	{ 2, OperandInfo82 },	// Inst #323 = MQQPRLoad
	{ 2, OperandInfo82 },	// Inst #324 = MQQPRStore
	{ 2, OperandInfo83 },	// Inst #325 = MQQQQPRLoad
	{ 2, OperandInfo83 },	// Inst #326 = MQQQQPRStore
	{ 6, OperandInfo84 },	// Inst #327 = MULv5
	{ 3, OperandInfo85 },	// Inst #328 = MVE_MEMCPYLOOPINST
	{ 3, OperandInfo86 },	// Inst #329 = MVE_MEMSETLOOPINST
	{ 5, OperandInfo73 },	// Inst #330 = MVNCCi
	{ 5, OperandInfo46 },	// Inst #331 = PICADD
	{ 5, OperandInfo87 },	// Inst #332 = PICLDR
	{ 5, OperandInfo87 },	// Inst #333 = PICLDRB
	{ 5, OperandInfo87 },	// Inst #334 = PICLDRH
	{ 5, OperandInfo87 },	// Inst #335 = PICLDRSB
	{ 5, OperandInfo87 },	// Inst #336 = PICLDRSH
	{ 5, OperandInfo87 },	// Inst #337 = PICSTR
	{ 5, OperandInfo87 },	// Inst #338 = PICSTRB
	{ 5, OperandInfo87 },	// Inst #339 = PICSTRH
	{ 6, OperandInfo51 },	// Inst #340 = RORi
	{ 6, OperandInfo52 },	// Inst #341 = RORr
	{ 2, OperandInfo45 },	// Inst #342 = RRX
	{ 5, OperandInfo88 },	// Inst #343 = RRXi
	{ 5, OperandInfo46 },	// Inst #344 = RSBSri
	{ 6, OperandInfo48 },	// Inst #345 = RSBSrsi
	{ 7, OperandInfo49 },	// Inst #346 = RSBSrsr
	{ 0, 0 },		// Inst #347 = SEH_EpilogEnd
	{ 0, 0 },		// Inst #348 = SEH_EpilogStart
	{ 1, OperandInfo3 },	// Inst #349 = SEH_Nop
	{ 1, OperandInfo3 },	// Inst #350 = SEH_Nop_Ret
	{ 0, 0 },		// Inst #351 = SEH_PrologEnd
	{ 2, OperandInfo10 },	// Inst #352 = SEH_SaveFRegs
	{ 1, OperandInfo3 },	// Inst #353 = SEH_SaveLR
	{ 2, OperandInfo10 },	// Inst #354 = SEH_SaveRegs
	{ 2, OperandInfo10 },	// Inst #355 = SEH_SaveRegs_Ret
	{ 1, OperandInfo3 },	// Inst #356 = SEH_SaveSP
	{ 2, OperandInfo10 },	// Inst #357 = SEH_StackAlloc
	{ 9, OperandInfo89 },	// Inst #358 = SMLALv5
	{ 7, OperandInfo90 },	// Inst #359 = SMULLv5
	{ 3, OperandInfo91 },	// Inst #360 = SPACE
	{ 4, OperandInfo70 },	// Inst #361 = STOREDUAL
	{ 4, OperandInfo67 },	// Inst #362 = STRBT_POST
	{ 7, OperandInfo92 },	// Inst #363 = STRBi_preidx
	{ 7, OperandInfo92 },	// Inst #364 = STRBr_preidx
	{ 7, OperandInfo93 },	// Inst #365 = STRH_preidx
	{ 4, OperandInfo67 },	// Inst #366 = STRT_POST
	{ 7, OperandInfo92 },	// Inst #367 = STRi_preidx
	{ 7, OperandInfo92 },	// Inst #368 = STRr_preidx
	{ 3, OperandInfo94 },	// Inst #369 = SUBS_PC_LR
	{ 5, OperandInfo46 },	// Inst #370 = SUBSri
	{ 5, OperandInfo47 },	// Inst #371 = SUBSrr
	{ 6, OperandInfo48 },	// Inst #372 = SUBSrsi
	{ 7, OperandInfo49 },	// Inst #373 = SUBSrsr
	{ 0, 0 },		// Inst #374 = SpeculationBarrierISBDSBEndBB
	{ 0, 0 },		// Inst #375 = SpeculationBarrierSBEndBB
	{ 1, OperandInfo53 },	// Inst #376 = TAILJMPd
	{ 1, OperandInfo95 },	// Inst #377 = TAILJMPr
	{ 1, OperandInfo78 },	// Inst #378 = TAILJMPr4
	{ 2, OperandInfo10 },	// Inst #379 = TCRETURNdi
	{ 2, OperandInfo96 },	// Inst #380 = TCRETURNri
	{ 0, 0 },		// Inst #381 = TPsoft
	{ 9, OperandInfo89 },	// Inst #382 = UMLALv5
	{ 7, OperandInfo90 },	// Inst #383 = UMULLv5
	{ 6, OperandInfo97 },	// Inst #384 = VLD1LNdAsm_16
	{ 6, OperandInfo97 },	// Inst #385 = VLD1LNdAsm_32
	{ 6, OperandInfo97 },	// Inst #386 = VLD1LNdAsm_8
	{ 6, OperandInfo97 },	// Inst #387 = VLD1LNdWB_fixed_Asm_16
	{ 6, OperandInfo97 },	// Inst #388 = VLD1LNdWB_fixed_Asm_32
	{ 6, OperandInfo97 },	// Inst #389 = VLD1LNdWB_fixed_Asm_8
	{ 7, OperandInfo98 },	// Inst #390 = VLD1LNdWB_register_Asm_16
	{ 7, OperandInfo98 },	// Inst #391 = VLD1LNdWB_register_Asm_32
	{ 7, OperandInfo98 },	// Inst #392 = VLD1LNdWB_register_Asm_8
	{ 6, OperandInfo97 },	// Inst #393 = VLD2LNdAsm_16
	{ 6, OperandInfo97 },	// Inst #394 = VLD2LNdAsm_32
	{ 6, OperandInfo97 },	// Inst #395 = VLD2LNdAsm_8
	{ 6, OperandInfo97 },	// Inst #396 = VLD2LNdWB_fixed_Asm_16
	{ 6, OperandInfo97 },	// Inst #397 = VLD2LNdWB_fixed_Asm_32
	{ 6, OperandInfo97 },	// Inst #398 = VLD2LNdWB_fixed_Asm_8
	{ 7, OperandInfo98 },	// Inst #399 = VLD2LNdWB_register_Asm_16
	{ 7, OperandInfo98 },	// Inst #400 = VLD2LNdWB_register_Asm_32
	{ 7, OperandInfo98 },	// Inst #401 = VLD2LNdWB_register_Asm_8
	{ 6, OperandInfo97 },	// Inst #402 = VLD2LNqAsm_16
	{ 6, OperandInfo97 },	// Inst #403 = VLD2LNqAsm_32
	{ 6, OperandInfo97 },	// Inst #404 = VLD2LNqWB_fixed_Asm_16
	{ 6, OperandInfo97 },	// Inst #405 = VLD2LNqWB_fixed_Asm_32
	{ 7, OperandInfo98 },	// Inst #406 = VLD2LNqWB_register_Asm_16
	{ 7, OperandInfo98 },	// Inst #407 = VLD2LNqWB_register_Asm_32
	{ 5, OperandInfo99 },	// Inst #408 = VLD3DUPdAsm_16
	{ 5, OperandInfo99 },	// Inst #409 = VLD3DUPdAsm_32
	{ 5, OperandInfo99 },	// Inst #410 = VLD3DUPdAsm_8
	{ 5, OperandInfo99 },	// Inst #411 = VLD3DUPdWB_fixed_Asm_16
	{ 5, OperandInfo99 },	// Inst #412 = VLD3DUPdWB_fixed_Asm_32
	{ 5, OperandInfo99 },	// Inst #413 = VLD3DUPdWB_fixed_Asm_8
	{ 6, OperandInfo100 },	// Inst #414 = VLD3DUPdWB_register_Asm_16
	{ 6, OperandInfo100 },	// Inst #415 = VLD3DUPdWB_register_Asm_32
	{ 6, OperandInfo100 },	// Inst #416 = VLD3DUPdWB_register_Asm_8
	{ 5, OperandInfo99 },	// Inst #417 = VLD3DUPqAsm_16
	{ 5, OperandInfo99 },	// Inst #418 = VLD3DUPqAsm_32
	{ 5, OperandInfo99 },	// Inst #419 = VLD3DUPqAsm_8
	{ 5, OperandInfo99 },	// Inst #420 = VLD3DUPqWB_fixed_Asm_16
	{ 5, OperandInfo99 },	// Inst #421 = VLD3DUPqWB_fixed_Asm_32
	{ 5, OperandInfo99 },	// Inst #422 = VLD3DUPqWB_fixed_Asm_8
	{ 6, OperandInfo100 },	// Inst #423 = VLD3DUPqWB_register_Asm_16
	{ 6, OperandInfo100 },	// Inst #424 = VLD3DUPqWB_register_Asm_32
	{ 6, OperandInfo100 },	// Inst #425 = VLD3DUPqWB_register_Asm_8
	{ 6, OperandInfo97 },	// Inst #426 = VLD3LNdAsm_16
	{ 6, OperandInfo97 },	// Inst #427 = VLD3LNdAsm_32
	{ 6, OperandInfo97 },	// Inst #428 = VLD3LNdAsm_8
	{ 6, OperandInfo97 },	// Inst #429 = VLD3LNdWB_fixed_Asm_16
	{ 6, OperandInfo97 },	// Inst #430 = VLD3LNdWB_fixed_Asm_32
	{ 6, OperandInfo97 },	// Inst #431 = VLD3LNdWB_fixed_Asm_8
	{ 7, OperandInfo98 },	// Inst #432 = VLD3LNdWB_register_Asm_16
	{ 7, OperandInfo98 },	// Inst #433 = VLD3LNdWB_register_Asm_32
	{ 7, OperandInfo98 },	// Inst #434 = VLD3LNdWB_register_Asm_8
	{ 6, OperandInfo97 },	// Inst #435 = VLD3LNqAsm_16
	{ 6, OperandInfo97 },	// Inst #436 = VLD3LNqAsm_32
	{ 6, OperandInfo97 },	// Inst #437 = VLD3LNqWB_fixed_Asm_16
	{ 6, OperandInfo97 },	// Inst #438 = VLD3LNqWB_fixed_Asm_32
	{ 7, OperandInfo98 },	// Inst #439 = VLD3LNqWB_register_Asm_16
	{ 7, OperandInfo98 },	// Inst #440 = VLD3LNqWB_register_Asm_32
	{ 5, OperandInfo99 },	// Inst #441 = VLD3dAsm_16
	{ 5, OperandInfo99 },	// Inst #442 = VLD3dAsm_32
	{ 5, OperandInfo99 },	// Inst #443 = VLD3dAsm_8
	{ 5, OperandInfo99 },	// Inst #444 = VLD3dWB_fixed_Asm_16
	{ 5, OperandInfo99 },	// Inst #445 = VLD3dWB_fixed_Asm_32
	{ 5, OperandInfo99 },	// Inst #446 = VLD3dWB_fixed_Asm_8
	{ 6, OperandInfo100 },	// Inst #447 = VLD3dWB_register_Asm_16
	{ 6, OperandInfo100 },	// Inst #448 = VLD3dWB_register_Asm_32
	{ 6, OperandInfo100 },	// Inst #449 = VLD3dWB_register_Asm_8
	{ 5, OperandInfo99 },	// Inst #450 = VLD3qAsm_16
	{ 5, OperandInfo99 },	// Inst #451 = VLD3qAsm_32
	{ 5, OperandInfo99 },	// Inst #452 = VLD3qAsm_8
	{ 5, OperandInfo99 },	// Inst #453 = VLD3qWB_fixed_Asm_16
	{ 5, OperandInfo99 },	// Inst #454 = VLD3qWB_fixed_Asm_32
	{ 5, OperandInfo99 },	// Inst #455 = VLD3qWB_fixed_Asm_8
	{ 6, OperandInfo100 },	// Inst #456 = VLD3qWB_register_Asm_16
	{ 6, OperandInfo100 },	// Inst #457 = VLD3qWB_register_Asm_32
	{ 6, OperandInfo100 },	// Inst #458 = VLD3qWB_register_Asm_8
	{ 5, OperandInfo99 },	// Inst #459 = VLD4DUPdAsm_16
	{ 5, OperandInfo99 },	// Inst #460 = VLD4DUPdAsm_32
	{ 5, OperandInfo99 },	// Inst #461 = VLD4DUPdAsm_8
	{ 5, OperandInfo99 },	// Inst #462 = VLD4DUPdWB_fixed_Asm_16
	{ 5, OperandInfo99 },	// Inst #463 = VLD4DUPdWB_fixed_Asm_32
	{ 5, OperandInfo99 },	// Inst #464 = VLD4DUPdWB_fixed_Asm_8
	{ 6, OperandInfo100 },	// Inst #465 = VLD4DUPdWB_register_Asm_16
	{ 6, OperandInfo100 },	// Inst #466 = VLD4DUPdWB_register_Asm_32
	{ 6, OperandInfo100 },	// Inst #467 = VLD4DUPdWB_register_Asm_8
	{ 5, OperandInfo99 },	// Inst #468 = VLD4DUPqAsm_16
	{ 5, OperandInfo99 },	// Inst #469 = VLD4DUPqAsm_32
	{ 5, OperandInfo99 },	// Inst #470 = VLD4DUPqAsm_8
	{ 5, OperandInfo99 },	// Inst #471 = VLD4DUPqWB_fixed_Asm_16
	{ 5, OperandInfo99 },	// Inst #472 = VLD4DUPqWB_fixed_Asm_32
	{ 5, OperandInfo99 },	// Inst #473 = VLD4DUPqWB_fixed_Asm_8
	{ 6, OperandInfo100 },	// Inst #474 = VLD4DUPqWB_register_Asm_16
	{ 6, OperandInfo100 },	// Inst #475 = VLD4DUPqWB_register_Asm_32
	{ 6, OperandInfo100 },	// Inst #476 = VLD4DUPqWB_register_Asm_8
	{ 6, OperandInfo97 },	// Inst #477 = VLD4LNdAsm_16
	{ 6, OperandInfo97 },	// Inst #478 = VLD4LNdAsm_32
	{ 6, OperandInfo97 },	// Inst #479 = VLD4LNdAsm_8
	{ 6, OperandInfo97 },	// Inst #480 = VLD4LNdWB_fixed_Asm_16
	{ 6, OperandInfo97 },	// Inst #481 = VLD4LNdWB_fixed_Asm_32
	{ 6, OperandInfo97 },	// Inst #482 = VLD4LNdWB_fixed_Asm_8
	{ 7, OperandInfo98 },	// Inst #483 = VLD4LNdWB_register_Asm_16
	{ 7, OperandInfo98 },	// Inst #484 = VLD4LNdWB_register_Asm_32
	{ 7, OperandInfo98 },	// Inst #485 = VLD4LNdWB_register_Asm_8
	{ 6, OperandInfo97 },	// Inst #486 = VLD4LNqAsm_16
	{ 6, OperandInfo97 },	// Inst #487 = VLD4LNqAsm_32
	{ 6, OperandInfo97 },	// Inst #488 = VLD4LNqWB_fixed_Asm_16
	{ 6, OperandInfo97 },	// Inst #489 = VLD4LNqWB_fixed_Asm_32
	{ 7, OperandInfo98 },	// Inst #490 = VLD4LNqWB_register_Asm_16
	{ 7, OperandInfo98 },	// Inst #491 = VLD4LNqWB_register_Asm_32
	{ 5, OperandInfo99 },	// Inst #492 = VLD4dAsm_16
	{ 5, OperandInfo99 },	// Inst #493 = VLD4dAsm_32
	{ 5, OperandInfo99 },	// Inst #494 = VLD4dAsm_8
	{ 5, OperandInfo99 },	// Inst #495 = VLD4dWB_fixed_Asm_16
	{ 5, OperandInfo99 },	// Inst #496 = VLD4dWB_fixed_Asm_32
	{ 5, OperandInfo99 },	// Inst #497 = VLD4dWB_fixed_Asm_8
	{ 6, OperandInfo100 },	// Inst #498 = VLD4dWB_register_Asm_16
	{ 6, OperandInfo100 },	// Inst #499 = VLD4dWB_register_Asm_32
	{ 6, OperandInfo100 },	// Inst #500 = VLD4dWB_register_Asm_8
	{ 5, OperandInfo99 },	// Inst #501 = VLD4qAsm_16
	{ 5, OperandInfo99 },	// Inst #502 = VLD4qAsm_32
	{ 5, OperandInfo99 },	// Inst #503 = VLD4qAsm_8
	{ 5, OperandInfo99 },	// Inst #504 = VLD4qWB_fixed_Asm_16
	{ 5, OperandInfo99 },	// Inst #505 = VLD4qWB_fixed_Asm_32
	{ 5, OperandInfo99 },	// Inst #506 = VLD4qWB_fixed_Asm_8
	{ 6, OperandInfo100 },	// Inst #507 = VLD4qWB_register_Asm_16
	{ 6, OperandInfo100 },	// Inst #508 = VLD4qWB_register_Asm_32
	{ 6, OperandInfo100 },	// Inst #509 = VLD4qWB_register_Asm_8
	{ 1, OperandInfo101 },	// Inst #510 = VMOVD0
	{ 5, OperandInfo102 },	// Inst #511 = VMOVDcc
	{ 5, OperandInfo103 },	// Inst #512 = VMOVHcc
	{ 1, OperandInfo104 },	// Inst #513 = VMOVQ0
	{ 5, OperandInfo105 },	// Inst #514 = VMOVScc
	{ 6, OperandInfo97 },	// Inst #515 = VST1LNdAsm_16
	{ 6, OperandInfo97 },	// Inst #516 = VST1LNdAsm_32
	{ 6, OperandInfo97 },	// Inst #517 = VST1LNdAsm_8
	{ 6, OperandInfo97 },	// Inst #518 = VST1LNdWB_fixed_Asm_16
	{ 6, OperandInfo97 },	// Inst #519 = VST1LNdWB_fixed_Asm_32
	{ 6, OperandInfo97 },	// Inst #520 = VST1LNdWB_fixed_Asm_8
	{ 7, OperandInfo98 },	// Inst #521 = VST1LNdWB_register_Asm_16
	{ 7, OperandInfo98 },	// Inst #522 = VST1LNdWB_register_Asm_32
	{ 7, OperandInfo98 },	// Inst #523 = VST1LNdWB_register_Asm_8
	{ 6, OperandInfo97 },	// Inst #524 = VST2LNdAsm_16
	{ 6, OperandInfo97 },	// Inst #525 = VST2LNdAsm_32
	{ 6, OperandInfo97 },	// Inst #526 = VST2LNdAsm_8
	{ 6, OperandInfo97 },	// Inst #527 = VST2LNdWB_fixed_Asm_16
	{ 6, OperandInfo97 },	// Inst #528 = VST2LNdWB_fixed_Asm_32
	{ 6, OperandInfo97 },	// Inst #529 = VST2LNdWB_fixed_Asm_8
	{ 7, OperandInfo98 },	// Inst #530 = VST2LNdWB_register_Asm_16
	{ 7, OperandInfo98 },	// Inst #531 = VST2LNdWB_register_Asm_32
	{ 7, OperandInfo98 },	// Inst #532 = VST2LNdWB_register_Asm_8
	{ 6, OperandInfo97 },	// Inst #533 = VST2LNqAsm_16
	{ 6, OperandInfo97 },	// Inst #534 = VST2LNqAsm_32
	{ 6, OperandInfo97 },	// Inst #535 = VST2LNqWB_fixed_Asm_16
	{ 6, OperandInfo97 },	// Inst #536 = VST2LNqWB_fixed_Asm_32
	{ 7, OperandInfo98 },	// Inst #537 = VST2LNqWB_register_Asm_16
	{ 7, OperandInfo98 },	// Inst #538 = VST2LNqWB_register_Asm_32
	{ 6, OperandInfo97 },	// Inst #539 = VST3LNdAsm_16
	{ 6, OperandInfo97 },	// Inst #540 = VST3LNdAsm_32
	{ 6, OperandInfo97 },	// Inst #541 = VST3LNdAsm_8
	{ 6, OperandInfo97 },	// Inst #542 = VST3LNdWB_fixed_Asm_16
	{ 6, OperandInfo97 },	// Inst #543 = VST3LNdWB_fixed_Asm_32
	{ 6, OperandInfo97 },	// Inst #544 = VST3LNdWB_fixed_Asm_8
	{ 7, OperandInfo98 },	// Inst #545 = VST3LNdWB_register_Asm_16
	{ 7, OperandInfo98 },	// Inst #546 = VST3LNdWB_register_Asm_32
	{ 7, OperandInfo98 },	// Inst #547 = VST3LNdWB_register_Asm_8
	{ 6, OperandInfo97 },	// Inst #548 = VST3LNqAsm_16
	{ 6, OperandInfo97 },	// Inst #549 = VST3LNqAsm_32
	{ 6, OperandInfo97 },	// Inst #550 = VST3LNqWB_fixed_Asm_16
	{ 6, OperandInfo97 },	// Inst #551 = VST3LNqWB_fixed_Asm_32
	{ 7, OperandInfo98 },	// Inst #552 = VST3LNqWB_register_Asm_16
	{ 7, OperandInfo98 },	// Inst #553 = VST3LNqWB_register_Asm_32
	{ 5, OperandInfo99 },	// Inst #554 = VST3dAsm_16
	{ 5, OperandInfo99 },	// Inst #555 = VST3dAsm_32
	{ 5, OperandInfo99 },	// Inst #556 = VST3dAsm_8
	{ 5, OperandInfo99 },	// Inst #557 = VST3dWB_fixed_Asm_16
	{ 5, OperandInfo99 },	// Inst #558 = VST3dWB_fixed_Asm_32
	{ 5, OperandInfo99 },	// Inst #559 = VST3dWB_fixed_Asm_8
	{ 6, OperandInfo100 },	// Inst #560 = VST3dWB_register_Asm_16
	{ 6, OperandInfo100 },	// Inst #561 = VST3dWB_register_Asm_32
	{ 6, OperandInfo100 },	// Inst #562 = VST3dWB_register_Asm_8
	{ 5, OperandInfo99 },	// Inst #563 = VST3qAsm_16
	{ 5, OperandInfo99 },	// Inst #564 = VST3qAsm_32
	{ 5, OperandInfo99 },	// Inst #565 = VST3qAsm_8
	{ 5, OperandInfo99 },	// Inst #566 = VST3qWB_fixed_Asm_16
	{ 5, OperandInfo99 },	// Inst #567 = VST3qWB_fixed_Asm_32
	{ 5, OperandInfo99 },	// Inst #568 = VST3qWB_fixed_Asm_8
	{ 6, OperandInfo100 },	// Inst #569 = VST3qWB_register_Asm_16
	{ 6, OperandInfo100 },	// Inst #570 = VST3qWB_register_Asm_32
	{ 6, OperandInfo100 },	// Inst #571 = VST3qWB_register_Asm_8
	{ 6, OperandInfo97 },	// Inst #572 = VST4LNdAsm_16
	{ 6, OperandInfo97 },	// Inst #573 = VST4LNdAsm_32
	{ 6, OperandInfo97 },	// Inst #574 = VST4LNdAsm_8
	{ 6, OperandInfo97 },	// Inst #575 = VST4LNdWB_fixed_Asm_16
	{ 6, OperandInfo97 },	// Inst #576 = VST4LNdWB_fixed_Asm_32
	{ 6, OperandInfo97 },	// Inst #577 = VST4LNdWB_fixed_Asm_8
	{ 7, OperandInfo98 },	// Inst #578 = VST4LNdWB_register_Asm_16
	{ 7, OperandInfo98 },	// Inst #579 = VST4LNdWB_register_Asm_32
	{ 7, OperandInfo98 },	// Inst #580 = VST4LNdWB_register_Asm_8
	{ 6, OperandInfo97 },	// Inst #581 = VST4LNqAsm_16
	{ 6, OperandInfo97 },	// Inst #582 = VST4LNqAsm_32
	{ 6, OperandInfo97 },	// Inst #583 = VST4LNqWB_fixed_Asm_16
	{ 6, OperandInfo97 },	// Inst #584 = VST4LNqWB_fixed_Asm_32
	{ 7, OperandInfo98 },	// Inst #585 = VST4LNqWB_register_Asm_16
	{ 7, OperandInfo98 },	// Inst #586 = VST4LNqWB_register_Asm_32
	{ 5, OperandInfo99 },	// Inst #587 = VST4dAsm_16
	{ 5, OperandInfo99 },	// Inst #588 = VST4dAsm_32
	{ 5, OperandInfo99 },	// Inst #589 = VST4dAsm_8
	{ 5, OperandInfo99 },	// Inst #590 = VST4dWB_fixed_Asm_16
	{ 5, OperandInfo99 },	// Inst #591 = VST4dWB_fixed_Asm_32
	{ 5, OperandInfo99 },	// Inst #592 = VST4dWB_fixed_Asm_8
	{ 6, OperandInfo100 },	// Inst #593 = VST4dWB_register_Asm_16
	{ 6, OperandInfo100 },	// Inst #594 = VST4dWB_register_Asm_32
	{ 6, OperandInfo100 },	// Inst #595 = VST4dWB_register_Asm_8
	{ 5, OperandInfo99 },	// Inst #596 = VST4qAsm_16
	{ 5, OperandInfo99 },	// Inst #597 = VST4qAsm_32
	{ 5, OperandInfo99 },	// Inst #598 = VST4qAsm_8
	{ 5, OperandInfo99 },	// Inst #599 = VST4qWB_fixed_Asm_16
	{ 5, OperandInfo99 },	// Inst #600 = VST4qWB_fixed_Asm_32
	{ 5, OperandInfo99 },	// Inst #601 = VST4qWB_fixed_Asm_8
	{ 6, OperandInfo100 },	// Inst #602 = VST4qWB_register_Asm_16
	{ 6, OperandInfo100 },	// Inst #603 = VST4qWB_register_Asm_32
	{ 6, OperandInfo100 },	// Inst #604 = VST4qWB_register_Asm_8
	{ 0, 0 },		// Inst #605 = WIN__CHKSTK
	{ 1, OperandInfo58 },	// Inst #606 = WIN__DBZCHK
	{ 2, OperandInfo106 },	// Inst #607 = t2ABS
	{ 5, OperandInfo107 },	// Inst #608 = t2ADDSri
	{ 5, OperandInfo108 },	// Inst #609 = t2ADDSrr
	{ 6, OperandInfo109 },	// Inst #610 = t2ADDSrs
	{ 1, OperandInfo2 },	// Inst #611 = t2BF_LabelPseudo
	{ 3, OperandInfo59 },	// Inst #612 = t2BR_JT
	{ 3, OperandInfo110 },	// Inst #613 = t2CALL_BTI
	{ 2, OperandInfo111 },	// Inst #614 = t2DoLoopStart
	{ 3, OperandInfo112 },	// Inst #615 = t2DoLoopStartTP
	{ 5, OperandInfo66 },	// Inst #616 = t2LDMIA_RET
	{ 4, OperandInfo113 },	// Inst #617 = t2LDRBpcrel
	{ 4, OperandInfo68 },	// Inst #618 = t2LDRConstPool
	{ 4, OperandInfo113 },	// Inst #619 = t2LDRHpcrel
	{ 2, OperandInfo114 },	// Inst #620 = t2LDRLIT_ga_pcrel
	{ 4, OperandInfo113 },	// Inst #621 = t2LDRSBpcrel
	{ 4, OperandInfo113 },	// Inst #622 = t2LDRSHpcrel
	{ 5, OperandInfo87 },	// Inst #623 = t2LDR_POST_imm
	{ 5, OperandInfo87 },	// Inst #624 = t2LDR_PRE_imm
	{ 3, OperandInfo115 },	// Inst #625 = t2LDRpci_pic
	{ 4, OperandInfo68 },	// Inst #626 = t2LDRpcrel
	{ 4, OperandInfo116 },	// Inst #627 = t2LEApcrel
	{ 4, OperandInfo116 },	// Inst #628 = t2LEApcrelJT
	{ 3, OperandInfo117 },	// Inst #629 = t2LoopDec
	{ 2, OperandInfo57 },	// Inst #630 = t2LoopEnd
	{ 3, OperandInfo118 },	// Inst #631 = t2LoopEndDec
	{ 6, OperandInfo119 },	// Inst #632 = t2MOVCCasr
	{ 5, OperandInfo120 },	// Inst #633 = t2MOVCCi
	{ 5, OperandInfo120 },	// Inst #634 = t2MOVCCi16
	{ 5, OperandInfo121 },	// Inst #635 = t2MOVCCi32imm
	{ 6, OperandInfo119 },	// Inst #636 = t2MOVCClsl
	{ 6, OperandInfo119 },	// Inst #637 = t2MOVCClsr
	{ 5, OperandInfo122 },	// Inst #638 = t2MOVCCr
	{ 6, OperandInfo119 },	// Inst #639 = t2MOVCCror
	{ 5, OperandInfo123 },	// Inst #640 = t2MOVSsi
	{ 6, OperandInfo124 },	// Inst #641 = t2MOVSsr
	{ 4, OperandInfo125 },	// Inst #642 = t2MOVTi16_ga_pcrel
	{ 2, OperandInfo114 },	// Inst #643 = t2MOV_ga_pcrel
	{ 3, OperandInfo115 },	// Inst #644 = t2MOVi16_ga_pcrel
	{ 2, OperandInfo114 },	// Inst #645 = t2MOVi32imm
	{ 5, OperandInfo123 },	// Inst #646 = t2MOVsi
	{ 6, OperandInfo124 },	// Inst #647 = t2MOVsr
	{ 5, OperandInfo120 },	// Inst #648 = t2MVNCCi
	{ 5, OperandInfo126 },	// Inst #649 = t2RSBSri
	{ 6, OperandInfo127 },	// Inst #650 = t2RSBSrs
	{ 6, OperandInfo128 },	// Inst #651 = t2STRB_preidx
	{ 6, OperandInfo128 },	// Inst #652 = t2STRH_preidx
	{ 5, OperandInfo87 },	// Inst #653 = t2STR_POST_imm
	{ 5, OperandInfo87 },	// Inst #654 = t2STR_PRE_imm
	{ 6, OperandInfo128 },	// Inst #655 = t2STR_preidx
	{ 5, OperandInfo107 },	// Inst #656 = t2SUBSri
	{ 5, OperandInfo108 },	// Inst #657 = t2SUBSrr
	{ 6, OperandInfo109 },	// Inst #658 = t2SUBSrs
	{ 0, 0 },		// Inst #659 = t2SpeculationBarrierISBDSBEndBB
	{ 0, 0 },		// Inst #660 = t2SpeculationBarrierSBEndBB
	{ 4, OperandInfo65 },	// Inst #661 = t2TBB_JT
	{ 4, OperandInfo65 },	// Inst #662 = t2TBH_JT
	{ 2, OperandInfo111 },	// Inst #663 = t2WhileLoopSetup
	{ 2, OperandInfo57 },	// Inst #664 = t2WhileLoopStart
	{ 3, OperandInfo129 },	// Inst #665 = t2WhileLoopStartLR
	{ 4, OperandInfo130 },	// Inst #666 = t2WhileLoopStartTP
	{ 3, OperandInfo131 },	// Inst #667 = tADCS
	{ 3, OperandInfo132 },	// Inst #668 = tADDSi3
	{ 3, OperandInfo132 },	// Inst #669 = tADDSi8
	{ 3, OperandInfo131 },	// Inst #670 = tADDSrr
	{ 3, OperandInfo133 },	// Inst #671 = tADDframe
	{ 2, OperandInfo10 },	// Inst #672 = tADJCALLSTACKDOWN
	{ 2, OperandInfo10 },	// Inst #673 = tADJCALLSTACKUP
	{ 1, OperandInfo134 },	// Inst #674 = tBLXNS_CALL
	{ 3, OperandInfo135 },	// Inst #675 = tBLXr_noip
	{ 4, OperandInfo136 },	// Inst #676 = tBL_PUSHLR
	{ 3, OperandInfo137 },	// Inst #677 = tBRIND
	{ 2, OperandInfo138 },	// Inst #678 = tBR_JTr
	{ 0, 0 },		// Inst #679 = tBXNS_RET
	{ 1, OperandInfo58 },	// Inst #680 = tBX_CALL
	{ 2, OperandInfo139 },	// Inst #681 = tBX_RET
	{ 3, OperandInfo140 },	// Inst #682 = tBX_RET_vararg
	{ 3, OperandInfo141 },	// Inst #683 = tBfar
	{ 5, OperandInfo142 },	// Inst #684 = tCMP_SWAP_16
	{ 5, OperandInfo143 },	// Inst #685 = tCMP_SWAP_32
	{ 5, OperandInfo142 },	// Inst #686 = tCMP_SWAP_8
	{ 5, OperandInfo144 },	// Inst #687 = tLDMIA_UPD
	{ 4, OperandInfo145 },	// Inst #688 = tLDRConstPool
	{ 2, OperandInfo138 },	// Inst #689 = tLDRLIT_ga_abs
	{ 2, OperandInfo138 },	// Inst #690 = tLDRLIT_ga_pcrel
	{ 5, OperandInfo146 },	// Inst #691 = tLDR_postidx
	{ 3, OperandInfo147 },	// Inst #692 = tLDRpci_pic
	{ 4, OperandInfo148 },	// Inst #693 = tLEApcrel
	{ 4, OperandInfo148 },	// Inst #694 = tLEApcrelJT
	{ 3, OperandInfo132 },	// Inst #695 = tLSLSri
	{ 5, OperandInfo149 },	// Inst #696 = tMOVCCr_pseudo
	{ 3, OperandInfo150 },	// Inst #697 = tPOP_RET
	{ 2, OperandInfo151 },	// Inst #698 = tRSBS
	{ 3, OperandInfo131 },	// Inst #699 = tSBCS
	{ 3, OperandInfo132 },	// Inst #700 = tSUBSi3
	{ 3, OperandInfo132 },	// Inst #701 = tSUBSi8
	{ 3, OperandInfo131 },	// Inst #702 = tSUBSrr
	{ 3, OperandInfo141 },	// Inst #703 = tTAILJMPd
	{ 3, OperandInfo141 },	// Inst #704 = tTAILJMPdND
	{ 1, OperandInfo95 },	// Inst #705 = tTAILJMPr
	{ 4, OperandInfo152 },	// Inst #706 = tTBB_JT
	{ 4, OperandInfo152 },	// Inst #707 = tTBH_JT
	{ 0, 0 },		// Inst #708 = tTPsoft
	{ 6, OperandInfo51 },	// Inst #709 = ADCri
	{ 6, OperandInfo153 },	// Inst #710 = ADCrr
	{ 7, OperandInfo154 },	// Inst #711 = ADCrsi
	{ 8, OperandInfo155 },	// Inst #712 = ADCrsr
	{ 6, OperandInfo51 },	// Inst #713 = ADDri
	{ 6, OperandInfo153 },	// Inst #714 = ADDrr
	{ 7, OperandInfo154 },	// Inst #715 = ADDrsi
	{ 8, OperandInfo156 },	// Inst #716 = ADDrsr
	{ 4, OperandInfo68 },	// Inst #717 = ADR
	{ 3, OperandInfo157 },	// Inst #718 = AESD
	{ 3, OperandInfo157 },	// Inst #719 = AESE
	{ 2, OperandInfo158 },	// Inst #720 = AESIMC
	{ 2, OperandInfo158 },	// Inst #721 = AESMC
	{ 6, OperandInfo51 },	// Inst #722 = ANDri
	{ 6, OperandInfo153 },	// Inst #723 = ANDrr
	{ 7, OperandInfo154 },	// Inst #724 = ANDrsi
	{ 8, OperandInfo156 },	// Inst #725 = ANDrsr
	{ 5, OperandInfo159 },	// Inst #726 = BF16VDOTI_VDOTD
	{ 5, OperandInfo160 },	// Inst #727 = BF16VDOTI_VDOTQ
	{ 4, OperandInfo161 },	// Inst #728 = BF16VDOTS_VDOTD
	{ 4, OperandInfo162 },	// Inst #729 = BF16VDOTS_VDOTQ
	{ 4, OperandInfo163 },	// Inst #730 = BF16_VCVT
	{ 5, OperandInfo105 },	// Inst #731 = BF16_VCVTB
	{ 5, OperandInfo105 },	// Inst #732 = BF16_VCVTT
	{ 5, OperandInfo73 },	// Inst #733 = BFC
	{ 6, OperandInfo164 },	// Inst #734 = BFI
	{ 6, OperandInfo51 },	// Inst #735 = BICri
	{ 6, OperandInfo153 },	// Inst #736 = BICrr
	{ 7, OperandInfo154 },	// Inst #737 = BICrsi
	{ 8, OperandInfo156 },	// Inst #738 = BICrsr
	{ 1, OperandInfo2 },	// Inst #739 = BKPT
	{ 1, OperandInfo53 },	// Inst #740 = BL
	{ 1, OperandInfo78 },	// Inst #741 = BLX
	{ 3, OperandInfo137 },	// Inst #742 = BLX_pred
	{ 1, OperandInfo53 },	// Inst #743 = BLXi
	{ 3, OperandInfo141 },	// Inst #744 = BL_pred
	{ 1, OperandInfo78 },	// Inst #745 = BX
	{ 3, OperandInfo137 },	// Inst #746 = BXJ
	{ 2, OperandInfo139 },	// Inst #747 = BX_RET
	{ 3, OperandInfo137 },	// Inst #748 = BX_pred
	{ 3, OperandInfo141 },	// Inst #749 = Bcc
	{ 3, OperandInfo165 },	// Inst #750 = CDE_CX1
	{ 6, OperandInfo166 },	// Inst #751 = CDE_CX1A
	{ 3, OperandInfo167 },	// Inst #752 = CDE_CX1D
	{ 6, OperandInfo168 },	// Inst #753 = CDE_CX1DA
	{ 4, OperandInfo169 },	// Inst #754 = CDE_CX2
	{ 7, OperandInfo170 },	// Inst #755 = CDE_CX2A
	{ 4, OperandInfo171 },	// Inst #756 = CDE_CX2D
	{ 7, OperandInfo172 },	// Inst #757 = CDE_CX2DA
	{ 5, OperandInfo173 },	// Inst #758 = CDE_CX3
	{ 8, OperandInfo174 },	// Inst #759 = CDE_CX3A
	{ 5, OperandInfo175 },	// Inst #760 = CDE_CX3D
	{ 8, OperandInfo176 },	// Inst #761 = CDE_CX3DA
	{ 4, OperandInfo177 },	// Inst #762 = CDE_VCX1A_fpdp
	{ 4, OperandInfo178 },	// Inst #763 = CDE_VCX1A_fpsp
	{ 7, OperandInfo179 },	// Inst #764 = CDE_VCX1A_vec
	{ 3, OperandInfo180 },	// Inst #765 = CDE_VCX1_fpdp
	{ 3, OperandInfo181 },	// Inst #766 = CDE_VCX1_fpsp
	{ 7, OperandInfo182 },	// Inst #767 = CDE_VCX1_vec
	{ 5, OperandInfo183 },	// Inst #768 = CDE_VCX2A_fpdp
	{ 5, OperandInfo184 },	// Inst #769 = CDE_VCX2A_fpsp
	{ 8, OperandInfo185 },	// Inst #770 = CDE_VCX2A_vec
	{ 4, OperandInfo186 },	// Inst #771 = CDE_VCX2_fpdp
	{ 4, OperandInfo187 },	// Inst #772 = CDE_VCX2_fpsp
	{ 8, OperandInfo188 },	// Inst #773 = CDE_VCX2_vec
	{ 6, OperandInfo189 },	// Inst #774 = CDE_VCX3A_fpdp
	{ 6, OperandInfo190 },	// Inst #775 = CDE_VCX3A_fpsp
	{ 9, OperandInfo191 },	// Inst #776 = CDE_VCX3A_vec
	{ 5, OperandInfo192 },	// Inst #777 = CDE_VCX3_fpdp
	{ 5, OperandInfo193 },	// Inst #778 = CDE_VCX3_fpsp
	{ 9, OperandInfo194 },	// Inst #779 = CDE_VCX3_vec
	{ 8, OperandInfo195 },	// Inst #780 = CDP
	{ 6, OperandInfo196 },	// Inst #781 = CDP2
	{ 0, 0 },		// Inst #782 = CLREX
	{ 4, OperandInfo197 },	// Inst #783 = CLZ
	{ 4, OperandInfo68 },	// Inst #784 = CMNri
	{ 4, OperandInfo197 },	// Inst #785 = CMNzrr
	{ 5, OperandInfo198 },	// Inst #786 = CMNzrsi
	{ 6, OperandInfo199 },	// Inst #787 = CMNzrsr
	{ 4, OperandInfo68 },	// Inst #788 = CMPri
	{ 4, OperandInfo197 },	// Inst #789 = CMPrr
	{ 5, OperandInfo198 },	// Inst #790 = CMPrsi
	{ 6, OperandInfo199 },	// Inst #791 = CMPrsr
	{ 1, OperandInfo2 },	// Inst #792 = CPS1p
	{ 2, OperandInfo7 },	// Inst #793 = CPS2p
	{ 3, OperandInfo200 },	// Inst #794 = CPS3p
	{ 3, OperandInfo201 },	// Inst #795 = CRC32B
	{ 3, OperandInfo201 },	// Inst #796 = CRC32CB
	{ 3, OperandInfo201 },	// Inst #797 = CRC32CH
	{ 3, OperandInfo201 },	// Inst #798 = CRC32CW
	{ 3, OperandInfo201 },	// Inst #799 = CRC32H
	{ 3, OperandInfo201 },	// Inst #800 = CRC32W
	{ 3, OperandInfo202 },	// Inst #801 = DBG
	{ 1, OperandInfo2 },	// Inst #802 = DMB
	{ 1, OperandInfo2 },	// Inst #803 = DSB
	{ 6, OperandInfo51 },	// Inst #804 = EORri
	{ 6, OperandInfo153 },	// Inst #805 = EORrr
	{ 7, OperandInfo154 },	// Inst #806 = EORrsi
	{ 8, OperandInfo156 },	// Inst #807 = EORrsr
	{ 2, OperandInfo139 },	// Inst #808 = ERET
	{ 4, OperandInfo203 },	// Inst #809 = FCONSTD
	{ 4, OperandInfo204 },	// Inst #810 = FCONSTH
	{ 4, OperandInfo205 },	// Inst #811 = FCONSTS
	{ 5, OperandInfo66 },	// Inst #812 = FLDMXDB_UPD
	{ 4, OperandInfo206 },	// Inst #813 = FLDMXIA
	{ 5, OperandInfo66 },	// Inst #814 = FLDMXIA_UPD
	{ 2, OperandInfo139 },	// Inst #815 = FMSTAT
	{ 5, OperandInfo66 },	// Inst #816 = FSTMXDB_UPD
	{ 4, OperandInfo206 },	// Inst #817 = FSTMXIA
	{ 5, OperandInfo66 },	// Inst #818 = FSTMXIA_UPD
	{ 3, OperandInfo202 },	// Inst #819 = HINT
	{ 1, OperandInfo2 },	// Inst #820 = HLT
	{ 1, OperandInfo2 },	// Inst #821 = HVC
	{ 1, OperandInfo2 },	// Inst #822 = ISB
	{ 4, OperandInfo67 },	// Inst #823 = LDA
	{ 4, OperandInfo67 },	// Inst #824 = LDAB
	{ 4, OperandInfo67 },	// Inst #825 = LDAEX
	{ 4, OperandInfo67 },	// Inst #826 = LDAEXB
	{ 4, OperandInfo207 },	// Inst #827 = LDAEXD
	{ 4, OperandInfo67 },	// Inst #828 = LDAEXH
	{ 4, OperandInfo67 },	// Inst #829 = LDAH
	{ 4, OperandInfo208 },	// Inst #830 = LDC2L_OFFSET
	{ 4, OperandInfo209 },	// Inst #831 = LDC2L_OPTION
	{ 4, OperandInfo208 },	// Inst #832 = LDC2L_POST
	{ 5, OperandInfo210 },	// Inst #833 = LDC2L_PRE
	{ 4, OperandInfo208 },	// Inst #834 = LDC2_OFFSET
	{ 4, OperandInfo209 },	// Inst #835 = LDC2_OPTION
	{ 4, OperandInfo208 },	// Inst #836 = LDC2_POST
	{ 5, OperandInfo210 },	// Inst #837 = LDC2_PRE
	{ 6, OperandInfo211 },	// Inst #838 = LDCL_OFFSET
	{ 6, OperandInfo212 },	// Inst #839 = LDCL_OPTION
	{ 6, OperandInfo211 },	// Inst #840 = LDCL_POST
	{ 7, OperandInfo213 },	// Inst #841 = LDCL_PRE
	{ 6, OperandInfo211 },	// Inst #842 = LDC_OFFSET
	{ 6, OperandInfo212 },	// Inst #843 = LDC_OPTION
	{ 6, OperandInfo211 },	// Inst #844 = LDC_POST
	{ 7, OperandInfo213 },	// Inst #845 = LDC_PRE
	{ 4, OperandInfo206 },	// Inst #846 = LDMDA
	{ 5, OperandInfo66 },	// Inst #847 = LDMDA_UPD
	{ 4, OperandInfo206 },	// Inst #848 = LDMDB
	{ 5, OperandInfo66 },	// Inst #849 = LDMDB_UPD
	{ 4, OperandInfo206 },	// Inst #850 = LDMIA
	{ 5, OperandInfo66 },	// Inst #851 = LDMIA_UPD
	{ 4, OperandInfo206 },	// Inst #852 = LDMIB
	{ 5, OperandInfo66 },	// Inst #853 = LDMIB_UPD
	{ 7, OperandInfo214 },	// Inst #854 = LDRBT_POST_IMM
	{ 7, OperandInfo214 },	// Inst #855 = LDRBT_POST_REG
	{ 7, OperandInfo214 },	// Inst #856 = LDRB_POST_IMM
	{ 7, OperandInfo214 },	// Inst #857 = LDRB_POST_REG
	{ 6, OperandInfo215 },	// Inst #858 = LDRB_PRE_IMM
	{ 7, OperandInfo214 },	// Inst #859 = LDRB_PRE_REG
	{ 5, OperandInfo216 },	// Inst #860 = LDRBi12
	{ 6, OperandInfo217 },	// Inst #861 = LDRBrs
	{ 7, OperandInfo218 },	// Inst #862 = LDRD
	{ 8, OperandInfo219 },	// Inst #863 = LDRD_POST
	{ 8, OperandInfo219 },	// Inst #864 = LDRD_PRE
	{ 4, OperandInfo67 },	// Inst #865 = LDREX
	{ 4, OperandInfo67 },	// Inst #866 = LDREXB
	{ 4, OperandInfo207 },	// Inst #867 = LDREXD
	{ 4, OperandInfo67 },	// Inst #868 = LDREXH
	{ 6, OperandInfo220 },	// Inst #869 = LDRH
	{ 6, OperandInfo215 },	// Inst #870 = LDRHTi
	{ 7, OperandInfo221 },	// Inst #871 = LDRHTr
	{ 7, OperandInfo222 },	// Inst #872 = LDRH_POST
	{ 7, OperandInfo222 },	// Inst #873 = LDRH_PRE
	{ 6, OperandInfo220 },	// Inst #874 = LDRSB
	{ 6, OperandInfo215 },	// Inst #875 = LDRSBTi
	{ 7, OperandInfo221 },	// Inst #876 = LDRSBTr
	{ 7, OperandInfo222 },	// Inst #877 = LDRSB_POST
	{ 7, OperandInfo222 },	// Inst #878 = LDRSB_PRE
	{ 6, OperandInfo220 },	// Inst #879 = LDRSH
	{ 6, OperandInfo215 },	// Inst #880 = LDRSHTi
	{ 7, OperandInfo221 },	// Inst #881 = LDRSHTr
	{ 7, OperandInfo222 },	// Inst #882 = LDRSH_POST
	{ 7, OperandInfo222 },	// Inst #883 = LDRSH_PRE
	{ 7, OperandInfo214 },	// Inst #884 = LDRT_POST_IMM
	{ 7, OperandInfo214 },	// Inst #885 = LDRT_POST_REG
	{ 7, OperandInfo214 },	// Inst #886 = LDR_POST_IMM
	{ 7, OperandInfo214 },	// Inst #887 = LDR_POST_REG
	{ 6, OperandInfo215 },	// Inst #888 = LDR_PRE_IMM
	{ 7, OperandInfo214 },	// Inst #889 = LDR_PRE_REG
	{ 5, OperandInfo87 },	// Inst #890 = LDRcp
	{ 5, OperandInfo87 },	// Inst #891 = LDRi12
	{ 6, OperandInfo223 },	// Inst #892 = LDRrs
	{ 8, OperandInfo224 },	// Inst #893 = MCR
	{ 6, OperandInfo225 },	// Inst #894 = MCR2
	{ 7, OperandInfo226 },	// Inst #895 = MCRR
	{ 5, OperandInfo227 },	// Inst #896 = MCRR2
	{ 7, OperandInfo228 },	// Inst #897 = MLA
	{ 6, OperandInfo229 },	// Inst #898 = MLS
	{ 2, OperandInfo139 },	// Inst #899 = MOVPCLR
	{ 5, OperandInfo230 },	// Inst #900 = MOVTi16
	{ 5, OperandInfo231 },	// Inst #901 = MOVi
	{ 4, OperandInfo68 },	// Inst #902 = MOVi16
	{ 5, OperandInfo88 },	// Inst #903 = MOVr
	{ 5, OperandInfo232 },	// Inst #904 = MOVr_TC
	{ 6, OperandInfo233 },	// Inst #905 = MOVsi
	{ 7, OperandInfo234 },	// Inst #906 = MOVsr
	{ 8, OperandInfo235 },	// Inst #907 = MRC
	{ 6, OperandInfo236 },	// Inst #908 = MRC2
	{ 7, OperandInfo237 },	// Inst #909 = MRRC
	{ 5, OperandInfo238 },	// Inst #910 = MRRC2
	{ 3, OperandInfo239 },	// Inst #911 = MRS
	{ 4, OperandInfo113 },	// Inst #912 = MRSbanked
	{ 3, OperandInfo239 },	// Inst #913 = MRSsys
	{ 4, OperandInfo240 },	// Inst #914 = MSR
	{ 4, OperandInfo241 },	// Inst #915 = MSRbanked
	{ 4, OperandInfo242 },	// Inst #916 = MSRi
	{ 6, OperandInfo52 },	// Inst #917 = MUL
	{ 7, OperandInfo243 },	// Inst #918 = MVE_ASRLi
	{ 7, OperandInfo244 },	// Inst #919 = MVE_ASRLr
	{ 2, OperandInfo111 },	// Inst #920 = MVE_DLSTP_16
	{ 2, OperandInfo111 },	// Inst #921 = MVE_DLSTP_32
	{ 2, OperandInfo111 },	// Inst #922 = MVE_DLSTP_64
	{ 2, OperandInfo111 },	// Inst #923 = MVE_DLSTP_8
	{ 2, OperandInfo139 },	// Inst #924 = MVE_LCTP
	{ 3, OperandInfo118 },	// Inst #925 = MVE_LETP
	{ 7, OperandInfo243 },	// Inst #926 = MVE_LSLLi
	{ 7, OperandInfo244 },	// Inst #927 = MVE_LSLLr
	{ 7, OperandInfo243 },	// Inst #928 = MVE_LSRL
	{ 5, OperandInfo122 },	// Inst #929 = MVE_SQRSHR
	{ 8, OperandInfo245 },	// Inst #930 = MVE_SQRSHRL
	{ 5, OperandInfo120 },	// Inst #931 = MVE_SQSHL
	{ 7, OperandInfo243 },	// Inst #932 = MVE_SQSHLL
	{ 5, OperandInfo120 },	// Inst #933 = MVE_SRSHR
	{ 7, OperandInfo243 },	// Inst #934 = MVE_SRSHRL
	{ 5, OperandInfo122 },	// Inst #935 = MVE_UQRSHL
	{ 8, OperandInfo245 },	// Inst #936 = MVE_UQRSHLL
	{ 5, OperandInfo120 },	// Inst #937 = MVE_UQSHL
	{ 7, OperandInfo243 },	// Inst #938 = MVE_UQSHLL
	{ 5, OperandInfo120 },	// Inst #939 = MVE_URSHR
	{ 7, OperandInfo243 },	// Inst #940 = MVE_URSHRL
	{ 7, OperandInfo246 },	// Inst #941 = MVE_VABAVs16
	{ 7, OperandInfo246 },	// Inst #942 = MVE_VABAVs32
	{ 7, OperandInfo246 },	// Inst #943 = MVE_VABAVs8
	{ 7, OperandInfo246 },	// Inst #944 = MVE_VABAVu16
	{ 7, OperandInfo246 },	// Inst #945 = MVE_VABAVu32
	{ 7, OperandInfo246 },	// Inst #946 = MVE_VABAVu8
	{ 7, OperandInfo247 },	// Inst #947 = MVE_VABDf16
	{ 7, OperandInfo247 },	// Inst #948 = MVE_VABDf32
	{ 7, OperandInfo247 },	// Inst #949 = MVE_VABDs16
	{ 7, OperandInfo247 },	// Inst #950 = MVE_VABDs32
	{ 7, OperandInfo247 },	// Inst #951 = MVE_VABDs8
	{ 7, OperandInfo247 },	// Inst #952 = MVE_VABDu16
	{ 7, OperandInfo247 },	// Inst #953 = MVE_VABDu32
	{ 7, OperandInfo247 },	// Inst #954 = MVE_VABDu8
	{ 6, OperandInfo248 },	// Inst #955 = MVE_VABSf16
	{ 6, OperandInfo248 },	// Inst #956 = MVE_VABSf32
	{ 6, OperandInfo248 },	// Inst #957 = MVE_VABSs16
	{ 6, OperandInfo248 },	// Inst #958 = MVE_VABSs32
	{ 6, OperandInfo248 },	// Inst #959 = MVE_VABSs8
	{ 9, OperandInfo249 },	// Inst #960 = MVE_VADC
	{ 8, OperandInfo250 },	// Inst #961 = MVE_VADCI
	{ 8, OperandInfo251 },	// Inst #962 = MVE_VADDLVs32acc
	{ 6, OperandInfo252 },	// Inst #963 = MVE_VADDLVs32no_acc
	{ 8, OperandInfo251 },	// Inst #964 = MVE_VADDLVu32acc
	{ 6, OperandInfo252 },	// Inst #965 = MVE_VADDLVu32no_acc
	{ 6, OperandInfo253 },	// Inst #966 = MVE_VADDVs16acc
	{ 5, OperandInfo254 },	// Inst #967 = MVE_VADDVs16no_acc
	{ 6, OperandInfo253 },	// Inst #968 = MVE_VADDVs32acc
	{ 5, OperandInfo254 },	// Inst #969 = MVE_VADDVs32no_acc
	{ 6, OperandInfo253 },	// Inst #970 = MVE_VADDVs8acc
	{ 5, OperandInfo254 },	// Inst #971 = MVE_VADDVs8no_acc
	{ 6, OperandInfo253 },	// Inst #972 = MVE_VADDVu16acc
	{ 5, OperandInfo254 },	// Inst #973 = MVE_VADDVu16no_acc
	{ 6, OperandInfo253 },	// Inst #974 = MVE_VADDVu32acc
	{ 5, OperandInfo254 },	// Inst #975 = MVE_VADDVu32no_acc
	{ 6, OperandInfo253 },	// Inst #976 = MVE_VADDVu8acc
	{ 5, OperandInfo254 },	// Inst #977 = MVE_VADDVu8no_acc
	{ 7, OperandInfo255 },	// Inst #978 = MVE_VADD_qr_f16
	{ 7, OperandInfo255 },	// Inst #979 = MVE_VADD_qr_f32
	{ 7, OperandInfo255 },	// Inst #980 = MVE_VADD_qr_i16
	{ 7, OperandInfo255 },	// Inst #981 = MVE_VADD_qr_i32
	{ 7, OperandInfo255 },	// Inst #982 = MVE_VADD_qr_i8
	{ 7, OperandInfo247 },	// Inst #983 = MVE_VADDf16
	{ 7, OperandInfo247 },	// Inst #984 = MVE_VADDf32
	{ 7, OperandInfo247 },	// Inst #985 = MVE_VADDi16
	{ 7, OperandInfo247 },	// Inst #986 = MVE_VADDi32
	{ 7, OperandInfo247 },	// Inst #987 = MVE_VADDi8
	{ 7, OperandInfo247 },	// Inst #988 = MVE_VAND
	{ 7, OperandInfo247 },	// Inst #989 = MVE_VBIC
	{ 6, OperandInfo256 },	// Inst #990 = MVE_VBICimmi16
	{ 6, OperandInfo256 },	// Inst #991 = MVE_VBICimmi32
	{ 7, OperandInfo255 },	// Inst #992 = MVE_VBRSR16
	{ 7, OperandInfo255 },	// Inst #993 = MVE_VBRSR32
	{ 7, OperandInfo255 },	// Inst #994 = MVE_VBRSR8
	{ 8, OperandInfo257 },	// Inst #995 = MVE_VCADDf16
	{ 8, OperandInfo258 },	// Inst #996 = MVE_VCADDf32
	{ 8, OperandInfo257 },	// Inst #997 = MVE_VCADDi16
	{ 8, OperandInfo258 },	// Inst #998 = MVE_VCADDi32
	{ 8, OperandInfo257 },	// Inst #999 = MVE_VCADDi8
	{ 6, OperandInfo248 },	// Inst #1000 = MVE_VCLSs16
	{ 6, OperandInfo248 },	// Inst #1001 = MVE_VCLSs32
	{ 6, OperandInfo248 },	// Inst #1002 = MVE_VCLSs8
	{ 6, OperandInfo248 },	// Inst #1003 = MVE_VCLZs16
	{ 6, OperandInfo248 },	// Inst #1004 = MVE_VCLZs32
	{ 6, OperandInfo248 },	// Inst #1005 = MVE_VCLZs8
	{ 8, OperandInfo259 },	// Inst #1006 = MVE_VCMLAf16
	{ 8, OperandInfo259 },	// Inst #1007 = MVE_VCMLAf32
	{ 7, OperandInfo260 },	// Inst #1008 = MVE_VCMPf16
	{ 7, OperandInfo261 },	// Inst #1009 = MVE_VCMPf16r
	{ 7, OperandInfo260 },	// Inst #1010 = MVE_VCMPf32
	{ 7, OperandInfo261 },	// Inst #1011 = MVE_VCMPf32r
	{ 7, OperandInfo260 },	// Inst #1012 = MVE_VCMPi16
	{ 7, OperandInfo261 },	// Inst #1013 = MVE_VCMPi16r
	{ 7, OperandInfo260 },	// Inst #1014 = MVE_VCMPi32
	{ 7, OperandInfo261 },	// Inst #1015 = MVE_VCMPi32r
	{ 7, OperandInfo260 },	// Inst #1016 = MVE_VCMPi8
	{ 7, OperandInfo261 },	// Inst #1017 = MVE_VCMPi8r
	{ 7, OperandInfo260 },	// Inst #1018 = MVE_VCMPs16
	{ 7, OperandInfo261 },	// Inst #1019 = MVE_VCMPs16r
	{ 7, OperandInfo260 },	// Inst #1020 = MVE_VCMPs32
	{ 7, OperandInfo261 },	// Inst #1021 = MVE_VCMPs32r
	{ 7, OperandInfo260 },	// Inst #1022 = MVE_VCMPs8
	{ 7, OperandInfo261 },	// Inst #1023 = MVE_VCMPs8r
	{ 7, OperandInfo260 },	// Inst #1024 = MVE_VCMPu16
	{ 7, OperandInfo261 },	// Inst #1025 = MVE_VCMPu16r
	{ 7, OperandInfo260 },	// Inst #1026 = MVE_VCMPu32
	{ 7, OperandInfo261 },	// Inst #1027 = MVE_VCMPu32r
	{ 7, OperandInfo260 },	// Inst #1028 = MVE_VCMPu8
	{ 7, OperandInfo261 },	// Inst #1029 = MVE_VCMPu8r
	{ 8, OperandInfo257 },	// Inst #1030 = MVE_VCMULf16
	{ 8, OperandInfo258 },	// Inst #1031 = MVE_VCMULf32
	{ 5, OperandInfo262 },	// Inst #1032 = MVE_VCTP16
	{ 5, OperandInfo262 },	// Inst #1033 = MVE_VCTP32
	{ 5, OperandInfo262 },	// Inst #1034 = MVE_VCTP64
	{ 5, OperandInfo262 },	// Inst #1035 = MVE_VCTP8
	{ 6, OperandInfo263 },	// Inst #1036 = MVE_VCVTf16f32bh
	{ 6, OperandInfo263 },	// Inst #1037 = MVE_VCVTf16f32th
	{ 7, OperandInfo264 },	// Inst #1038 = MVE_VCVTf16s16_fix
	{ 6, OperandInfo248 },	// Inst #1039 = MVE_VCVTf16s16n
	{ 7, OperandInfo264 },	// Inst #1040 = MVE_VCVTf16u16_fix
	{ 6, OperandInfo248 },	// Inst #1041 = MVE_VCVTf16u16n
	{ 6, OperandInfo248 },	// Inst #1042 = MVE_VCVTf32f16bh
	{ 6, OperandInfo248 },	// Inst #1043 = MVE_VCVTf32f16th
	{ 7, OperandInfo264 },	// Inst #1044 = MVE_VCVTf32s32_fix
	{ 6, OperandInfo248 },	// Inst #1045 = MVE_VCVTf32s32n
	{ 7, OperandInfo264 },	// Inst #1046 = MVE_VCVTf32u32_fix
	{ 6, OperandInfo248 },	// Inst #1047 = MVE_VCVTf32u32n
	{ 7, OperandInfo264 },	// Inst #1048 = MVE_VCVTs16f16_fix
	{ 6, OperandInfo248 },	// Inst #1049 = MVE_VCVTs16f16a
	{ 6, OperandInfo248 },	// Inst #1050 = MVE_VCVTs16f16m
	{ 6, OperandInfo248 },	// Inst #1051 = MVE_VCVTs16f16n
	{ 6, OperandInfo248 },	// Inst #1052 = MVE_VCVTs16f16p
	{ 6, OperandInfo248 },	// Inst #1053 = MVE_VCVTs16f16z
	{ 7, OperandInfo264 },	// Inst #1054 = MVE_VCVTs32f32_fix
	{ 6, OperandInfo248 },	// Inst #1055 = MVE_VCVTs32f32a
	{ 6, OperandInfo248 },	// Inst #1056 = MVE_VCVTs32f32m
	{ 6, OperandInfo248 },	// Inst #1057 = MVE_VCVTs32f32n
	{ 6, OperandInfo248 },	// Inst #1058 = MVE_VCVTs32f32p
	{ 6, OperandInfo248 },	// Inst #1059 = MVE_VCVTs32f32z
	{ 7, OperandInfo264 },	// Inst #1060 = MVE_VCVTu16f16_fix
	{ 6, OperandInfo248 },	// Inst #1061 = MVE_VCVTu16f16a
	{ 6, OperandInfo248 },	// Inst #1062 = MVE_VCVTu16f16m
	{ 6, OperandInfo248 },	// Inst #1063 = MVE_VCVTu16f16n
	{ 6, OperandInfo248 },	// Inst #1064 = MVE_VCVTu16f16p
	{ 6, OperandInfo248 },	// Inst #1065 = MVE_VCVTu16f16z
	{ 7, OperandInfo264 },	// Inst #1066 = MVE_VCVTu32f32_fix
	{ 6, OperandInfo248 },	// Inst #1067 = MVE_VCVTu32f32a
	{ 6, OperandInfo248 },	// Inst #1068 = MVE_VCVTu32f32m
	{ 6, OperandInfo248 },	// Inst #1069 = MVE_VCVTu32f32n
	{ 6, OperandInfo248 },	// Inst #1070 = MVE_VCVTu32f32p
	{ 6, OperandInfo248 },	// Inst #1071 = MVE_VCVTu32f32z
	{ 8, OperandInfo265 },	// Inst #1072 = MVE_VDDUPu16
	{ 8, OperandInfo265 },	// Inst #1073 = MVE_VDDUPu32
	{ 8, OperandInfo265 },	// Inst #1074 = MVE_VDDUPu8
	{ 6, OperandInfo266 },	// Inst #1075 = MVE_VDUP16
	{ 6, OperandInfo266 },	// Inst #1076 = MVE_VDUP32
	{ 6, OperandInfo266 },	// Inst #1077 = MVE_VDUP8
	{ 9, OperandInfo267 },	// Inst #1078 = MVE_VDWDUPu16
	{ 9, OperandInfo267 },	// Inst #1079 = MVE_VDWDUPu32
	{ 9, OperandInfo267 },	// Inst #1080 = MVE_VDWDUPu8
	{ 7, OperandInfo247 },	// Inst #1081 = MVE_VEOR
	{ 7, OperandInfo268 },	// Inst #1082 = MVE_VFMA_qr_Sf16
	{ 7, OperandInfo268 },	// Inst #1083 = MVE_VFMA_qr_Sf32
	{ 7, OperandInfo268 },	// Inst #1084 = MVE_VFMA_qr_f16
	{ 7, OperandInfo268 },	// Inst #1085 = MVE_VFMA_qr_f32
	{ 7, OperandInfo269 },	// Inst #1086 = MVE_VFMAf16
	{ 7, OperandInfo269 },	// Inst #1087 = MVE_VFMAf32
	{ 7, OperandInfo269 },	// Inst #1088 = MVE_VFMSf16
	{ 7, OperandInfo269 },	// Inst #1089 = MVE_VFMSf32
	{ 7, OperandInfo255 },	// Inst #1090 = MVE_VHADD_qr_s16
	{ 7, OperandInfo255 },	// Inst #1091 = MVE_VHADD_qr_s32
	{ 7, OperandInfo255 },	// Inst #1092 = MVE_VHADD_qr_s8
	{ 7, OperandInfo255 },	// Inst #1093 = MVE_VHADD_qr_u16
	{ 7, OperandInfo255 },	// Inst #1094 = MVE_VHADD_qr_u32
	{ 7, OperandInfo255 },	// Inst #1095 = MVE_VHADD_qr_u8
	{ 7, OperandInfo247 },	// Inst #1096 = MVE_VHADDs16
	{ 7, OperandInfo247 },	// Inst #1097 = MVE_VHADDs32
	{ 7, OperandInfo247 },	// Inst #1098 = MVE_VHADDs8
	{ 7, OperandInfo247 },	// Inst #1099 = MVE_VHADDu16
	{ 7, OperandInfo247 },	// Inst #1100 = MVE_VHADDu32
	{ 7, OperandInfo247 },	// Inst #1101 = MVE_VHADDu8
	{ 8, OperandInfo257 },	// Inst #1102 = MVE_VHCADDs16
	{ 8, OperandInfo258 },	// Inst #1103 = MVE_VHCADDs32
	{ 8, OperandInfo257 },	// Inst #1104 = MVE_VHCADDs8
	{ 7, OperandInfo255 },	// Inst #1105 = MVE_VHSUB_qr_s16
	{ 7, OperandInfo255 },	// Inst #1106 = MVE_VHSUB_qr_s32
	{ 7, OperandInfo255 },	// Inst #1107 = MVE_VHSUB_qr_s8
	{ 7, OperandInfo255 },	// Inst #1108 = MVE_VHSUB_qr_u16
	{ 7, OperandInfo255 },	// Inst #1109 = MVE_VHSUB_qr_u32
	{ 7, OperandInfo255 },	// Inst #1110 = MVE_VHSUB_qr_u8
	{ 7, OperandInfo247 },	// Inst #1111 = MVE_VHSUBs16
	{ 7, OperandInfo247 },	// Inst #1112 = MVE_VHSUBs32
	{ 7, OperandInfo247 },	// Inst #1113 = MVE_VHSUBs8
	{ 7, OperandInfo247 },	// Inst #1114 = MVE_VHSUBu16
	{ 7, OperandInfo247 },	// Inst #1115 = MVE_VHSUBu32
	{ 7, OperandInfo247 },	// Inst #1116 = MVE_VHSUBu8
	{ 8, OperandInfo265 },	// Inst #1117 = MVE_VIDUPu16
	{ 8, OperandInfo265 },	// Inst #1118 = MVE_VIDUPu32
	{ 8, OperandInfo265 },	// Inst #1119 = MVE_VIDUPu8
	{ 9, OperandInfo267 },	// Inst #1120 = MVE_VIWDUPu16
	{ 9, OperandInfo267 },	// Inst #1121 = MVE_VIWDUPu32
	{ 9, OperandInfo267 },	// Inst #1122 = MVE_VIWDUPu8
	{ 3, OperandInfo270 },	// Inst #1123 = MVE_VLD20_16
	{ 4, OperandInfo271 },	// Inst #1124 = MVE_VLD20_16_wb
	{ 3, OperandInfo270 },	// Inst #1125 = MVE_VLD20_32
	{ 4, OperandInfo271 },	// Inst #1126 = MVE_VLD20_32_wb
	{ 3, OperandInfo270 },	// Inst #1127 = MVE_VLD20_8
	{ 4, OperandInfo271 },	// Inst #1128 = MVE_VLD20_8_wb
	{ 3, OperandInfo270 },	// Inst #1129 = MVE_VLD21_16
	{ 4, OperandInfo271 },	// Inst #1130 = MVE_VLD21_16_wb
	{ 3, OperandInfo270 },	// Inst #1131 = MVE_VLD21_32
	{ 4, OperandInfo271 },	// Inst #1132 = MVE_VLD21_32_wb
	{ 3, OperandInfo270 },	// Inst #1133 = MVE_VLD21_8
	{ 4, OperandInfo271 },	// Inst #1134 = MVE_VLD21_8_wb
	{ 3, OperandInfo272 },	// Inst #1135 = MVE_VLD40_16
	{ 4, OperandInfo273 },	// Inst #1136 = MVE_VLD40_16_wb
	{ 3, OperandInfo272 },	// Inst #1137 = MVE_VLD40_32
	{ 4, OperandInfo273 },	// Inst #1138 = MVE_VLD40_32_wb
	{ 3, OperandInfo272 },	// Inst #1139 = MVE_VLD40_8
	{ 4, OperandInfo273 },	// Inst #1140 = MVE_VLD40_8_wb
	{ 3, OperandInfo272 },	// Inst #1141 = MVE_VLD41_16
	{ 4, OperandInfo273 },	// Inst #1142 = MVE_VLD41_16_wb
	{ 3, OperandInfo272 },	// Inst #1143 = MVE_VLD41_32
	{ 4, OperandInfo273 },	// Inst #1144 = MVE_VLD41_32_wb
	{ 3, OperandInfo272 },	// Inst #1145 = MVE_VLD41_8
	{ 4, OperandInfo273 },	// Inst #1146 = MVE_VLD41_8_wb
	{ 3, OperandInfo272 },	// Inst #1147 = MVE_VLD42_16
	{ 4, OperandInfo273 },	// Inst #1148 = MVE_VLD42_16_wb
	{ 3, OperandInfo272 },	// Inst #1149 = MVE_VLD42_32
	{ 4, OperandInfo273 },	// Inst #1150 = MVE_VLD42_32_wb
	{ 3, OperandInfo272 },	// Inst #1151 = MVE_VLD42_8
	{ 4, OperandInfo273 },	// Inst #1152 = MVE_VLD42_8_wb
	{ 3, OperandInfo272 },	// Inst #1153 = MVE_VLD43_16
	{ 4, OperandInfo273 },	// Inst #1154 = MVE_VLD43_16_wb
	{ 3, OperandInfo272 },	// Inst #1155 = MVE_VLD43_32
	{ 4, OperandInfo273 },	// Inst #1156 = MVE_VLD43_32_wb
	{ 3, OperandInfo272 },	// Inst #1157 = MVE_VLD43_8
	{ 4, OperandInfo273 },	// Inst #1158 = MVE_VLD43_8_wb
	{ 6, OperandInfo274 },	// Inst #1159 = MVE_VLDRBS16
	{ 7, OperandInfo275 },	// Inst #1160 = MVE_VLDRBS16_post
	{ 7, OperandInfo275 },	// Inst #1161 = MVE_VLDRBS16_pre
	{ 6, OperandInfo276 },	// Inst #1162 = MVE_VLDRBS16_rq
	{ 6, OperandInfo274 },	// Inst #1163 = MVE_VLDRBS32
	{ 7, OperandInfo275 },	// Inst #1164 = MVE_VLDRBS32_post
	{ 7, OperandInfo275 },	// Inst #1165 = MVE_VLDRBS32_pre
	{ 6, OperandInfo276 },	// Inst #1166 = MVE_VLDRBS32_rq
	{ 6, OperandInfo274 },	// Inst #1167 = MVE_VLDRBU16
	{ 7, OperandInfo275 },	// Inst #1168 = MVE_VLDRBU16_post
	{ 7, OperandInfo275 },	// Inst #1169 = MVE_VLDRBU16_pre
	{ 6, OperandInfo276 },	// Inst #1170 = MVE_VLDRBU16_rq
	{ 6, OperandInfo274 },	// Inst #1171 = MVE_VLDRBU32
	{ 7, OperandInfo275 },	// Inst #1172 = MVE_VLDRBU32_post
	{ 7, OperandInfo275 },	// Inst #1173 = MVE_VLDRBU32_pre
	{ 6, OperandInfo276 },	// Inst #1174 = MVE_VLDRBU32_rq
	{ 6, OperandInfo277 },	// Inst #1175 = MVE_VLDRBU8
	{ 7, OperandInfo278 },	// Inst #1176 = MVE_VLDRBU8_post
	{ 7, OperandInfo278 },	// Inst #1177 = MVE_VLDRBU8_pre
	{ 6, OperandInfo276 },	// Inst #1178 = MVE_VLDRBU8_rq
	{ 6, OperandInfo279 },	// Inst #1179 = MVE_VLDRDU64_qi
	{ 7, OperandInfo280 },	// Inst #1180 = MVE_VLDRDU64_qi_pre
	{ 6, OperandInfo276 },	// Inst #1181 = MVE_VLDRDU64_rq
	{ 6, OperandInfo276 },	// Inst #1182 = MVE_VLDRDU64_rq_u
	{ 6, OperandInfo274 },	// Inst #1183 = MVE_VLDRHS32
	{ 7, OperandInfo275 },	// Inst #1184 = MVE_VLDRHS32_post
	{ 7, OperandInfo275 },	// Inst #1185 = MVE_VLDRHS32_pre
	{ 6, OperandInfo276 },	// Inst #1186 = MVE_VLDRHS32_rq
	{ 6, OperandInfo276 },	// Inst #1187 = MVE_VLDRHS32_rq_u
	{ 6, OperandInfo277 },	// Inst #1188 = MVE_VLDRHU16
	{ 7, OperandInfo278 },	// Inst #1189 = MVE_VLDRHU16_post
	{ 7, OperandInfo278 },	// Inst #1190 = MVE_VLDRHU16_pre
	{ 6, OperandInfo276 },	// Inst #1191 = MVE_VLDRHU16_rq
	{ 6, OperandInfo276 },	// Inst #1192 = MVE_VLDRHU16_rq_u
	{ 6, OperandInfo274 },	// Inst #1193 = MVE_VLDRHU32
	{ 7, OperandInfo275 },	// Inst #1194 = MVE_VLDRHU32_post
	{ 7, OperandInfo275 },	// Inst #1195 = MVE_VLDRHU32_pre
	{ 6, OperandInfo276 },	// Inst #1196 = MVE_VLDRHU32_rq
	{ 6, OperandInfo276 },	// Inst #1197 = MVE_VLDRHU32_rq_u
	{ 6, OperandInfo277 },	// Inst #1198 = MVE_VLDRWU32
	{ 7, OperandInfo278 },	// Inst #1199 = MVE_VLDRWU32_post
	{ 7, OperandInfo278 },	// Inst #1200 = MVE_VLDRWU32_pre
	{ 6, OperandInfo279 },	// Inst #1201 = MVE_VLDRWU32_qi
	{ 7, OperandInfo280 },	// Inst #1202 = MVE_VLDRWU32_qi_pre
	{ 6, OperandInfo276 },	// Inst #1203 = MVE_VLDRWU32_rq
	{ 6, OperandInfo276 },	// Inst #1204 = MVE_VLDRWU32_rq_u
	{ 6, OperandInfo281 },	// Inst #1205 = MVE_VMAXAVs16
	{ 6, OperandInfo281 },	// Inst #1206 = MVE_VMAXAVs32
	{ 6, OperandInfo281 },	// Inst #1207 = MVE_VMAXAVs8
	{ 6, OperandInfo263 },	// Inst #1208 = MVE_VMAXAs16
	{ 6, OperandInfo263 },	// Inst #1209 = MVE_VMAXAs32
	{ 6, OperandInfo263 },	// Inst #1210 = MVE_VMAXAs8
	{ 6, OperandInfo281 },	// Inst #1211 = MVE_VMAXNMAVf16
	{ 6, OperandInfo281 },	// Inst #1212 = MVE_VMAXNMAVf32
	{ 6, OperandInfo263 },	// Inst #1213 = MVE_VMAXNMAf16
	{ 6, OperandInfo263 },	// Inst #1214 = MVE_VMAXNMAf32
	{ 6, OperandInfo281 },	// Inst #1215 = MVE_VMAXNMVf16
	{ 6, OperandInfo281 },	// Inst #1216 = MVE_VMAXNMVf32
	{ 7, OperandInfo247 },	// Inst #1217 = MVE_VMAXNMf16
	{ 7, OperandInfo247 },	// Inst #1218 = MVE_VMAXNMf32
	{ 6, OperandInfo281 },	// Inst #1219 = MVE_VMAXVs16
	{ 6, OperandInfo281 },	// Inst #1220 = MVE_VMAXVs32
	{ 6, OperandInfo281 },	// Inst #1221 = MVE_VMAXVs8
	{ 6, OperandInfo281 },	// Inst #1222 = MVE_VMAXVu16
	{ 6, OperandInfo281 },	// Inst #1223 = MVE_VMAXVu32
	{ 6, OperandInfo281 },	// Inst #1224 = MVE_VMAXVu8
	{ 7, OperandInfo247 },	// Inst #1225 = MVE_VMAXs16
	{ 7, OperandInfo247 },	// Inst #1226 = MVE_VMAXs32
	{ 7, OperandInfo247 },	// Inst #1227 = MVE_VMAXs8
	{ 7, OperandInfo247 },	// Inst #1228 = MVE_VMAXu16
	{ 7, OperandInfo247 },	// Inst #1229 = MVE_VMAXu32
	{ 7, OperandInfo247 },	// Inst #1230 = MVE_VMAXu8
	{ 6, OperandInfo281 },	// Inst #1231 = MVE_VMINAVs16
	{ 6, OperandInfo281 },	// Inst #1232 = MVE_VMINAVs32
	{ 6, OperandInfo281 },	// Inst #1233 = MVE_VMINAVs8
	{ 6, OperandInfo263 },	// Inst #1234 = MVE_VMINAs16
	{ 6, OperandInfo263 },	// Inst #1235 = MVE_VMINAs32
	{ 6, OperandInfo263 },	// Inst #1236 = MVE_VMINAs8
	{ 6, OperandInfo281 },	// Inst #1237 = MVE_VMINNMAVf16
	{ 6, OperandInfo281 },	// Inst #1238 = MVE_VMINNMAVf32
	{ 6, OperandInfo263 },	// Inst #1239 = MVE_VMINNMAf16
	{ 6, OperandInfo263 },	// Inst #1240 = MVE_VMINNMAf32
	{ 6, OperandInfo281 },	// Inst #1241 = MVE_VMINNMVf16
	{ 6, OperandInfo281 },	// Inst #1242 = MVE_VMINNMVf32
	{ 7, OperandInfo247 },	// Inst #1243 = MVE_VMINNMf16
	{ 7, OperandInfo247 },	// Inst #1244 = MVE_VMINNMf32
	{ 6, OperandInfo281 },	// Inst #1245 = MVE_VMINVs16
	{ 6, OperandInfo281 },	// Inst #1246 = MVE_VMINVs32
	{ 6, OperandInfo281 },	// Inst #1247 = MVE_VMINVs8
	{ 6, OperandInfo281 },	// Inst #1248 = MVE_VMINVu16
	{ 6, OperandInfo281 },	// Inst #1249 = MVE_VMINVu32
	{ 6, OperandInfo281 },	// Inst #1250 = MVE_VMINVu8
	{ 7, OperandInfo247 },	// Inst #1251 = MVE_VMINs16
	{ 7, OperandInfo247 },	// Inst #1252 = MVE_VMINs32
	{ 7, OperandInfo247 },	// Inst #1253 = MVE_VMINs8
	{ 7, OperandInfo247 },	// Inst #1254 = MVE_VMINu16
	{ 7, OperandInfo247 },	// Inst #1255 = MVE_VMINu32
	{ 7, OperandInfo247 },	// Inst #1256 = MVE_VMINu8
	{ 7, OperandInfo282 },	// Inst #1257 = MVE_VMLADAVas16
	{ 7, OperandInfo282 },	// Inst #1258 = MVE_VMLADAVas32
	{ 7, OperandInfo282 },	// Inst #1259 = MVE_VMLADAVas8
	{ 7, OperandInfo282 },	// Inst #1260 = MVE_VMLADAVau16
	{ 7, OperandInfo282 },	// Inst #1261 = MVE_VMLADAVau32
	{ 7, OperandInfo282 },	// Inst #1262 = MVE_VMLADAVau8
	{ 7, OperandInfo282 },	// Inst #1263 = MVE_VMLADAVaxs16
	{ 7, OperandInfo282 },	// Inst #1264 = MVE_VMLADAVaxs32
	{ 7, OperandInfo282 },	// Inst #1265 = MVE_VMLADAVaxs8
	{ 6, OperandInfo283 },	// Inst #1266 = MVE_VMLADAVs16
	{ 6, OperandInfo283 },	// Inst #1267 = MVE_VMLADAVs32
	{ 6, OperandInfo283 },	// Inst #1268 = MVE_VMLADAVs8
	{ 6, OperandInfo283 },	// Inst #1269 = MVE_VMLADAVu16
	{ 6, OperandInfo283 },	// Inst #1270 = MVE_VMLADAVu32
	{ 6, OperandInfo283 },	// Inst #1271 = MVE_VMLADAVu8
	{ 6, OperandInfo283 },	// Inst #1272 = MVE_VMLADAVxs16
	{ 6, OperandInfo283 },	// Inst #1273 = MVE_VMLADAVxs32
	{ 6, OperandInfo283 },	// Inst #1274 = MVE_VMLADAVxs8
	{ 9, OperandInfo284 },	// Inst #1275 = MVE_VMLALDAVas16
	{ 9, OperandInfo284 },	// Inst #1276 = MVE_VMLALDAVas32
	{ 9, OperandInfo284 },	// Inst #1277 = MVE_VMLALDAVau16
	{ 9, OperandInfo284 },	// Inst #1278 = MVE_VMLALDAVau32
	{ 9, OperandInfo284 },	// Inst #1279 = MVE_VMLALDAVaxs16
	{ 9, OperandInfo284 },	// Inst #1280 = MVE_VMLALDAVaxs32
	{ 7, OperandInfo285 },	// Inst #1281 = MVE_VMLALDAVs16
	{ 7, OperandInfo285 },	// Inst #1282 = MVE_VMLALDAVs32
	{ 7, OperandInfo285 },	// Inst #1283 = MVE_VMLALDAVu16
	{ 7, OperandInfo285 },	// Inst #1284 = MVE_VMLALDAVu32
	{ 7, OperandInfo285 },	// Inst #1285 = MVE_VMLALDAVxs16
	{ 7, OperandInfo285 },	// Inst #1286 = MVE_VMLALDAVxs32
	{ 7, OperandInfo268 },	// Inst #1287 = MVE_VMLAS_qr_i16
	{ 7, OperandInfo268 },	// Inst #1288 = MVE_VMLAS_qr_i32
	{ 7, OperandInfo268 },	// Inst #1289 = MVE_VMLAS_qr_i8
	{ 7, OperandInfo268 },	// Inst #1290 = MVE_VMLA_qr_i16
	{ 7, OperandInfo268 },	// Inst #1291 = MVE_VMLA_qr_i32
	{ 7, OperandInfo268 },	// Inst #1292 = MVE_VMLA_qr_i8
	{ 7, OperandInfo282 },	// Inst #1293 = MVE_VMLSDAVas16
	{ 7, OperandInfo282 },	// Inst #1294 = MVE_VMLSDAVas32
	{ 7, OperandInfo282 },	// Inst #1295 = MVE_VMLSDAVas8
	{ 7, OperandInfo282 },	// Inst #1296 = MVE_VMLSDAVaxs16
	{ 7, OperandInfo282 },	// Inst #1297 = MVE_VMLSDAVaxs32
	{ 7, OperandInfo282 },	// Inst #1298 = MVE_VMLSDAVaxs8
	{ 6, OperandInfo283 },	// Inst #1299 = MVE_VMLSDAVs16
	{ 6, OperandInfo283 },	// Inst #1300 = MVE_VMLSDAVs32
	{ 6, OperandInfo283 },	// Inst #1301 = MVE_VMLSDAVs8
	{ 6, OperandInfo283 },	// Inst #1302 = MVE_VMLSDAVxs16
	{ 6, OperandInfo283 },	// Inst #1303 = MVE_VMLSDAVxs32
	{ 6, OperandInfo283 },	// Inst #1304 = MVE_VMLSDAVxs8
	{ 9, OperandInfo284 },	// Inst #1305 = MVE_VMLSLDAVas16
	{ 9, OperandInfo284 },	// Inst #1306 = MVE_VMLSLDAVas32
	{ 9, OperandInfo284 },	// Inst #1307 = MVE_VMLSLDAVaxs16
	{ 9, OperandInfo284 },	// Inst #1308 = MVE_VMLSLDAVaxs32
	{ 7, OperandInfo285 },	// Inst #1309 = MVE_VMLSLDAVs16
	{ 7, OperandInfo285 },	// Inst #1310 = MVE_VMLSLDAVs32
	{ 7, OperandInfo285 },	// Inst #1311 = MVE_VMLSLDAVxs16
	{ 7, OperandInfo285 },	// Inst #1312 = MVE_VMLSLDAVxs32
	{ 6, OperandInfo248 },	// Inst #1313 = MVE_VMOVLs16bh
	{ 6, OperandInfo248 },	// Inst #1314 = MVE_VMOVLs16th
	{ 6, OperandInfo248 },	// Inst #1315 = MVE_VMOVLs8bh
	{ 6, OperandInfo248 },	// Inst #1316 = MVE_VMOVLs8th
	{ 6, OperandInfo248 },	// Inst #1317 = MVE_VMOVLu16bh
	{ 6, OperandInfo248 },	// Inst #1318 = MVE_VMOVLu16th
	{ 6, OperandInfo248 },	// Inst #1319 = MVE_VMOVLu8bh
	{ 6, OperandInfo248 },	// Inst #1320 = MVE_VMOVLu8th
	{ 6, OperandInfo263 },	// Inst #1321 = MVE_VMOVNi16bh
	{ 6, OperandInfo263 },	// Inst #1322 = MVE_VMOVNi16th
	{ 6, OperandInfo263 },	// Inst #1323 = MVE_VMOVNi32bh
	{ 6, OperandInfo263 },	// Inst #1324 = MVE_VMOVNi32th
	{ 5, OperandInfo286 },	// Inst #1325 = MVE_VMOV_from_lane_32
	{ 5, OperandInfo286 },	// Inst #1326 = MVE_VMOV_from_lane_s16
	{ 5, OperandInfo286 },	// Inst #1327 = MVE_VMOV_from_lane_s8
	{ 5, OperandInfo286 },	// Inst #1328 = MVE_VMOV_from_lane_u16
	{ 5, OperandInfo286 },	// Inst #1329 = MVE_VMOV_from_lane_u8
	{ 8, OperandInfo287 },	// Inst #1330 = MVE_VMOV_q_rr
	{ 7, OperandInfo288 },	// Inst #1331 = MVE_VMOV_rr_q
	{ 6, OperandInfo289 },	// Inst #1332 = MVE_VMOV_to_lane_16
	{ 6, OperandInfo289 },	// Inst #1333 = MVE_VMOV_to_lane_32
	{ 6, OperandInfo289 },	// Inst #1334 = MVE_VMOV_to_lane_8
	{ 6, OperandInfo290 },	// Inst #1335 = MVE_VMOVimmf32
	{ 6, OperandInfo290 },	// Inst #1336 = MVE_VMOVimmi16
	{ 6, OperandInfo290 },	// Inst #1337 = MVE_VMOVimmi32
	{ 6, OperandInfo290 },	// Inst #1338 = MVE_VMOVimmi64
	{ 6, OperandInfo290 },	// Inst #1339 = MVE_VMOVimmi8
	{ 7, OperandInfo247 },	// Inst #1340 = MVE_VMULHs16
	{ 7, OperandInfo247 },	// Inst #1341 = MVE_VMULHs32
	{ 7, OperandInfo247 },	// Inst #1342 = MVE_VMULHs8
	{ 7, OperandInfo247 },	// Inst #1343 = MVE_VMULHu16
	{ 7, OperandInfo247 },	// Inst #1344 = MVE_VMULHu32
	{ 7, OperandInfo247 },	// Inst #1345 = MVE_VMULHu8
	{ 7, OperandInfo247 },	// Inst #1346 = MVE_VMULLBp16
	{ 7, OperandInfo247 },	// Inst #1347 = MVE_VMULLBp8
	{ 7, OperandInfo247 },	// Inst #1348 = MVE_VMULLBs16
	{ 7, OperandInfo291 },	// Inst #1349 = MVE_VMULLBs32
	{ 7, OperandInfo247 },	// Inst #1350 = MVE_VMULLBs8
	{ 7, OperandInfo247 },	// Inst #1351 = MVE_VMULLBu16
	{ 7, OperandInfo291 },	// Inst #1352 = MVE_VMULLBu32
	{ 7, OperandInfo247 },	// Inst #1353 = MVE_VMULLBu8
	{ 7, OperandInfo247 },	// Inst #1354 = MVE_VMULLTp16
	{ 7, OperandInfo247 },	// Inst #1355 = MVE_VMULLTp8
	{ 7, OperandInfo247 },	// Inst #1356 = MVE_VMULLTs16
	{ 7, OperandInfo291 },	// Inst #1357 = MVE_VMULLTs32
	{ 7, OperandInfo247 },	// Inst #1358 = MVE_VMULLTs8
	{ 7, OperandInfo247 },	// Inst #1359 = MVE_VMULLTu16
	{ 7, OperandInfo291 },	// Inst #1360 = MVE_VMULLTu32
	{ 7, OperandInfo247 },	// Inst #1361 = MVE_VMULLTu8
	{ 7, OperandInfo255 },	// Inst #1362 = MVE_VMUL_qr_f16
	{ 7, OperandInfo255 },	// Inst #1363 = MVE_VMUL_qr_f32
	{ 7, OperandInfo255 },	// Inst #1364 = MVE_VMUL_qr_i16
	{ 7, OperandInfo255 },	// Inst #1365 = MVE_VMUL_qr_i32
	{ 7, OperandInfo255 },	// Inst #1366 = MVE_VMUL_qr_i8
	{ 7, OperandInfo247 },	// Inst #1367 = MVE_VMULf16
	{ 7, OperandInfo247 },	// Inst #1368 = MVE_VMULf32
	{ 7, OperandInfo247 },	// Inst #1369 = MVE_VMULi16
	{ 7, OperandInfo247 },	// Inst #1370 = MVE_VMULi32
	{ 7, OperandInfo247 },	// Inst #1371 = MVE_VMULi8
	{ 6, OperandInfo248 },	// Inst #1372 = MVE_VMVN
	{ 6, OperandInfo290 },	// Inst #1373 = MVE_VMVNimmi16
	{ 6, OperandInfo290 },	// Inst #1374 = MVE_VMVNimmi32
	{ 6, OperandInfo248 },	// Inst #1375 = MVE_VNEGf16
	{ 6, OperandInfo248 },	// Inst #1376 = MVE_VNEGf32
	{ 6, OperandInfo248 },	// Inst #1377 = MVE_VNEGs16
	{ 6, OperandInfo248 },	// Inst #1378 = MVE_VNEGs32
	{ 6, OperandInfo248 },	// Inst #1379 = MVE_VNEGs8
	{ 7, OperandInfo247 },	// Inst #1380 = MVE_VORN
	{ 7, OperandInfo247 },	// Inst #1381 = MVE_VORR
	{ 6, OperandInfo256 },	// Inst #1382 = MVE_VORRimmi16
	{ 6, OperandInfo256 },	// Inst #1383 = MVE_VORRimmi32
	{ 5, OperandInfo292 },	// Inst #1384 = MVE_VPNOT
	{ 6, OperandInfo293 },	// Inst #1385 = MVE_VPSEL
	{ 1, OperandInfo2 },	// Inst #1386 = MVE_VPST
	{ 4, OperandInfo294 },	// Inst #1387 = MVE_VPTv16i8
	{ 4, OperandInfo295 },	// Inst #1388 = MVE_VPTv16i8r
	{ 4, OperandInfo294 },	// Inst #1389 = MVE_VPTv16s8
	{ 4, OperandInfo295 },	// Inst #1390 = MVE_VPTv16s8r
	{ 4, OperandInfo294 },	// Inst #1391 = MVE_VPTv16u8
	{ 4, OperandInfo295 },	// Inst #1392 = MVE_VPTv16u8r
	{ 4, OperandInfo294 },	// Inst #1393 = MVE_VPTv4f32
	{ 4, OperandInfo295 },	// Inst #1394 = MVE_VPTv4f32r
	{ 4, OperandInfo294 },	// Inst #1395 = MVE_VPTv4i32
	{ 4, OperandInfo295 },	// Inst #1396 = MVE_VPTv4i32r
	{ 4, OperandInfo294 },	// Inst #1397 = MVE_VPTv4s32
	{ 4, OperandInfo295 },	// Inst #1398 = MVE_VPTv4s32r
	{ 4, OperandInfo294 },	// Inst #1399 = MVE_VPTv4u32
	{ 4, OperandInfo295 },	// Inst #1400 = MVE_VPTv4u32r
	{ 4, OperandInfo294 },	// Inst #1401 = MVE_VPTv8f16
	{ 4, OperandInfo295 },	// Inst #1402 = MVE_VPTv8f16r
	{ 4, OperandInfo294 },	// Inst #1403 = MVE_VPTv8i16
	{ 4, OperandInfo295 },	// Inst #1404 = MVE_VPTv8i16r
	{ 4, OperandInfo294 },	// Inst #1405 = MVE_VPTv8s16
	{ 4, OperandInfo295 },	// Inst #1406 = MVE_VPTv8s16r
	{ 4, OperandInfo294 },	// Inst #1407 = MVE_VPTv8u16
	{ 4, OperandInfo295 },	// Inst #1408 = MVE_VPTv8u16r
	{ 6, OperandInfo248 },	// Inst #1409 = MVE_VQABSs16
	{ 6, OperandInfo248 },	// Inst #1410 = MVE_VQABSs32
	{ 6, OperandInfo248 },	// Inst #1411 = MVE_VQABSs8
	{ 7, OperandInfo255 },	// Inst #1412 = MVE_VQADD_qr_s16
	{ 7, OperandInfo255 },	// Inst #1413 = MVE_VQADD_qr_s32
	{ 7, OperandInfo255 },	// Inst #1414 = MVE_VQADD_qr_s8
	{ 7, OperandInfo255 },	// Inst #1415 = MVE_VQADD_qr_u16
	{ 7, OperandInfo255 },	// Inst #1416 = MVE_VQADD_qr_u32
	{ 7, OperandInfo255 },	// Inst #1417 = MVE_VQADD_qr_u8
	{ 7, OperandInfo247 },	// Inst #1418 = MVE_VQADDs16
	{ 7, OperandInfo247 },	// Inst #1419 = MVE_VQADDs32
	{ 7, OperandInfo247 },	// Inst #1420 = MVE_VQADDs8
	{ 7, OperandInfo247 },	// Inst #1421 = MVE_VQADDu16
	{ 7, OperandInfo247 },	// Inst #1422 = MVE_VQADDu32
	{ 7, OperandInfo247 },	// Inst #1423 = MVE_VQADDu8
	{ 7, OperandInfo269 },	// Inst #1424 = MVE_VQDMLADHXs16
	{ 7, OperandInfo296 },	// Inst #1425 = MVE_VQDMLADHXs32
	{ 7, OperandInfo269 },	// Inst #1426 = MVE_VQDMLADHXs8
	{ 7, OperandInfo269 },	// Inst #1427 = MVE_VQDMLADHs16
	{ 7, OperandInfo296 },	// Inst #1428 = MVE_VQDMLADHs32
	{ 7, OperandInfo269 },	// Inst #1429 = MVE_VQDMLADHs8
	{ 7, OperandInfo268 },	// Inst #1430 = MVE_VQDMLAH_qrs16
	{ 7, OperandInfo268 },	// Inst #1431 = MVE_VQDMLAH_qrs32
	{ 7, OperandInfo268 },	// Inst #1432 = MVE_VQDMLAH_qrs8
	{ 7, OperandInfo268 },	// Inst #1433 = MVE_VQDMLASH_qrs16
	{ 7, OperandInfo268 },	// Inst #1434 = MVE_VQDMLASH_qrs32
	{ 7, OperandInfo268 },	// Inst #1435 = MVE_VQDMLASH_qrs8
	{ 7, OperandInfo269 },	// Inst #1436 = MVE_VQDMLSDHXs16
	{ 7, OperandInfo296 },	// Inst #1437 = MVE_VQDMLSDHXs32
	{ 7, OperandInfo269 },	// Inst #1438 = MVE_VQDMLSDHXs8
	{ 7, OperandInfo269 },	// Inst #1439 = MVE_VQDMLSDHs16
	{ 7, OperandInfo296 },	// Inst #1440 = MVE_VQDMLSDHs32
	{ 7, OperandInfo269 },	// Inst #1441 = MVE_VQDMLSDHs8
	{ 7, OperandInfo255 },	// Inst #1442 = MVE_VQDMULH_qr_s16
	{ 7, OperandInfo255 },	// Inst #1443 = MVE_VQDMULH_qr_s32
	{ 7, OperandInfo255 },	// Inst #1444 = MVE_VQDMULH_qr_s8
	{ 7, OperandInfo247 },	// Inst #1445 = MVE_VQDMULHi16
	{ 7, OperandInfo247 },	// Inst #1446 = MVE_VQDMULHi32
	{ 7, OperandInfo247 },	// Inst #1447 = MVE_VQDMULHi8
	{ 7, OperandInfo255 },	// Inst #1448 = MVE_VQDMULL_qr_s16bh
	{ 7, OperandInfo255 },	// Inst #1449 = MVE_VQDMULL_qr_s16th
	{ 7, OperandInfo297 },	// Inst #1450 = MVE_VQDMULL_qr_s32bh
	{ 7, OperandInfo297 },	// Inst #1451 = MVE_VQDMULL_qr_s32th
	{ 7, OperandInfo247 },	// Inst #1452 = MVE_VQDMULLs16bh
	{ 7, OperandInfo247 },	// Inst #1453 = MVE_VQDMULLs16th
	{ 7, OperandInfo291 },	// Inst #1454 = MVE_VQDMULLs32bh
	{ 7, OperandInfo291 },	// Inst #1455 = MVE_VQDMULLs32th
	{ 6, OperandInfo263 },	// Inst #1456 = MVE_VQMOVNs16bh
	{ 6, OperandInfo263 },	// Inst #1457 = MVE_VQMOVNs16th
	{ 6, OperandInfo263 },	// Inst #1458 = MVE_VQMOVNs32bh
	{ 6, OperandInfo263 },	// Inst #1459 = MVE_VQMOVNs32th
	{ 6, OperandInfo263 },	// Inst #1460 = MVE_VQMOVNu16bh
	{ 6, OperandInfo263 },	// Inst #1461 = MVE_VQMOVNu16th
	{ 6, OperandInfo263 },	// Inst #1462 = MVE_VQMOVNu32bh
	{ 6, OperandInfo263 },	// Inst #1463 = MVE_VQMOVNu32th
	{ 6, OperandInfo263 },	// Inst #1464 = MVE_VQMOVUNs16bh
	{ 6, OperandInfo263 },	// Inst #1465 = MVE_VQMOVUNs16th
	{ 6, OperandInfo263 },	// Inst #1466 = MVE_VQMOVUNs32bh
	{ 6, OperandInfo263 },	// Inst #1467 = MVE_VQMOVUNs32th
	{ 6, OperandInfo248 },	// Inst #1468 = MVE_VQNEGs16
	{ 6, OperandInfo248 },	// Inst #1469 = MVE_VQNEGs32
	{ 6, OperandInfo248 },	// Inst #1470 = MVE_VQNEGs8
	{ 7, OperandInfo269 },	// Inst #1471 = MVE_VQRDMLADHXs16
	{ 7, OperandInfo296 },	// Inst #1472 = MVE_VQRDMLADHXs32
	{ 7, OperandInfo269 },	// Inst #1473 = MVE_VQRDMLADHXs8
	{ 7, OperandInfo269 },	// Inst #1474 = MVE_VQRDMLADHs16
	{ 7, OperandInfo296 },	// Inst #1475 = MVE_VQRDMLADHs32
	{ 7, OperandInfo269 },	// Inst #1476 = MVE_VQRDMLADHs8
	{ 7, OperandInfo268 },	// Inst #1477 = MVE_VQRDMLAH_qrs16
	{ 7, OperandInfo268 },	// Inst #1478 = MVE_VQRDMLAH_qrs32
	{ 7, OperandInfo268 },	// Inst #1479 = MVE_VQRDMLAH_qrs8
	{ 7, OperandInfo268 },	// Inst #1480 = MVE_VQRDMLASH_qrs16
	{ 7, OperandInfo268 },	// Inst #1481 = MVE_VQRDMLASH_qrs32
	{ 7, OperandInfo268 },	// Inst #1482 = MVE_VQRDMLASH_qrs8
	{ 7, OperandInfo269 },	// Inst #1483 = MVE_VQRDMLSDHXs16
	{ 7, OperandInfo296 },	// Inst #1484 = MVE_VQRDMLSDHXs32
	{ 7, OperandInfo269 },	// Inst #1485 = MVE_VQRDMLSDHXs8
	{ 7, OperandInfo269 },	// Inst #1486 = MVE_VQRDMLSDHs16
	{ 7, OperandInfo296 },	// Inst #1487 = MVE_VQRDMLSDHs32
	{ 7, OperandInfo269 },	// Inst #1488 = MVE_VQRDMLSDHs8
	{ 7, OperandInfo255 },	// Inst #1489 = MVE_VQRDMULH_qr_s16
	{ 7, OperandInfo255 },	// Inst #1490 = MVE_VQRDMULH_qr_s32
	{ 7, OperandInfo255 },	// Inst #1491 = MVE_VQRDMULH_qr_s8
	{ 7, OperandInfo247 },	// Inst #1492 = MVE_VQRDMULHi16
	{ 7, OperandInfo247 },	// Inst #1493 = MVE_VQRDMULHi32
	{ 7, OperandInfo247 },	// Inst #1494 = MVE_VQRDMULHi8
	{ 7, OperandInfo247 },	// Inst #1495 = MVE_VQRSHL_by_vecs16
	{ 7, OperandInfo247 },	// Inst #1496 = MVE_VQRSHL_by_vecs32
	{ 7, OperandInfo247 },	// Inst #1497 = MVE_VQRSHL_by_vecs8
	{ 7, OperandInfo247 },	// Inst #1498 = MVE_VQRSHL_by_vecu16
	{ 7, OperandInfo247 },	// Inst #1499 = MVE_VQRSHL_by_vecu32
	{ 7, OperandInfo247 },	// Inst #1500 = MVE_VQRSHL_by_vecu8
	{ 6, OperandInfo298 },	// Inst #1501 = MVE_VQRSHL_qrs16
	{ 6, OperandInfo298 },	// Inst #1502 = MVE_VQRSHL_qrs32
	{ 6, OperandInfo298 },	// Inst #1503 = MVE_VQRSHL_qrs8
	{ 6, OperandInfo298 },	// Inst #1504 = MVE_VQRSHL_qru16
	{ 6, OperandInfo298 },	// Inst #1505 = MVE_VQRSHL_qru32
	{ 6, OperandInfo298 },	// Inst #1506 = MVE_VQRSHL_qru8
	{ 7, OperandInfo299 },	// Inst #1507 = MVE_VQRSHRNbhs16
	{ 7, OperandInfo299 },	// Inst #1508 = MVE_VQRSHRNbhs32
	{ 7, OperandInfo299 },	// Inst #1509 = MVE_VQRSHRNbhu16
	{ 7, OperandInfo299 },	// Inst #1510 = MVE_VQRSHRNbhu32
	{ 7, OperandInfo299 },	// Inst #1511 = MVE_VQRSHRNths16
	{ 7, OperandInfo299 },	// Inst #1512 = MVE_VQRSHRNths32
	{ 7, OperandInfo299 },	// Inst #1513 = MVE_VQRSHRNthu16
	{ 7, OperandInfo299 },	// Inst #1514 = MVE_VQRSHRNthu32
	{ 7, OperandInfo299 },	// Inst #1515 = MVE_VQRSHRUNs16bh
	{ 7, OperandInfo299 },	// Inst #1516 = MVE_VQRSHRUNs16th
	{ 7, OperandInfo299 },	// Inst #1517 = MVE_VQRSHRUNs32bh
	{ 7, OperandInfo299 },	// Inst #1518 = MVE_VQRSHRUNs32th
	{ 7, OperandInfo264 },	// Inst #1519 = MVE_VQSHLU_imms16
	{ 7, OperandInfo264 },	// Inst #1520 = MVE_VQSHLU_imms32
	{ 7, OperandInfo264 },	// Inst #1521 = MVE_VQSHLU_imms8
	{ 7, OperandInfo247 },	// Inst #1522 = MVE_VQSHL_by_vecs16
	{ 7, OperandInfo247 },	// Inst #1523 = MVE_VQSHL_by_vecs32
	{ 7, OperandInfo247 },	// Inst #1524 = MVE_VQSHL_by_vecs8
	{ 7, OperandInfo247 },	// Inst #1525 = MVE_VQSHL_by_vecu16
	{ 7, OperandInfo247 },	// Inst #1526 = MVE_VQSHL_by_vecu32
	{ 7, OperandInfo247 },	// Inst #1527 = MVE_VQSHL_by_vecu8
	{ 6, OperandInfo298 },	// Inst #1528 = MVE_VQSHL_qrs16
	{ 6, OperandInfo298 },	// Inst #1529 = MVE_VQSHL_qrs32
	{ 6, OperandInfo298 },	// Inst #1530 = MVE_VQSHL_qrs8
	{ 6, OperandInfo298 },	// Inst #1531 = MVE_VQSHL_qru16
	{ 6, OperandInfo298 },	// Inst #1532 = MVE_VQSHL_qru32
	{ 6, OperandInfo298 },	// Inst #1533 = MVE_VQSHL_qru8
	{ 7, OperandInfo264 },	// Inst #1534 = MVE_VQSHLimms16
	{ 7, OperandInfo264 },	// Inst #1535 = MVE_VQSHLimms32
	{ 7, OperandInfo264 },	// Inst #1536 = MVE_VQSHLimms8
	{ 7, OperandInfo264 },	// Inst #1537 = MVE_VQSHLimmu16
	{ 7, OperandInfo264 },	// Inst #1538 = MVE_VQSHLimmu32
	{ 7, OperandInfo264 },	// Inst #1539 = MVE_VQSHLimmu8
	{ 7, OperandInfo299 },	// Inst #1540 = MVE_VQSHRNbhs16
	{ 7, OperandInfo299 },	// Inst #1541 = MVE_VQSHRNbhs32
	{ 7, OperandInfo299 },	// Inst #1542 = MVE_VQSHRNbhu16
	{ 7, OperandInfo299 },	// Inst #1543 = MVE_VQSHRNbhu32
	{ 7, OperandInfo299 },	// Inst #1544 = MVE_VQSHRNths16
	{ 7, OperandInfo299 },	// Inst #1545 = MVE_VQSHRNths32
	{ 7, OperandInfo299 },	// Inst #1546 = MVE_VQSHRNthu16
	{ 7, OperandInfo299 },	// Inst #1547 = MVE_VQSHRNthu32
	{ 7, OperandInfo299 },	// Inst #1548 = MVE_VQSHRUNs16bh
	{ 7, OperandInfo299 },	// Inst #1549 = MVE_VQSHRUNs16th
	{ 7, OperandInfo299 },	// Inst #1550 = MVE_VQSHRUNs32bh
	{ 7, OperandInfo299 },	// Inst #1551 = MVE_VQSHRUNs32th
	{ 7, OperandInfo255 },	// Inst #1552 = MVE_VQSUB_qr_s16
	{ 7, OperandInfo255 },	// Inst #1553 = MVE_VQSUB_qr_s32
	{ 7, OperandInfo255 },	// Inst #1554 = MVE_VQSUB_qr_s8
	{ 7, OperandInfo255 },	// Inst #1555 = MVE_VQSUB_qr_u16
	{ 7, OperandInfo255 },	// Inst #1556 = MVE_VQSUB_qr_u32
	{ 7, OperandInfo255 },	// Inst #1557 = MVE_VQSUB_qr_u8
	{ 7, OperandInfo247 },	// Inst #1558 = MVE_VQSUBs16
	{ 7, OperandInfo247 },	// Inst #1559 = MVE_VQSUBs32
	{ 7, OperandInfo247 },	// Inst #1560 = MVE_VQSUBs8
	{ 7, OperandInfo247 },	// Inst #1561 = MVE_VQSUBu16
	{ 7, OperandInfo247 },	// Inst #1562 = MVE_VQSUBu32
	{ 7, OperandInfo247 },	// Inst #1563 = MVE_VQSUBu8
	{ 6, OperandInfo248 },	// Inst #1564 = MVE_VREV16_8
	{ 6, OperandInfo248 },	// Inst #1565 = MVE_VREV32_16
	{ 6, OperandInfo248 },	// Inst #1566 = MVE_VREV32_8
	{ 6, OperandInfo300 },	// Inst #1567 = MVE_VREV64_16
	{ 6, OperandInfo300 },	// Inst #1568 = MVE_VREV64_32
	{ 6, OperandInfo300 },	// Inst #1569 = MVE_VREV64_8
	{ 7, OperandInfo247 },	// Inst #1570 = MVE_VRHADDs16
	{ 7, OperandInfo247 },	// Inst #1571 = MVE_VRHADDs32
	{ 7, OperandInfo247 },	// Inst #1572 = MVE_VRHADDs8
	{ 7, OperandInfo247 },	// Inst #1573 = MVE_VRHADDu16
	{ 7, OperandInfo247 },	// Inst #1574 = MVE_VRHADDu32
	{ 7, OperandInfo247 },	// Inst #1575 = MVE_VRHADDu8
	{ 6, OperandInfo248 },	// Inst #1576 = MVE_VRINTf16A
	{ 6, OperandInfo248 },	// Inst #1577 = MVE_VRINTf16M
	{ 6, OperandInfo248 },	// Inst #1578 = MVE_VRINTf16N
	{ 6, OperandInfo248 },	// Inst #1579 = MVE_VRINTf16P
	{ 6, OperandInfo248 },	// Inst #1580 = MVE_VRINTf16X
	{ 6, OperandInfo248 },	// Inst #1581 = MVE_VRINTf16Z
	{ 6, OperandInfo248 },	// Inst #1582 = MVE_VRINTf32A
	{ 6, OperandInfo248 },	// Inst #1583 = MVE_VRINTf32M
	{ 6, OperandInfo248 },	// Inst #1584 = MVE_VRINTf32N
	{ 6, OperandInfo248 },	// Inst #1585 = MVE_VRINTf32P
	{ 6, OperandInfo248 },	// Inst #1586 = MVE_VRINTf32X
	{ 6, OperandInfo248 },	// Inst #1587 = MVE_VRINTf32Z
	{ 9, OperandInfo284 },	// Inst #1588 = MVE_VRMLALDAVHas32
	{ 9, OperandInfo284 },	// Inst #1589 = MVE_VRMLALDAVHau32
	{ 9, OperandInfo284 },	// Inst #1590 = MVE_VRMLALDAVHaxs32
	{ 7, OperandInfo285 },	// Inst #1591 = MVE_VRMLALDAVHs32
	{ 7, OperandInfo285 },	// Inst #1592 = MVE_VRMLALDAVHu32
	{ 7, OperandInfo285 },	// Inst #1593 = MVE_VRMLALDAVHxs32
	{ 9, OperandInfo284 },	// Inst #1594 = MVE_VRMLSLDAVHas32
	{ 9, OperandInfo284 },	// Inst #1595 = MVE_VRMLSLDAVHaxs32
	{ 7, OperandInfo285 },	// Inst #1596 = MVE_VRMLSLDAVHs32
	{ 7, OperandInfo285 },	// Inst #1597 = MVE_VRMLSLDAVHxs32
	{ 7, OperandInfo247 },	// Inst #1598 = MVE_VRMULHs16
	{ 7, OperandInfo247 },	// Inst #1599 = MVE_VRMULHs32
	{ 7, OperandInfo247 },	// Inst #1600 = MVE_VRMULHs8
	{ 7, OperandInfo247 },	// Inst #1601 = MVE_VRMULHu16
	{ 7, OperandInfo247 },	// Inst #1602 = MVE_VRMULHu32
	{ 7, OperandInfo247 },	// Inst #1603 = MVE_VRMULHu8
	{ 7, OperandInfo247 },	// Inst #1604 = MVE_VRSHL_by_vecs16
	{ 7, OperandInfo247 },	// Inst #1605 = MVE_VRSHL_by_vecs32
	{ 7, OperandInfo247 },	// Inst #1606 = MVE_VRSHL_by_vecs8
	{ 7, OperandInfo247 },	// Inst #1607 = MVE_VRSHL_by_vecu16
	{ 7, OperandInfo247 },	// Inst #1608 = MVE_VRSHL_by_vecu32
	{ 7, OperandInfo247 },	// Inst #1609 = MVE_VRSHL_by_vecu8
	{ 6, OperandInfo298 },	// Inst #1610 = MVE_VRSHL_qrs16
	{ 6, OperandInfo298 },	// Inst #1611 = MVE_VRSHL_qrs32
	{ 6, OperandInfo298 },	// Inst #1612 = MVE_VRSHL_qrs8
	{ 6, OperandInfo298 },	// Inst #1613 = MVE_VRSHL_qru16
	{ 6, OperandInfo298 },	// Inst #1614 = MVE_VRSHL_qru32
	{ 6, OperandInfo298 },	// Inst #1615 = MVE_VRSHL_qru8
	{ 7, OperandInfo299 },	// Inst #1616 = MVE_VRSHRNi16bh
	{ 7, OperandInfo299 },	// Inst #1617 = MVE_VRSHRNi16th
	{ 7, OperandInfo299 },	// Inst #1618 = MVE_VRSHRNi32bh
	{ 7, OperandInfo299 },	// Inst #1619 = MVE_VRSHRNi32th
	{ 7, OperandInfo264 },	// Inst #1620 = MVE_VRSHR_imms16
	{ 7, OperandInfo264 },	// Inst #1621 = MVE_VRSHR_imms32
	{ 7, OperandInfo264 },	// Inst #1622 = MVE_VRSHR_imms8
	{ 7, OperandInfo264 },	// Inst #1623 = MVE_VRSHR_immu16
	{ 7, OperandInfo264 },	// Inst #1624 = MVE_VRSHR_immu32
	{ 7, OperandInfo264 },	// Inst #1625 = MVE_VRSHR_immu8
	{ 9, OperandInfo249 },	// Inst #1626 = MVE_VSBC
	{ 8, OperandInfo250 },	// Inst #1627 = MVE_VSBCI
	{ 8, OperandInfo301 },	// Inst #1628 = MVE_VSHLC
	{ 7, OperandInfo264 },	// Inst #1629 = MVE_VSHLL_imms16bh
	{ 7, OperandInfo264 },	// Inst #1630 = MVE_VSHLL_imms16th
	{ 7, OperandInfo264 },	// Inst #1631 = MVE_VSHLL_imms8bh
	{ 7, OperandInfo264 },	// Inst #1632 = MVE_VSHLL_imms8th
	{ 7, OperandInfo264 },	// Inst #1633 = MVE_VSHLL_immu16bh
	{ 7, OperandInfo264 },	// Inst #1634 = MVE_VSHLL_immu16th
	{ 7, OperandInfo264 },	// Inst #1635 = MVE_VSHLL_immu8bh
	{ 7, OperandInfo264 },	// Inst #1636 = MVE_VSHLL_immu8th
	{ 6, OperandInfo248 },	// Inst #1637 = MVE_VSHLL_lws16bh
	{ 6, OperandInfo248 },	// Inst #1638 = MVE_VSHLL_lws16th
	{ 6, OperandInfo248 },	// Inst #1639 = MVE_VSHLL_lws8bh
	{ 6, OperandInfo248 },	// Inst #1640 = MVE_VSHLL_lws8th
	{ 6, OperandInfo248 },	// Inst #1641 = MVE_VSHLL_lwu16bh
	{ 6, OperandInfo248 },	// Inst #1642 = MVE_VSHLL_lwu16th
	{ 6, OperandInfo248 },	// Inst #1643 = MVE_VSHLL_lwu8bh
	{ 6, OperandInfo248 },	// Inst #1644 = MVE_VSHLL_lwu8th
	{ 7, OperandInfo247 },	// Inst #1645 = MVE_VSHL_by_vecs16
	{ 7, OperandInfo247 },	// Inst #1646 = MVE_VSHL_by_vecs32
	{ 7, OperandInfo247 },	// Inst #1647 = MVE_VSHL_by_vecs8
	{ 7, OperandInfo247 },	// Inst #1648 = MVE_VSHL_by_vecu16
	{ 7, OperandInfo247 },	// Inst #1649 = MVE_VSHL_by_vecu32
	{ 7, OperandInfo247 },	// Inst #1650 = MVE_VSHL_by_vecu8
	{ 7, OperandInfo264 },	// Inst #1651 = MVE_VSHL_immi16
	{ 7, OperandInfo264 },	// Inst #1652 = MVE_VSHL_immi32
	{ 7, OperandInfo264 },	// Inst #1653 = MVE_VSHL_immi8
	{ 6, OperandInfo298 },	// Inst #1654 = MVE_VSHL_qrs16
	{ 6, OperandInfo298 },	// Inst #1655 = MVE_VSHL_qrs32
	{ 6, OperandInfo298 },	// Inst #1656 = MVE_VSHL_qrs8
	{ 6, OperandInfo298 },	// Inst #1657 = MVE_VSHL_qru16
	{ 6, OperandInfo298 },	// Inst #1658 = MVE_VSHL_qru32
	{ 6, OperandInfo298 },	// Inst #1659 = MVE_VSHL_qru8
	{ 7, OperandInfo299 },	// Inst #1660 = MVE_VSHRNi16bh
	{ 7, OperandInfo299 },	// Inst #1661 = MVE_VSHRNi16th
	{ 7, OperandInfo299 },	// Inst #1662 = MVE_VSHRNi32bh
	{ 7, OperandInfo299 },	// Inst #1663 = MVE_VSHRNi32th
	{ 7, OperandInfo264 },	// Inst #1664 = MVE_VSHR_imms16
	{ 7, OperandInfo264 },	// Inst #1665 = MVE_VSHR_imms32
	{ 7, OperandInfo264 },	// Inst #1666 = MVE_VSHR_imms8
	{ 7, OperandInfo264 },	// Inst #1667 = MVE_VSHR_immu16
	{ 7, OperandInfo264 },	// Inst #1668 = MVE_VSHR_immu32
	{ 7, OperandInfo264 },	// Inst #1669 = MVE_VSHR_immu8
	{ 7, OperandInfo299 },	// Inst #1670 = MVE_VSLIimm16
	{ 7, OperandInfo299 },	// Inst #1671 = MVE_VSLIimm32
	{ 7, OperandInfo299 },	// Inst #1672 = MVE_VSLIimm8
	{ 7, OperandInfo299 },	// Inst #1673 = MVE_VSRIimm16
	{ 7, OperandInfo299 },	// Inst #1674 = MVE_VSRIimm32
	{ 7, OperandInfo299 },	// Inst #1675 = MVE_VSRIimm8
	{ 2, OperandInfo302 },	// Inst #1676 = MVE_VST20_16
	{ 3, OperandInfo303 },	// Inst #1677 = MVE_VST20_16_wb
	{ 2, OperandInfo302 },	// Inst #1678 = MVE_VST20_32
	{ 3, OperandInfo303 },	// Inst #1679 = MVE_VST20_32_wb
	{ 2, OperandInfo302 },	// Inst #1680 = MVE_VST20_8
	{ 3, OperandInfo303 },	// Inst #1681 = MVE_VST20_8_wb
	{ 2, OperandInfo302 },	// Inst #1682 = MVE_VST21_16
	{ 3, OperandInfo303 },	// Inst #1683 = MVE_VST21_16_wb
	{ 2, OperandInfo302 },	// Inst #1684 = MVE_VST21_32
	{ 3, OperandInfo303 },	// Inst #1685 = MVE_VST21_32_wb
	{ 2, OperandInfo302 },	// Inst #1686 = MVE_VST21_8
	{ 3, OperandInfo303 },	// Inst #1687 = MVE_VST21_8_wb
	{ 2, OperandInfo304 },	// Inst #1688 = MVE_VST40_16
	{ 3, OperandInfo305 },	// Inst #1689 = MVE_VST40_16_wb
	{ 2, OperandInfo304 },	// Inst #1690 = MVE_VST40_32
	{ 3, OperandInfo305 },	// Inst #1691 = MVE_VST40_32_wb
	{ 2, OperandInfo304 },	// Inst #1692 = MVE_VST40_8
	{ 3, OperandInfo305 },	// Inst #1693 = MVE_VST40_8_wb
	{ 2, OperandInfo304 },	// Inst #1694 = MVE_VST41_16
	{ 3, OperandInfo305 },	// Inst #1695 = MVE_VST41_16_wb
	{ 2, OperandInfo304 },	// Inst #1696 = MVE_VST41_32
	{ 3, OperandInfo305 },	// Inst #1697 = MVE_VST41_32_wb
	{ 2, OperandInfo304 },	// Inst #1698 = MVE_VST41_8
	{ 3, OperandInfo305 },	// Inst #1699 = MVE_VST41_8_wb
	{ 2, OperandInfo304 },	// Inst #1700 = MVE_VST42_16
	{ 3, OperandInfo305 },	// Inst #1701 = MVE_VST42_16_wb
	{ 2, OperandInfo304 },	// Inst #1702 = MVE_VST42_32
	{ 3, OperandInfo305 },	// Inst #1703 = MVE_VST42_32_wb
	{ 2, OperandInfo304 },	// Inst #1704 = MVE_VST42_8
	{ 3, OperandInfo305 },	// Inst #1705 = MVE_VST42_8_wb
	{ 2, OperandInfo304 },	// Inst #1706 = MVE_VST43_16
	{ 3, OperandInfo305 },	// Inst #1707 = MVE_VST43_16_wb
	{ 2, OperandInfo304 },	// Inst #1708 = MVE_VST43_32
	{ 3, OperandInfo305 },	// Inst #1709 = MVE_VST43_32_wb
	{ 2, OperandInfo304 },	// Inst #1710 = MVE_VST43_8
	{ 3, OperandInfo305 },	// Inst #1711 = MVE_VST43_8_wb
	{ 6, OperandInfo274 },	// Inst #1712 = MVE_VSTRB16
	{ 7, OperandInfo275 },	// Inst #1713 = MVE_VSTRB16_post
	{ 7, OperandInfo275 },	// Inst #1714 = MVE_VSTRB16_pre
	{ 6, OperandInfo306 },	// Inst #1715 = MVE_VSTRB16_rq
	{ 6, OperandInfo274 },	// Inst #1716 = MVE_VSTRB32
	{ 7, OperandInfo275 },	// Inst #1717 = MVE_VSTRB32_post
	{ 7, OperandInfo275 },	// Inst #1718 = MVE_VSTRB32_pre
	{ 6, OperandInfo306 },	// Inst #1719 = MVE_VSTRB32_rq
	{ 6, OperandInfo306 },	// Inst #1720 = MVE_VSTRB8_rq
	{ 6, OperandInfo277 },	// Inst #1721 = MVE_VSTRBU8
	{ 7, OperandInfo278 },	// Inst #1722 = MVE_VSTRBU8_post
	{ 7, OperandInfo278 },	// Inst #1723 = MVE_VSTRBU8_pre
	{ 6, OperandInfo307 },	// Inst #1724 = MVE_VSTRD64_qi
	{ 7, OperandInfo308 },	// Inst #1725 = MVE_VSTRD64_qi_pre
	{ 6, OperandInfo306 },	// Inst #1726 = MVE_VSTRD64_rq
	{ 6, OperandInfo306 },	// Inst #1727 = MVE_VSTRD64_rq_u
	{ 6, OperandInfo306 },	// Inst #1728 = MVE_VSTRH16_rq
	{ 6, OperandInfo306 },	// Inst #1729 = MVE_VSTRH16_rq_u
	{ 6, OperandInfo274 },	// Inst #1730 = MVE_VSTRH32
	{ 7, OperandInfo275 },	// Inst #1731 = MVE_VSTRH32_post
	{ 7, OperandInfo275 },	// Inst #1732 = MVE_VSTRH32_pre
	{ 6, OperandInfo306 },	// Inst #1733 = MVE_VSTRH32_rq
	{ 6, OperandInfo306 },	// Inst #1734 = MVE_VSTRH32_rq_u
	{ 6, OperandInfo277 },	// Inst #1735 = MVE_VSTRHU16
	{ 7, OperandInfo278 },	// Inst #1736 = MVE_VSTRHU16_post
	{ 7, OperandInfo278 },	// Inst #1737 = MVE_VSTRHU16_pre
	{ 6, OperandInfo307 },	// Inst #1738 = MVE_VSTRW32_qi
	{ 7, OperandInfo308 },	// Inst #1739 = MVE_VSTRW32_qi_pre
	{ 6, OperandInfo306 },	// Inst #1740 = MVE_VSTRW32_rq
	{ 6, OperandInfo306 },	// Inst #1741 = MVE_VSTRW32_rq_u
	{ 6, OperandInfo277 },	// Inst #1742 = MVE_VSTRWU32
	{ 7, OperandInfo278 },	// Inst #1743 = MVE_VSTRWU32_post
	{ 7, OperandInfo278 },	// Inst #1744 = MVE_VSTRWU32_pre
	{ 7, OperandInfo255 },	// Inst #1745 = MVE_VSUB_qr_f16
	{ 7, OperandInfo255 },	// Inst #1746 = MVE_VSUB_qr_f32
	{ 7, OperandInfo255 },	// Inst #1747 = MVE_VSUB_qr_i16
	{ 7, OperandInfo255 },	// Inst #1748 = MVE_VSUB_qr_i32
	{ 7, OperandInfo255 },	// Inst #1749 = MVE_VSUB_qr_i8
	{ 7, OperandInfo247 },	// Inst #1750 = MVE_VSUBf16
	{ 7, OperandInfo247 },	// Inst #1751 = MVE_VSUBf32
	{ 7, OperandInfo247 },	// Inst #1752 = MVE_VSUBi16
	{ 7, OperandInfo247 },	// Inst #1753 = MVE_VSUBi32
	{ 7, OperandInfo247 },	// Inst #1754 = MVE_VSUBi8
	{ 3, OperandInfo129 },	// Inst #1755 = MVE_WLSTP_16
	{ 3, OperandInfo129 },	// Inst #1756 = MVE_WLSTP_32
	{ 3, OperandInfo129 },	// Inst #1757 = MVE_WLSTP_64
	{ 3, OperandInfo129 },	// Inst #1758 = MVE_WLSTP_8
	{ 5, OperandInfo231 },	// Inst #1759 = MVNi
	{ 5, OperandInfo88 },	// Inst #1760 = MVNr
	{ 6, OperandInfo233 },	// Inst #1761 = MVNsi
	{ 7, OperandInfo309 },	// Inst #1762 = MVNsr
	{ 3, OperandInfo310 },	// Inst #1763 = NEON_VMAXNMNDf
	{ 3, OperandInfo310 },	// Inst #1764 = NEON_VMAXNMNDh
	{ 3, OperandInfo311 },	// Inst #1765 = NEON_VMAXNMNQf
	{ 3, OperandInfo311 },	// Inst #1766 = NEON_VMAXNMNQh
	{ 3, OperandInfo310 },	// Inst #1767 = NEON_VMINNMNDf
	{ 3, OperandInfo310 },	// Inst #1768 = NEON_VMINNMNDh
	{ 3, OperandInfo311 },	// Inst #1769 = NEON_VMINNMNQf
	{ 3, OperandInfo311 },	// Inst #1770 = NEON_VMINNMNQh
	{ 6, OperandInfo51 },	// Inst #1771 = ORRri
	{ 6, OperandInfo153 },	// Inst #1772 = ORRrr
	{ 7, OperandInfo154 },	// Inst #1773 = ORRrsi
	{ 8, OperandInfo156 },	// Inst #1774 = ORRrsr
	{ 6, OperandInfo312 },	// Inst #1775 = PKHBT
	{ 6, OperandInfo312 },	// Inst #1776 = PKHTB
	{ 2, OperandInfo313 },	// Inst #1777 = PLDWi12
	{ 3, OperandInfo314 },	// Inst #1778 = PLDWrs
	{ 2, OperandInfo313 },	// Inst #1779 = PLDi12
	{ 3, OperandInfo314 },	// Inst #1780 = PLDrs
	{ 2, OperandInfo313 },	// Inst #1781 = PLIi12
	{ 3, OperandInfo314 },	// Inst #1782 = PLIrs
	{ 5, OperandInfo315 },	// Inst #1783 = QADD
	{ 5, OperandInfo315 },	// Inst #1784 = QADD16
	{ 5, OperandInfo315 },	// Inst #1785 = QADD8
	{ 5, OperandInfo315 },	// Inst #1786 = QASX
	{ 5, OperandInfo315 },	// Inst #1787 = QDADD
	{ 5, OperandInfo315 },	// Inst #1788 = QDSUB
	{ 5, OperandInfo315 },	// Inst #1789 = QSAX
	{ 5, OperandInfo315 },	// Inst #1790 = QSUB
	{ 5, OperandInfo315 },	// Inst #1791 = QSUB16
	{ 5, OperandInfo315 },	// Inst #1792 = QSUB8
	{ 4, OperandInfo197 },	// Inst #1793 = RBIT
	{ 4, OperandInfo197 },	// Inst #1794 = REV
	{ 4, OperandInfo197 },	// Inst #1795 = REV16
	{ 4, OperandInfo197 },	// Inst #1796 = REVSH
	{ 1, OperandInfo78 },	// Inst #1797 = RFEDA
	{ 2, OperandInfo316 },	// Inst #1798 = RFEDA_UPD
	{ 1, OperandInfo78 },	// Inst #1799 = RFEDB
	{ 2, OperandInfo316 },	// Inst #1800 = RFEDB_UPD
	{ 1, OperandInfo78 },	// Inst #1801 = RFEIA
	{ 2, OperandInfo316 },	// Inst #1802 = RFEIA_UPD
	{ 1, OperandInfo78 },	// Inst #1803 = RFEIB
	{ 2, OperandInfo316 },	// Inst #1804 = RFEIB_UPD
	{ 6, OperandInfo51 },	// Inst #1805 = RSBri
	{ 6, OperandInfo153 },	// Inst #1806 = RSBrr
	{ 7, OperandInfo154 },	// Inst #1807 = RSBrsi
	{ 8, OperandInfo156 },	// Inst #1808 = RSBrsr
	{ 6, OperandInfo51 },	// Inst #1809 = RSCri
	{ 6, OperandInfo153 },	// Inst #1810 = RSCrr
	{ 7, OperandInfo154 },	// Inst #1811 = RSCrsi
	{ 8, OperandInfo156 },	// Inst #1812 = RSCrsr
	{ 5, OperandInfo315 },	// Inst #1813 = SADD16
	{ 5, OperandInfo315 },	// Inst #1814 = SADD8
	{ 5, OperandInfo315 },	// Inst #1815 = SASX
	{ 0, 0 },		// Inst #1816 = SB
	{ 6, OperandInfo51 },	// Inst #1817 = SBCri
	{ 6, OperandInfo153 },	// Inst #1818 = SBCrr
	{ 7, OperandInfo154 },	// Inst #1819 = SBCrsi
	{ 8, OperandInfo155 },	// Inst #1820 = SBCrsr
	{ 6, OperandInfo317 },	// Inst #1821 = SBFX
	{ 5, OperandInfo47 },	// Inst #1822 = SDIV
	{ 5, OperandInfo47 },	// Inst #1823 = SEL
	{ 1, OperandInfo2 },	// Inst #1824 = SETEND
	{ 1, OperandInfo2 },	// Inst #1825 = SETPAN
	{ 4, OperandInfo162 },	// Inst #1826 = SHA1C
	{ 2, OperandInfo158 },	// Inst #1827 = SHA1H
	{ 4, OperandInfo162 },	// Inst #1828 = SHA1M
	{ 4, OperandInfo162 },	// Inst #1829 = SHA1P
	{ 4, OperandInfo162 },	// Inst #1830 = SHA1SU0
	{ 3, OperandInfo157 },	// Inst #1831 = SHA1SU1
	{ 4, OperandInfo162 },	// Inst #1832 = SHA256H
	{ 4, OperandInfo162 },	// Inst #1833 = SHA256H2
	{ 3, OperandInfo157 },	// Inst #1834 = SHA256SU0
	{ 4, OperandInfo162 },	// Inst #1835 = SHA256SU1
	{ 5, OperandInfo315 },	// Inst #1836 = SHADD16
	{ 5, OperandInfo315 },	// Inst #1837 = SHADD8
	{ 5, OperandInfo315 },	// Inst #1838 = SHASX
	{ 5, OperandInfo315 },	// Inst #1839 = SHSAX
	{ 5, OperandInfo315 },	// Inst #1840 = SHSUB16
	{ 5, OperandInfo315 },	// Inst #1841 = SHSUB8
	{ 3, OperandInfo202 },	// Inst #1842 = SMC
	{ 6, OperandInfo318 },	// Inst #1843 = SMLABB
	{ 6, OperandInfo318 },	// Inst #1844 = SMLABT
	{ 6, OperandInfo318 },	// Inst #1845 = SMLAD
	{ 6, OperandInfo318 },	// Inst #1846 = SMLADX
	{ 9, OperandInfo319 },	// Inst #1847 = SMLAL
	{ 8, OperandInfo320 },	// Inst #1848 = SMLALBB
	{ 8, OperandInfo320 },	// Inst #1849 = SMLALBT
	{ 8, OperandInfo320 },	// Inst #1850 = SMLALD
	{ 8, OperandInfo320 },	// Inst #1851 = SMLALDX
	{ 8, OperandInfo320 },	// Inst #1852 = SMLALTB
	{ 8, OperandInfo320 },	// Inst #1853 = SMLALTT
	{ 6, OperandInfo318 },	// Inst #1854 = SMLATB
	{ 6, OperandInfo318 },	// Inst #1855 = SMLATT
	{ 6, OperandInfo318 },	// Inst #1856 = SMLAWB
	{ 6, OperandInfo318 },	// Inst #1857 = SMLAWT
	{ 6, OperandInfo318 },	// Inst #1858 = SMLSD
	{ 6, OperandInfo318 },	// Inst #1859 = SMLSDX
	{ 8, OperandInfo320 },	// Inst #1860 = SMLSLD
	{ 8, OperandInfo320 },	// Inst #1861 = SMLSLDX
	{ 6, OperandInfo229 },	// Inst #1862 = SMMLA
	{ 6, OperandInfo229 },	// Inst #1863 = SMMLAR
	{ 6, OperandInfo229 },	// Inst #1864 = SMMLS
	{ 6, OperandInfo229 },	// Inst #1865 = SMMLSR
	{ 5, OperandInfo47 },	// Inst #1866 = SMMUL
	{ 5, OperandInfo47 },	// Inst #1867 = SMMULR
	{ 5, OperandInfo315 },	// Inst #1868 = SMUAD
	{ 5, OperandInfo315 },	// Inst #1869 = SMUADX
	{ 5, OperandInfo47 },	// Inst #1870 = SMULBB
	{ 5, OperandInfo47 },	// Inst #1871 = SMULBT
	{ 7, OperandInfo321 },	// Inst #1872 = SMULL
	{ 5, OperandInfo47 },	// Inst #1873 = SMULTB
	{ 5, OperandInfo47 },	// Inst #1874 = SMULTT
	{ 5, OperandInfo47 },	// Inst #1875 = SMULWB
	{ 5, OperandInfo47 },	// Inst #1876 = SMULWT
	{ 5, OperandInfo315 },	// Inst #1877 = SMUSD
	{ 5, OperandInfo315 },	// Inst #1878 = SMUSDX
	{ 1, OperandInfo2 },	// Inst #1879 = SRSDA
	{ 1, OperandInfo2 },	// Inst #1880 = SRSDA_UPD
	{ 1, OperandInfo2 },	// Inst #1881 = SRSDB
	{ 1, OperandInfo2 },	// Inst #1882 = SRSDB_UPD
	{ 1, OperandInfo2 },	// Inst #1883 = SRSIA
	{ 1, OperandInfo2 },	// Inst #1884 = SRSIA_UPD
	{ 1, OperandInfo2 },	// Inst #1885 = SRSIB
	{ 1, OperandInfo2 },	// Inst #1886 = SRSIB_UPD
	{ 6, OperandInfo322 },	// Inst #1887 = SSAT
	{ 5, OperandInfo323 },	// Inst #1888 = SSAT16
	{ 5, OperandInfo315 },	// Inst #1889 = SSAX
	{ 5, OperandInfo315 },	// Inst #1890 = SSUB16
	{ 5, OperandInfo315 },	// Inst #1891 = SSUB8
	{ 4, OperandInfo208 },	// Inst #1892 = STC2L_OFFSET
	{ 4, OperandInfo209 },	// Inst #1893 = STC2L_OPTION
	{ 4, OperandInfo208 },	// Inst #1894 = STC2L_POST
	{ 5, OperandInfo210 },	// Inst #1895 = STC2L_PRE
	{ 4, OperandInfo208 },	// Inst #1896 = STC2_OFFSET
	{ 4, OperandInfo209 },	// Inst #1897 = STC2_OPTION
	{ 4, OperandInfo208 },	// Inst #1898 = STC2_POST
	{ 5, OperandInfo210 },	// Inst #1899 = STC2_PRE
	{ 6, OperandInfo211 },	// Inst #1900 = STCL_OFFSET
	{ 6, OperandInfo212 },	// Inst #1901 = STCL_OPTION
	{ 6, OperandInfo211 },	// Inst #1902 = STCL_POST
	{ 7, OperandInfo213 },	// Inst #1903 = STCL_PRE
	{ 6, OperandInfo211 },	// Inst #1904 = STC_OFFSET
	{ 6, OperandInfo212 },	// Inst #1905 = STC_OPTION
	{ 6, OperandInfo211 },	// Inst #1906 = STC_POST
	{ 7, OperandInfo213 },	// Inst #1907 = STC_PRE
	{ 4, OperandInfo67 },	// Inst #1908 = STL
	{ 4, OperandInfo67 },	// Inst #1909 = STLB
	{ 5, OperandInfo324 },	// Inst #1910 = STLEX
	{ 5, OperandInfo324 },	// Inst #1911 = STLEXB
	{ 5, OperandInfo325 },	// Inst #1912 = STLEXD
	{ 5, OperandInfo324 },	// Inst #1913 = STLEXH
	{ 4, OperandInfo67 },	// Inst #1914 = STLH
	{ 4, OperandInfo206 },	// Inst #1915 = STMDA
	{ 5, OperandInfo66 },	// Inst #1916 = STMDA_UPD
	{ 4, OperandInfo206 },	// Inst #1917 = STMDB
	{ 5, OperandInfo66 },	// Inst #1918 = STMDB_UPD
	{ 4, OperandInfo206 },	// Inst #1919 = STMIA
	{ 5, OperandInfo66 },	// Inst #1920 = STMIA_UPD
	{ 4, OperandInfo206 },	// Inst #1921 = STMIB
	{ 5, OperandInfo66 },	// Inst #1922 = STMIB_UPD
	{ 7, OperandInfo326 },	// Inst #1923 = STRBT_POST_IMM
	{ 7, OperandInfo326 },	// Inst #1924 = STRBT_POST_REG
	{ 7, OperandInfo327 },	// Inst #1925 = STRB_POST_IMM
	{ 7, OperandInfo327 },	// Inst #1926 = STRB_POST_REG
	{ 6, OperandInfo328 },	// Inst #1927 = STRB_PRE_IMM
	{ 7, OperandInfo327 },	// Inst #1928 = STRB_PRE_REG
	{ 5, OperandInfo216 },	// Inst #1929 = STRBi12
	{ 6, OperandInfo217 },	// Inst #1930 = STRBrs
	{ 7, OperandInfo218 },	// Inst #1931 = STRD
	{ 8, OperandInfo329 },	// Inst #1932 = STRD_POST
	{ 8, OperandInfo329 },	// Inst #1933 = STRD_PRE
	{ 5, OperandInfo324 },	// Inst #1934 = STREX
	{ 5, OperandInfo324 },	// Inst #1935 = STREXB
	{ 5, OperandInfo325 },	// Inst #1936 = STREXD
	{ 5, OperandInfo324 },	// Inst #1937 = STREXH
	{ 6, OperandInfo220 },	// Inst #1938 = STRH
	{ 6, OperandInfo330 },	// Inst #1939 = STRHTi
	{ 7, OperandInfo326 },	// Inst #1940 = STRHTr
	{ 7, OperandInfo331 },	// Inst #1941 = STRH_POST
	{ 7, OperandInfo331 },	// Inst #1942 = STRH_PRE
	{ 7, OperandInfo326 },	// Inst #1943 = STRT_POST_IMM
	{ 7, OperandInfo326 },	// Inst #1944 = STRT_POST_REG
	{ 7, OperandInfo327 },	// Inst #1945 = STR_POST_IMM
	{ 7, OperandInfo327 },	// Inst #1946 = STR_POST_REG
	{ 6, OperandInfo328 },	// Inst #1947 = STR_PRE_IMM
	{ 7, OperandInfo327 },	// Inst #1948 = STR_PRE_REG
	{ 5, OperandInfo87 },	// Inst #1949 = STRi12
	{ 6, OperandInfo223 },	// Inst #1950 = STRrs
	{ 6, OperandInfo51 },	// Inst #1951 = SUBri
	{ 6, OperandInfo153 },	// Inst #1952 = SUBrr
	{ 7, OperandInfo154 },	// Inst #1953 = SUBrsi
	{ 8, OperandInfo156 },	// Inst #1954 = SUBrsr
	{ 3, OperandInfo202 },	// Inst #1955 = SVC
	{ 5, OperandInfo332 },	// Inst #1956 = SWP
	{ 5, OperandInfo332 },	// Inst #1957 = SWPB
	{ 6, OperandInfo333 },	// Inst #1958 = SXTAB
	{ 6, OperandInfo333 },	// Inst #1959 = SXTAB16
	{ 6, OperandInfo333 },	// Inst #1960 = SXTAH
	{ 5, OperandInfo334 },	// Inst #1961 = SXTB
	{ 5, OperandInfo334 },	// Inst #1962 = SXTB16
	{ 5, OperandInfo334 },	// Inst #1963 = SXTH
	{ 4, OperandInfo68 },	// Inst #1964 = TEQri
	{ 4, OperandInfo197 },	// Inst #1965 = TEQrr
	{ 5, OperandInfo198 },	// Inst #1966 = TEQrsi
	{ 6, OperandInfo199 },	// Inst #1967 = TEQrsr
	{ 0, 0 },		// Inst #1968 = TRAP
	{ 0, 0 },		// Inst #1969 = TRAPNaCl
	{ 1, OperandInfo2 },	// Inst #1970 = TSB
	{ 4, OperandInfo68 },	// Inst #1971 = TSTri
	{ 4, OperandInfo197 },	// Inst #1972 = TSTrr
	{ 5, OperandInfo198 },	// Inst #1973 = TSTrsi
	{ 6, OperandInfo199 },	// Inst #1974 = TSTrsr
	{ 5, OperandInfo315 },	// Inst #1975 = UADD16
	{ 5, OperandInfo315 },	// Inst #1976 = UADD8
	{ 5, OperandInfo315 },	// Inst #1977 = UASX
	{ 6, OperandInfo317 },	// Inst #1978 = UBFX
	{ 1, OperandInfo2 },	// Inst #1979 = UDF
	{ 5, OperandInfo47 },	// Inst #1980 = UDIV
	{ 5, OperandInfo315 },	// Inst #1981 = UHADD16
	{ 5, OperandInfo315 },	// Inst #1982 = UHADD8
	{ 5, OperandInfo315 },	// Inst #1983 = UHASX
	{ 5, OperandInfo315 },	// Inst #1984 = UHSAX
	{ 5, OperandInfo315 },	// Inst #1985 = UHSUB16
	{ 5, OperandInfo315 },	// Inst #1986 = UHSUB8
	{ 8, OperandInfo335 },	// Inst #1987 = UMAAL
	{ 9, OperandInfo319 },	// Inst #1988 = UMLAL
	{ 7, OperandInfo321 },	// Inst #1989 = UMULL
	{ 5, OperandInfo315 },	// Inst #1990 = UQADD16
	{ 5, OperandInfo315 },	// Inst #1991 = UQADD8
	{ 5, OperandInfo315 },	// Inst #1992 = UQASX
	{ 5, OperandInfo315 },	// Inst #1993 = UQSAX
	{ 5, OperandInfo315 },	// Inst #1994 = UQSUB16
	{ 5, OperandInfo315 },	// Inst #1995 = UQSUB8
	{ 5, OperandInfo47 },	// Inst #1996 = USAD8
	{ 6, OperandInfo229 },	// Inst #1997 = USADA8
	{ 6, OperandInfo322 },	// Inst #1998 = USAT
	{ 5, OperandInfo323 },	// Inst #1999 = USAT16
	{ 5, OperandInfo315 },	// Inst #2000 = USAX
	{ 5, OperandInfo315 },	// Inst #2001 = USUB16
	{ 5, OperandInfo315 },	// Inst #2002 = USUB8
	{ 6, OperandInfo333 },	// Inst #2003 = UXTAB
	{ 6, OperandInfo333 },	// Inst #2004 = UXTAB16
	{ 6, OperandInfo333 },	// Inst #2005 = UXTAH
	{ 5, OperandInfo334 },	// Inst #2006 = UXTB
	{ 5, OperandInfo334 },	// Inst #2007 = UXTB16
	{ 5, OperandInfo334 },	// Inst #2008 = UXTH
	{ 6, OperandInfo336 },	// Inst #2009 = VABALsv2i64
	{ 6, OperandInfo336 },	// Inst #2010 = VABALsv4i32
	{ 6, OperandInfo336 },	// Inst #2011 = VABALsv8i16
	{ 6, OperandInfo336 },	// Inst #2012 = VABALuv2i64
	{ 6, OperandInfo336 },	// Inst #2013 = VABALuv4i32
	{ 6, OperandInfo336 },	// Inst #2014 = VABALuv8i16
	{ 6, OperandInfo337 },	// Inst #2015 = VABAsv16i8
	{ 6, OperandInfo338 },	// Inst #2016 = VABAsv2i32
	{ 6, OperandInfo338 },	// Inst #2017 = VABAsv4i16
	{ 6, OperandInfo337 },	// Inst #2018 = VABAsv4i32
	{ 6, OperandInfo337 },	// Inst #2019 = VABAsv8i16
	{ 6, OperandInfo338 },	// Inst #2020 = VABAsv8i8
	{ 6, OperandInfo337 },	// Inst #2021 = VABAuv16i8
	{ 6, OperandInfo338 },	// Inst #2022 = VABAuv2i32
	{ 6, OperandInfo338 },	// Inst #2023 = VABAuv4i16
	{ 6, OperandInfo337 },	// Inst #2024 = VABAuv4i32
	{ 6, OperandInfo337 },	// Inst #2025 = VABAuv8i16
	{ 6, OperandInfo338 },	// Inst #2026 = VABAuv8i8
	{ 5, OperandInfo339 },	// Inst #2027 = VABDLsv2i64
	{ 5, OperandInfo339 },	// Inst #2028 = VABDLsv4i32
	{ 5, OperandInfo339 },	// Inst #2029 = VABDLsv8i16
	{ 5, OperandInfo339 },	// Inst #2030 = VABDLuv2i64
	{ 5, OperandInfo339 },	// Inst #2031 = VABDLuv4i32
	{ 5, OperandInfo339 },	// Inst #2032 = VABDLuv8i16
	{ 5, OperandInfo340 },	// Inst #2033 = VABDfd
	{ 5, OperandInfo341 },	// Inst #2034 = VABDfq
	{ 5, OperandInfo340 },	// Inst #2035 = VABDhd
	{ 5, OperandInfo341 },	// Inst #2036 = VABDhq
	{ 5, OperandInfo341 },	// Inst #2037 = VABDsv16i8
	{ 5, OperandInfo340 },	// Inst #2038 = VABDsv2i32
	{ 5, OperandInfo340 },	// Inst #2039 = VABDsv4i16
	{ 5, OperandInfo341 },	// Inst #2040 = VABDsv4i32
	{ 5, OperandInfo341 },	// Inst #2041 = VABDsv8i16
	{ 5, OperandInfo340 },	// Inst #2042 = VABDsv8i8
	{ 5, OperandInfo341 },	// Inst #2043 = VABDuv16i8
	{ 5, OperandInfo340 },	// Inst #2044 = VABDuv2i32
	{ 5, OperandInfo340 },	// Inst #2045 = VABDuv4i16
	{ 5, OperandInfo341 },	// Inst #2046 = VABDuv4i32
	{ 5, OperandInfo341 },	// Inst #2047 = VABDuv8i16
	{ 5, OperandInfo340 },	// Inst #2048 = VABDuv8i8
	{ 4, OperandInfo342 },	// Inst #2049 = VABSD
	{ 4, OperandInfo343 },	// Inst #2050 = VABSH
	{ 4, OperandInfo344 },	// Inst #2051 = VABSS
	{ 4, OperandInfo342 },	// Inst #2052 = VABSfd
	{ 4, OperandInfo345 },	// Inst #2053 = VABSfq
	{ 4, OperandInfo342 },	// Inst #2054 = VABShd
	{ 4, OperandInfo345 },	// Inst #2055 = VABShq
	{ 4, OperandInfo345 },	// Inst #2056 = VABSv16i8
	{ 4, OperandInfo342 },	// Inst #2057 = VABSv2i32
	{ 4, OperandInfo342 },	// Inst #2058 = VABSv4i16
	{ 4, OperandInfo345 },	// Inst #2059 = VABSv4i32
	{ 4, OperandInfo345 },	// Inst #2060 = VABSv8i16
	{ 4, OperandInfo342 },	// Inst #2061 = VABSv8i8
	{ 5, OperandInfo340 },	// Inst #2062 = VACGEfd
	{ 5, OperandInfo341 },	// Inst #2063 = VACGEfq
	{ 5, OperandInfo340 },	// Inst #2064 = VACGEhd
	{ 5, OperandInfo341 },	// Inst #2065 = VACGEhq
	{ 5, OperandInfo340 },	// Inst #2066 = VACGTfd
	{ 5, OperandInfo341 },	// Inst #2067 = VACGTfq
	{ 5, OperandInfo340 },	// Inst #2068 = VACGThd
	{ 5, OperandInfo341 },	// Inst #2069 = VACGThq
	{ 5, OperandInfo340 },	// Inst #2070 = VADDD
	{ 5, OperandInfo346 },	// Inst #2071 = VADDH
	{ 5, OperandInfo347 },	// Inst #2072 = VADDHNv2i32
	{ 5, OperandInfo347 },	// Inst #2073 = VADDHNv4i16
	{ 5, OperandInfo347 },	// Inst #2074 = VADDHNv8i8
	{ 5, OperandInfo339 },	// Inst #2075 = VADDLsv2i64
	{ 5, OperandInfo339 },	// Inst #2076 = VADDLsv4i32
	{ 5, OperandInfo339 },	// Inst #2077 = VADDLsv8i16
	{ 5, OperandInfo339 },	// Inst #2078 = VADDLuv2i64
	{ 5, OperandInfo339 },	// Inst #2079 = VADDLuv4i32
	{ 5, OperandInfo339 },	// Inst #2080 = VADDLuv8i16
	{ 5, OperandInfo348 },	// Inst #2081 = VADDS
	{ 5, OperandInfo349 },	// Inst #2082 = VADDWsv2i64
	{ 5, OperandInfo349 },	// Inst #2083 = VADDWsv4i32
	{ 5, OperandInfo349 },	// Inst #2084 = VADDWsv8i16
	{ 5, OperandInfo349 },	// Inst #2085 = VADDWuv2i64
	{ 5, OperandInfo349 },	// Inst #2086 = VADDWuv4i32
	{ 5, OperandInfo349 },	// Inst #2087 = VADDWuv8i16
	{ 5, OperandInfo340 },	// Inst #2088 = VADDfd
	{ 5, OperandInfo341 },	// Inst #2089 = VADDfq
	{ 5, OperandInfo340 },	// Inst #2090 = VADDhd
	{ 5, OperandInfo341 },	// Inst #2091 = VADDhq
	{ 5, OperandInfo341 },	// Inst #2092 = VADDv16i8
	{ 5, OperandInfo340 },	// Inst #2093 = VADDv1i64
	{ 5, OperandInfo340 },	// Inst #2094 = VADDv2i32
	{ 5, OperandInfo341 },	// Inst #2095 = VADDv2i64
	{ 5, OperandInfo340 },	// Inst #2096 = VADDv4i16
	{ 5, OperandInfo341 },	// Inst #2097 = VADDv4i32
	{ 5, OperandInfo341 },	// Inst #2098 = VADDv8i16
	{ 5, OperandInfo340 },	// Inst #2099 = VADDv8i8
	{ 5, OperandInfo340 },	// Inst #2100 = VANDd
	{ 5, OperandInfo341 },	// Inst #2101 = VANDq
	{ 4, OperandInfo162 },	// Inst #2102 = VBF16MALBQ
	{ 5, OperandInfo350 },	// Inst #2103 = VBF16MALBQI
	{ 4, OperandInfo162 },	// Inst #2104 = VBF16MALTQ
	{ 5, OperandInfo350 },	// Inst #2105 = VBF16MALTQI
	{ 5, OperandInfo340 },	// Inst #2106 = VBICd
	{ 5, OperandInfo351 },	// Inst #2107 = VBICiv2i32
	{ 5, OperandInfo351 },	// Inst #2108 = VBICiv4i16
	{ 5, OperandInfo352 },	// Inst #2109 = VBICiv4i32
	{ 5, OperandInfo352 },	// Inst #2110 = VBICiv8i16
	{ 5, OperandInfo341 },	// Inst #2111 = VBICq
	{ 6, OperandInfo338 },	// Inst #2112 = VBIFd
	{ 6, OperandInfo337 },	// Inst #2113 = VBIFq
	{ 6, OperandInfo338 },	// Inst #2114 = VBITd
	{ 6, OperandInfo337 },	// Inst #2115 = VBITq
	{ 6, OperandInfo338 },	// Inst #2116 = VBSLd
	{ 6, OperandInfo337 },	// Inst #2117 = VBSLq
	{ 6, OperandInfo353 },	// Inst #2118 = VBSPd
	{ 6, OperandInfo354 },	// Inst #2119 = VBSPq
	{ 4, OperandInfo355 },	// Inst #2120 = VCADDv2f32
	{ 4, OperandInfo355 },	// Inst #2121 = VCADDv4f16
	{ 4, OperandInfo356 },	// Inst #2122 = VCADDv4f32
	{ 4, OperandInfo356 },	// Inst #2123 = VCADDv8f16
	{ 5, OperandInfo340 },	// Inst #2124 = VCEQfd
	{ 5, OperandInfo341 },	// Inst #2125 = VCEQfq
	{ 5, OperandInfo340 },	// Inst #2126 = VCEQhd
	{ 5, OperandInfo341 },	// Inst #2127 = VCEQhq
	{ 5, OperandInfo341 },	// Inst #2128 = VCEQv16i8
	{ 5, OperandInfo340 },	// Inst #2129 = VCEQv2i32
	{ 5, OperandInfo340 },	// Inst #2130 = VCEQv4i16
	{ 5, OperandInfo341 },	// Inst #2131 = VCEQv4i32
	{ 5, OperandInfo341 },	// Inst #2132 = VCEQv8i16
	{ 5, OperandInfo340 },	// Inst #2133 = VCEQv8i8
	{ 4, OperandInfo345 },	// Inst #2134 = VCEQzv16i8
	{ 4, OperandInfo342 },	// Inst #2135 = VCEQzv2f32
	{ 4, OperandInfo342 },	// Inst #2136 = VCEQzv2i32
	{ 4, OperandInfo342 },	// Inst #2137 = VCEQzv4f16
	{ 4, OperandInfo345 },	// Inst #2138 = VCEQzv4f32
	{ 4, OperandInfo342 },	// Inst #2139 = VCEQzv4i16
	{ 4, OperandInfo345 },	// Inst #2140 = VCEQzv4i32
	{ 4, OperandInfo345 },	// Inst #2141 = VCEQzv8f16
	{ 4, OperandInfo345 },	// Inst #2142 = VCEQzv8i16
	{ 4, OperandInfo342 },	// Inst #2143 = VCEQzv8i8
	{ 5, OperandInfo340 },	// Inst #2144 = VCGEfd
	{ 5, OperandInfo341 },	// Inst #2145 = VCGEfq
	{ 5, OperandInfo340 },	// Inst #2146 = VCGEhd
	{ 5, OperandInfo341 },	// Inst #2147 = VCGEhq
	{ 5, OperandInfo341 },	// Inst #2148 = VCGEsv16i8
	{ 5, OperandInfo340 },	// Inst #2149 = VCGEsv2i32
	{ 5, OperandInfo340 },	// Inst #2150 = VCGEsv4i16
	{ 5, OperandInfo341 },	// Inst #2151 = VCGEsv4i32
	{ 5, OperandInfo341 },	// Inst #2152 = VCGEsv8i16
	{ 5, OperandInfo340 },	// Inst #2153 = VCGEsv8i8
	{ 5, OperandInfo341 },	// Inst #2154 = VCGEuv16i8
	{ 5, OperandInfo340 },	// Inst #2155 = VCGEuv2i32
	{ 5, OperandInfo340 },	// Inst #2156 = VCGEuv4i16
	{ 5, OperandInfo341 },	// Inst #2157 = VCGEuv4i32
	{ 5, OperandInfo341 },	// Inst #2158 = VCGEuv8i16
	{ 5, OperandInfo340 },	// Inst #2159 = VCGEuv8i8
	{ 4, OperandInfo345 },	// Inst #2160 = VCGEzv16i8
	{ 4, OperandInfo342 },	// Inst #2161 = VCGEzv2f32
	{ 4, OperandInfo342 },	// Inst #2162 = VCGEzv2i32
	{ 4, OperandInfo342 },	// Inst #2163 = VCGEzv4f16
	{ 4, OperandInfo345 },	// Inst #2164 = VCGEzv4f32
	{ 4, OperandInfo342 },	// Inst #2165 = VCGEzv4i16
	{ 4, OperandInfo345 },	// Inst #2166 = VCGEzv4i32
	{ 4, OperandInfo345 },	// Inst #2167 = VCGEzv8f16
	{ 4, OperandInfo345 },	// Inst #2168 = VCGEzv8i16
	{ 4, OperandInfo342 },	// Inst #2169 = VCGEzv8i8
	{ 5, OperandInfo340 },	// Inst #2170 = VCGTfd
	{ 5, OperandInfo341 },	// Inst #2171 = VCGTfq
	{ 5, OperandInfo340 },	// Inst #2172 = VCGThd
	{ 5, OperandInfo341 },	// Inst #2173 = VCGThq
	{ 5, OperandInfo341 },	// Inst #2174 = VCGTsv16i8
	{ 5, OperandInfo340 },	// Inst #2175 = VCGTsv2i32
	{ 5, OperandInfo340 },	// Inst #2176 = VCGTsv4i16
	{ 5, OperandInfo341 },	// Inst #2177 = VCGTsv4i32
	{ 5, OperandInfo341 },	// Inst #2178 = VCGTsv8i16
	{ 5, OperandInfo340 },	// Inst #2179 = VCGTsv8i8
	{ 5, OperandInfo341 },	// Inst #2180 = VCGTuv16i8
	{ 5, OperandInfo340 },	// Inst #2181 = VCGTuv2i32
	{ 5, OperandInfo340 },	// Inst #2182 = VCGTuv4i16
	{ 5, OperandInfo341 },	// Inst #2183 = VCGTuv4i32
	{ 5, OperandInfo341 },	// Inst #2184 = VCGTuv8i16
	{ 5, OperandInfo340 },	// Inst #2185 = VCGTuv8i8
	{ 4, OperandInfo345 },	// Inst #2186 = VCGTzv16i8
	{ 4, OperandInfo342 },	// Inst #2187 = VCGTzv2f32
	{ 4, OperandInfo342 },	// Inst #2188 = VCGTzv2i32
	{ 4, OperandInfo342 },	// Inst #2189 = VCGTzv4f16
	{ 4, OperandInfo345 },	// Inst #2190 = VCGTzv4f32
	{ 4, OperandInfo342 },	// Inst #2191 = VCGTzv4i16
	{ 4, OperandInfo345 },	// Inst #2192 = VCGTzv4i32
	{ 4, OperandInfo345 },	// Inst #2193 = VCGTzv8f16
	{ 4, OperandInfo345 },	// Inst #2194 = VCGTzv8i16
	{ 4, OperandInfo342 },	// Inst #2195 = VCGTzv8i8
	{ 4, OperandInfo345 },	// Inst #2196 = VCLEzv16i8
	{ 4, OperandInfo342 },	// Inst #2197 = VCLEzv2f32
	{ 4, OperandInfo342 },	// Inst #2198 = VCLEzv2i32
	{ 4, OperandInfo342 },	// Inst #2199 = VCLEzv4f16
	{ 4, OperandInfo345 },	// Inst #2200 = VCLEzv4f32
	{ 4, OperandInfo342 },	// Inst #2201 = VCLEzv4i16
	{ 4, OperandInfo345 },	// Inst #2202 = VCLEzv4i32
	{ 4, OperandInfo345 },	// Inst #2203 = VCLEzv8f16
	{ 4, OperandInfo345 },	// Inst #2204 = VCLEzv8i16
	{ 4, OperandInfo342 },	// Inst #2205 = VCLEzv8i8
	{ 4, OperandInfo345 },	// Inst #2206 = VCLSv16i8
	{ 4, OperandInfo342 },	// Inst #2207 = VCLSv2i32
	{ 4, OperandInfo342 },	// Inst #2208 = VCLSv4i16
	{ 4, OperandInfo345 },	// Inst #2209 = VCLSv4i32
	{ 4, OperandInfo345 },	// Inst #2210 = VCLSv8i16
	{ 4, OperandInfo342 },	// Inst #2211 = VCLSv8i8
	{ 4, OperandInfo345 },	// Inst #2212 = VCLTzv16i8
	{ 4, OperandInfo342 },	// Inst #2213 = VCLTzv2f32
	{ 4, OperandInfo342 },	// Inst #2214 = VCLTzv2i32
	{ 4, OperandInfo342 },	// Inst #2215 = VCLTzv4f16
	{ 4, OperandInfo345 },	// Inst #2216 = VCLTzv4f32
	{ 4, OperandInfo342 },	// Inst #2217 = VCLTzv4i16
	{ 4, OperandInfo345 },	// Inst #2218 = VCLTzv4i32
	{ 4, OperandInfo345 },	// Inst #2219 = VCLTzv8f16
	{ 4, OperandInfo345 },	// Inst #2220 = VCLTzv8i16
	{ 4, OperandInfo342 },	// Inst #2221 = VCLTzv8i8
	{ 4, OperandInfo345 },	// Inst #2222 = VCLZv16i8
	{ 4, OperandInfo342 },	// Inst #2223 = VCLZv2i32
	{ 4, OperandInfo342 },	// Inst #2224 = VCLZv4i16
	{ 4, OperandInfo345 },	// Inst #2225 = VCLZv4i32
	{ 4, OperandInfo345 },	// Inst #2226 = VCLZv8i16
	{ 4, OperandInfo342 },	// Inst #2227 = VCLZv8i8
	{ 5, OperandInfo357 },	// Inst #2228 = VCMLAv2f32
	{ 6, OperandInfo358 },	// Inst #2229 = VCMLAv2f32_indexed
	{ 5, OperandInfo357 },	// Inst #2230 = VCMLAv4f16
	{ 6, OperandInfo359 },	// Inst #2231 = VCMLAv4f16_indexed
	{ 5, OperandInfo360 },	// Inst #2232 = VCMLAv4f32
	{ 6, OperandInfo361 },	// Inst #2233 = VCMLAv4f32_indexed
	{ 5, OperandInfo360 },	// Inst #2234 = VCMLAv8f16
	{ 6, OperandInfo362 },	// Inst #2235 = VCMLAv8f16_indexed
	{ 4, OperandInfo342 },	// Inst #2236 = VCMPD
	{ 4, OperandInfo342 },	// Inst #2237 = VCMPED
	{ 4, OperandInfo343 },	// Inst #2238 = VCMPEH
	{ 4, OperandInfo344 },	// Inst #2239 = VCMPES
	{ 3, OperandInfo363 },	// Inst #2240 = VCMPEZD
	{ 3, OperandInfo364 },	// Inst #2241 = VCMPEZH
	{ 3, OperandInfo365 },	// Inst #2242 = VCMPEZS
	{ 4, OperandInfo343 },	// Inst #2243 = VCMPH
	{ 4, OperandInfo344 },	// Inst #2244 = VCMPS
	{ 3, OperandInfo363 },	// Inst #2245 = VCMPZD
	{ 3, OperandInfo364 },	// Inst #2246 = VCMPZH
	{ 3, OperandInfo365 },	// Inst #2247 = VCMPZS
	{ 4, OperandInfo342 },	// Inst #2248 = VCNTd
	{ 4, OperandInfo345 },	// Inst #2249 = VCNTq
	{ 2, OperandInfo366 },	// Inst #2250 = VCVTANSDf
	{ 2, OperandInfo366 },	// Inst #2251 = VCVTANSDh
	{ 2, OperandInfo158 },	// Inst #2252 = VCVTANSQf
	{ 2, OperandInfo158 },	// Inst #2253 = VCVTANSQh
	{ 2, OperandInfo366 },	// Inst #2254 = VCVTANUDf
	{ 2, OperandInfo366 },	// Inst #2255 = VCVTANUDh
	{ 2, OperandInfo158 },	// Inst #2256 = VCVTANUQf
	{ 2, OperandInfo158 },	// Inst #2257 = VCVTANUQh
	{ 2, OperandInfo367 },	// Inst #2258 = VCVTASD
	{ 2, OperandInfo368 },	// Inst #2259 = VCVTASH
	{ 2, OperandInfo369 },	// Inst #2260 = VCVTASS
	{ 2, OperandInfo367 },	// Inst #2261 = VCVTAUD
	{ 2, OperandInfo368 },	// Inst #2262 = VCVTAUH
	{ 2, OperandInfo369 },	// Inst #2263 = VCVTAUS
	{ 5, OperandInfo370 },	// Inst #2264 = VCVTBDH
	{ 4, OperandInfo371 },	// Inst #2265 = VCVTBHD
	{ 4, OperandInfo344 },	// Inst #2266 = VCVTBHS
	{ 5, OperandInfo105 },	// Inst #2267 = VCVTBSH
	{ 4, OperandInfo371 },	// Inst #2268 = VCVTDS
	{ 2, OperandInfo366 },	// Inst #2269 = VCVTMNSDf
	{ 2, OperandInfo366 },	// Inst #2270 = VCVTMNSDh
	{ 2, OperandInfo158 },	// Inst #2271 = VCVTMNSQf
	{ 2, OperandInfo158 },	// Inst #2272 = VCVTMNSQh
	{ 2, OperandInfo366 },	// Inst #2273 = VCVTMNUDf
	{ 2, OperandInfo366 },	// Inst #2274 = VCVTMNUDh
	{ 2, OperandInfo158 },	// Inst #2275 = VCVTMNUQf
	{ 2, OperandInfo158 },	// Inst #2276 = VCVTMNUQh
	{ 2, OperandInfo367 },	// Inst #2277 = VCVTMSD
	{ 2, OperandInfo368 },	// Inst #2278 = VCVTMSH
	{ 2, OperandInfo369 },	// Inst #2279 = VCVTMSS
	{ 2, OperandInfo367 },	// Inst #2280 = VCVTMUD
	{ 2, OperandInfo368 },	// Inst #2281 = VCVTMUH
	{ 2, OperandInfo369 },	// Inst #2282 = VCVTMUS
	{ 2, OperandInfo366 },	// Inst #2283 = VCVTNNSDf
	{ 2, OperandInfo366 },	// Inst #2284 = VCVTNNSDh
	{ 2, OperandInfo158 },	// Inst #2285 = VCVTNNSQf
	{ 2, OperandInfo158 },	// Inst #2286 = VCVTNNSQh
	{ 2, OperandInfo366 },	// Inst #2287 = VCVTNNUDf
	{ 2, OperandInfo366 },	// Inst #2288 = VCVTNNUDh
	{ 2, OperandInfo158 },	// Inst #2289 = VCVTNNUQf
	{ 2, OperandInfo158 },	// Inst #2290 = VCVTNNUQh
	{ 2, OperandInfo367 },	// Inst #2291 = VCVTNSD
	{ 2, OperandInfo368 },	// Inst #2292 = VCVTNSH
	{ 2, OperandInfo369 },	// Inst #2293 = VCVTNSS
	{ 2, OperandInfo367 },	// Inst #2294 = VCVTNUD
	{ 2, OperandInfo368 },	// Inst #2295 = VCVTNUH
	{ 2, OperandInfo369 },	// Inst #2296 = VCVTNUS
	{ 2, OperandInfo366 },	// Inst #2297 = VCVTPNSDf
	{ 2, OperandInfo366 },	// Inst #2298 = VCVTPNSDh
	{ 2, OperandInfo158 },	// Inst #2299 = VCVTPNSQf
	{ 2, OperandInfo158 },	// Inst #2300 = VCVTPNSQh
	{ 2, OperandInfo366 },	// Inst #2301 = VCVTPNUDf
	{ 2, OperandInfo366 },	// Inst #2302 = VCVTPNUDh
	{ 2, OperandInfo158 },	// Inst #2303 = VCVTPNUQf
	{ 2, OperandInfo158 },	// Inst #2304 = VCVTPNUQh
	{ 2, OperandInfo367 },	// Inst #2305 = VCVTPSD
	{ 2, OperandInfo368 },	// Inst #2306 = VCVTPSH
	{ 2, OperandInfo369 },	// Inst #2307 = VCVTPSS
	{ 2, OperandInfo367 },	// Inst #2308 = VCVTPUD
	{ 2, OperandInfo368 },	// Inst #2309 = VCVTPUH
	{ 2, OperandInfo369 },	// Inst #2310 = VCVTPUS
	{ 4, OperandInfo372 },	// Inst #2311 = VCVTSD
	{ 5, OperandInfo370 },	// Inst #2312 = VCVTTDH
	{ 4, OperandInfo371 },	// Inst #2313 = VCVTTHD
	{ 4, OperandInfo344 },	// Inst #2314 = VCVTTHS
	{ 5, OperandInfo105 },	// Inst #2315 = VCVTTSH
	{ 4, OperandInfo163 },	// Inst #2316 = VCVTf2h
	{ 4, OperandInfo342 },	// Inst #2317 = VCVTf2sd
	{ 4, OperandInfo345 },	// Inst #2318 = VCVTf2sq
	{ 4, OperandInfo342 },	// Inst #2319 = VCVTf2ud
	{ 4, OperandInfo345 },	// Inst #2320 = VCVTf2uq
	{ 5, OperandInfo373 },	// Inst #2321 = VCVTf2xsd
	{ 5, OperandInfo374 },	// Inst #2322 = VCVTf2xsq
	{ 5, OperandInfo373 },	// Inst #2323 = VCVTf2xud
	{ 5, OperandInfo374 },	// Inst #2324 = VCVTf2xuq
	{ 4, OperandInfo375 },	// Inst #2325 = VCVTh2f
	{ 4, OperandInfo342 },	// Inst #2326 = VCVTh2sd
	{ 4, OperandInfo345 },	// Inst #2327 = VCVTh2sq
	{ 4, OperandInfo342 },	// Inst #2328 = VCVTh2ud
	{ 4, OperandInfo345 },	// Inst #2329 = VCVTh2uq
	{ 5, OperandInfo373 },	// Inst #2330 = VCVTh2xsd
	{ 5, OperandInfo374 },	// Inst #2331 = VCVTh2xsq
	{ 5, OperandInfo373 },	// Inst #2332 = VCVTh2xud
	{ 5, OperandInfo374 },	// Inst #2333 = VCVTh2xuq
	{ 4, OperandInfo342 },	// Inst #2334 = VCVTs2fd
	{ 4, OperandInfo345 },	// Inst #2335 = VCVTs2fq
	{ 4, OperandInfo342 },	// Inst #2336 = VCVTs2hd
	{ 4, OperandInfo345 },	// Inst #2337 = VCVTs2hq
	{ 4, OperandInfo342 },	// Inst #2338 = VCVTu2fd
	{ 4, OperandInfo345 },	// Inst #2339 = VCVTu2fq
	{ 4, OperandInfo342 },	// Inst #2340 = VCVTu2hd
	{ 4, OperandInfo345 },	// Inst #2341 = VCVTu2hq
	{ 5, OperandInfo373 },	// Inst #2342 = VCVTxs2fd
	{ 5, OperandInfo374 },	// Inst #2343 = VCVTxs2fq
	{ 5, OperandInfo373 },	// Inst #2344 = VCVTxs2hd
	{ 5, OperandInfo374 },	// Inst #2345 = VCVTxs2hq
	{ 5, OperandInfo373 },	// Inst #2346 = VCVTxu2fd
	{ 5, OperandInfo374 },	// Inst #2347 = VCVTxu2fq
	{ 5, OperandInfo373 },	// Inst #2348 = VCVTxu2hd
	{ 5, OperandInfo374 },	// Inst #2349 = VCVTxu2hq
	{ 5, OperandInfo340 },	// Inst #2350 = VDIVD
	{ 5, OperandInfo346 },	// Inst #2351 = VDIVH
	{ 5, OperandInfo348 },	// Inst #2352 = VDIVS
	{ 4, OperandInfo376 },	// Inst #2353 = VDUP16d
	{ 4, OperandInfo377 },	// Inst #2354 = VDUP16q
	{ 4, OperandInfo376 },	// Inst #2355 = VDUP32d
	{ 4, OperandInfo377 },	// Inst #2356 = VDUP32q
	{ 4, OperandInfo376 },	// Inst #2357 = VDUP8d
	{ 4, OperandInfo377 },	// Inst #2358 = VDUP8q
	{ 5, OperandInfo373 },	// Inst #2359 = VDUPLN16d
	{ 5, OperandInfo378 },	// Inst #2360 = VDUPLN16q
	{ 5, OperandInfo373 },	// Inst #2361 = VDUPLN32d
	{ 5, OperandInfo378 },	// Inst #2362 = VDUPLN32q
	{ 5, OperandInfo373 },	// Inst #2363 = VDUPLN8d
	{ 5, OperandInfo378 },	// Inst #2364 = VDUPLN8q
	{ 5, OperandInfo340 },	// Inst #2365 = VEORd
	{ 5, OperandInfo341 },	// Inst #2366 = VEORq
	{ 6, OperandInfo379 },	// Inst #2367 = VEXTd16
	{ 6, OperandInfo379 },	// Inst #2368 = VEXTd32
	{ 6, OperandInfo379 },	// Inst #2369 = VEXTd8
	{ 6, OperandInfo380 },	// Inst #2370 = VEXTq16
	{ 6, OperandInfo380 },	// Inst #2371 = VEXTq32
	{ 6, OperandInfo380 },	// Inst #2372 = VEXTq64
	{ 6, OperandInfo380 },	// Inst #2373 = VEXTq8
	{ 6, OperandInfo338 },	// Inst #2374 = VFMAD
	{ 6, OperandInfo381 },	// Inst #2375 = VFMAH
	{ 3, OperandInfo382 },	// Inst #2376 = VFMALD
	{ 4, OperandInfo383 },	// Inst #2377 = VFMALDI
	{ 3, OperandInfo384 },	// Inst #2378 = VFMALQ
	{ 4, OperandInfo385 },	// Inst #2379 = VFMALQI
	{ 6, OperandInfo386 },	// Inst #2380 = VFMAS
	{ 6, OperandInfo338 },	// Inst #2381 = VFMAfd
	{ 6, OperandInfo337 },	// Inst #2382 = VFMAfq
	{ 6, OperandInfo338 },	// Inst #2383 = VFMAhd
	{ 6, OperandInfo337 },	// Inst #2384 = VFMAhq
	{ 6, OperandInfo338 },	// Inst #2385 = VFMSD
	{ 6, OperandInfo381 },	// Inst #2386 = VFMSH
	{ 3, OperandInfo382 },	// Inst #2387 = VFMSLD
	{ 4, OperandInfo383 },	// Inst #2388 = VFMSLDI
	{ 3, OperandInfo384 },	// Inst #2389 = VFMSLQ
	{ 4, OperandInfo385 },	// Inst #2390 = VFMSLQI
	{ 6, OperandInfo386 },	// Inst #2391 = VFMSS
	{ 6, OperandInfo338 },	// Inst #2392 = VFMSfd
	{ 6, OperandInfo337 },	// Inst #2393 = VFMSfq
	{ 6, OperandInfo338 },	// Inst #2394 = VFMShd
	{ 6, OperandInfo337 },	// Inst #2395 = VFMShq
	{ 6, OperandInfo338 },	// Inst #2396 = VFNMAD
	{ 6, OperandInfo381 },	// Inst #2397 = VFNMAH
	{ 6, OperandInfo386 },	// Inst #2398 = VFNMAS
	{ 6, OperandInfo338 },	// Inst #2399 = VFNMSD
	{ 6, OperandInfo381 },	// Inst #2400 = VFNMSH
	{ 6, OperandInfo386 },	// Inst #2401 = VFNMSS
	{ 3, OperandInfo310 },	// Inst #2402 = VFP_VMAXNMD
	{ 3, OperandInfo387 },	// Inst #2403 = VFP_VMAXNMH
	{ 3, OperandInfo388 },	// Inst #2404 = VFP_VMAXNMS
	{ 3, OperandInfo310 },	// Inst #2405 = VFP_VMINNMD
	{ 3, OperandInfo387 },	// Inst #2406 = VFP_VMINNMH
	{ 3, OperandInfo388 },	// Inst #2407 = VFP_VMINNMS
	{ 5, OperandInfo389 },	// Inst #2408 = VGETLNi32
	{ 5, OperandInfo389 },	// Inst #2409 = VGETLNs16
	{ 5, OperandInfo389 },	// Inst #2410 = VGETLNs8
	{ 5, OperandInfo389 },	// Inst #2411 = VGETLNu16
	{ 5, OperandInfo389 },	// Inst #2412 = VGETLNu8
	{ 5, OperandInfo341 },	// Inst #2413 = VHADDsv16i8
	{ 5, OperandInfo340 },	// Inst #2414 = VHADDsv2i32
	{ 5, OperandInfo340 },	// Inst #2415 = VHADDsv4i16
	{ 5, OperandInfo341 },	// Inst #2416 = VHADDsv4i32
	{ 5, OperandInfo341 },	// Inst #2417 = VHADDsv8i16
	{ 5, OperandInfo340 },	// Inst #2418 = VHADDsv8i8
	{ 5, OperandInfo341 },	// Inst #2419 = VHADDuv16i8
	{ 5, OperandInfo340 },	// Inst #2420 = VHADDuv2i32
	{ 5, OperandInfo340 },	// Inst #2421 = VHADDuv4i16
	{ 5, OperandInfo341 },	// Inst #2422 = VHADDuv4i32
	{ 5, OperandInfo341 },	// Inst #2423 = VHADDuv8i16
	{ 5, OperandInfo340 },	// Inst #2424 = VHADDuv8i8
	{ 5, OperandInfo341 },	// Inst #2425 = VHSUBsv16i8
	{ 5, OperandInfo340 },	// Inst #2426 = VHSUBsv2i32
	{ 5, OperandInfo340 },	// Inst #2427 = VHSUBsv4i16
	{ 5, OperandInfo341 },	// Inst #2428 = VHSUBsv4i32
	{ 5, OperandInfo341 },	// Inst #2429 = VHSUBsv8i16
	{ 5, OperandInfo340 },	// Inst #2430 = VHSUBsv8i8
	{ 5, OperandInfo341 },	// Inst #2431 = VHSUBuv16i8
	{ 5, OperandInfo340 },	// Inst #2432 = VHSUBuv2i32
	{ 5, OperandInfo340 },	// Inst #2433 = VHSUBuv4i16
	{ 5, OperandInfo341 },	// Inst #2434 = VHSUBuv4i32
	{ 5, OperandInfo341 },	// Inst #2435 = VHSUBuv8i16
	{ 5, OperandInfo340 },	// Inst #2436 = VHSUBuv8i8
	{ 3, OperandInfo390 },	// Inst #2437 = VINSH
	{ 4, OperandInfo372 },	// Inst #2438 = VJCVT
	{ 5, OperandInfo99 },	// Inst #2439 = VLD1DUPd16
	{ 6, OperandInfo391 },	// Inst #2440 = VLD1DUPd16wb_fixed
	{ 7, OperandInfo392 },	// Inst #2441 = VLD1DUPd16wb_register
	{ 5, OperandInfo99 },	// Inst #2442 = VLD1DUPd32
	{ 6, OperandInfo391 },	// Inst #2443 = VLD1DUPd32wb_fixed
	{ 7, OperandInfo392 },	// Inst #2444 = VLD1DUPd32wb_register
	{ 5, OperandInfo99 },	// Inst #2445 = VLD1DUPd8
	{ 6, OperandInfo391 },	// Inst #2446 = VLD1DUPd8wb_fixed
	{ 7, OperandInfo392 },	// Inst #2447 = VLD1DUPd8wb_register
	{ 5, OperandInfo393 },	// Inst #2448 = VLD1DUPq16
	{ 6, OperandInfo394 },	// Inst #2449 = VLD1DUPq16wb_fixed
	{ 7, OperandInfo395 },	// Inst #2450 = VLD1DUPq16wb_register
	{ 5, OperandInfo393 },	// Inst #2451 = VLD1DUPq32
	{ 6, OperandInfo394 },	// Inst #2452 = VLD1DUPq32wb_fixed
	{ 7, OperandInfo395 },	// Inst #2453 = VLD1DUPq32wb_register
	{ 5, OperandInfo393 },	// Inst #2454 = VLD1DUPq8
	{ 6, OperandInfo394 },	// Inst #2455 = VLD1DUPq8wb_fixed
	{ 7, OperandInfo395 },	// Inst #2456 = VLD1DUPq8wb_register
	{ 7, OperandInfo396 },	// Inst #2457 = VLD1LNd16
	{ 9, OperandInfo397 },	// Inst #2458 = VLD1LNd16_UPD
	{ 7, OperandInfo396 },	// Inst #2459 = VLD1LNd32
	{ 9, OperandInfo397 },	// Inst #2460 = VLD1LNd32_UPD
	{ 7, OperandInfo396 },	// Inst #2461 = VLD1LNd8
	{ 9, OperandInfo397 },	// Inst #2462 = VLD1LNd8_UPD
	{ 7, OperandInfo398 },	// Inst #2463 = VLD1LNq16Pseudo
	{ 9, OperandInfo399 },	// Inst #2464 = VLD1LNq16Pseudo_UPD
	{ 7, OperandInfo398 },	// Inst #2465 = VLD1LNq32Pseudo
	{ 9, OperandInfo399 },	// Inst #2466 = VLD1LNq32Pseudo_UPD
	{ 7, OperandInfo398 },	// Inst #2467 = VLD1LNq8Pseudo
	{ 9, OperandInfo399 },	// Inst #2468 = VLD1LNq8Pseudo_UPD
	{ 5, OperandInfo99 },	// Inst #2469 = VLD1d16
	{ 5, OperandInfo99 },	// Inst #2470 = VLD1d16Q
	{ 5, OperandInfo400 },	// Inst #2471 = VLD1d16QPseudo
	{ 6, OperandInfo401 },	// Inst #2472 = VLD1d16QPseudoWB_fixed
	{ 7, OperandInfo402 },	// Inst #2473 = VLD1d16QPseudoWB_register
	{ 6, OperandInfo391 },	// Inst #2474 = VLD1d16Qwb_fixed
	{ 7, OperandInfo392 },	// Inst #2475 = VLD1d16Qwb_register
	{ 5, OperandInfo99 },	// Inst #2476 = VLD1d16T
	{ 5, OperandInfo400 },	// Inst #2477 = VLD1d16TPseudo
	{ 6, OperandInfo401 },	// Inst #2478 = VLD1d16TPseudoWB_fixed
	{ 7, OperandInfo402 },	// Inst #2479 = VLD1d16TPseudoWB_register
	{ 6, OperandInfo391 },	// Inst #2480 = VLD1d16Twb_fixed
	{ 7, OperandInfo392 },	// Inst #2481 = VLD1d16Twb_register
	{ 6, OperandInfo391 },	// Inst #2482 = VLD1d16wb_fixed
	{ 7, OperandInfo392 },	// Inst #2483 = VLD1d16wb_register
	{ 5, OperandInfo99 },	// Inst #2484 = VLD1d32
	{ 5, OperandInfo99 },	// Inst #2485 = VLD1d32Q
	{ 5, OperandInfo400 },	// Inst #2486 = VLD1d32QPseudo
	{ 6, OperandInfo401 },	// Inst #2487 = VLD1d32QPseudoWB_fixed
	{ 7, OperandInfo402 },	// Inst #2488 = VLD1d32QPseudoWB_register
	{ 6, OperandInfo391 },	// Inst #2489 = VLD1d32Qwb_fixed
	{ 7, OperandInfo392 },	// Inst #2490 = VLD1d32Qwb_register
	{ 5, OperandInfo99 },	// Inst #2491 = VLD1d32T
	{ 5, OperandInfo400 },	// Inst #2492 = VLD1d32TPseudo
	{ 6, OperandInfo401 },	// Inst #2493 = VLD1d32TPseudoWB_fixed
	{ 7, OperandInfo402 },	// Inst #2494 = VLD1d32TPseudoWB_register
	{ 6, OperandInfo391 },	// Inst #2495 = VLD1d32Twb_fixed
	{ 7, OperandInfo392 },	// Inst #2496 = VLD1d32Twb_register
	{ 6, OperandInfo391 },	// Inst #2497 = VLD1d32wb_fixed
	{ 7, OperandInfo392 },	// Inst #2498 = VLD1d32wb_register
	{ 5, OperandInfo99 },	// Inst #2499 = VLD1d64
	{ 5, OperandInfo99 },	// Inst #2500 = VLD1d64Q
	{ 5, OperandInfo400 },	// Inst #2501 = VLD1d64QPseudo
	{ 6, OperandInfo401 },	// Inst #2502 = VLD1d64QPseudoWB_fixed
	{ 7, OperandInfo402 },	// Inst #2503 = VLD1d64QPseudoWB_register
	{ 6, OperandInfo391 },	// Inst #2504 = VLD1d64Qwb_fixed
	{ 7, OperandInfo392 },	// Inst #2505 = VLD1d64Qwb_register
	{ 5, OperandInfo99 },	// Inst #2506 = VLD1d64T
	{ 5, OperandInfo400 },	// Inst #2507 = VLD1d64TPseudo
	{ 6, OperandInfo401 },	// Inst #2508 = VLD1d64TPseudoWB_fixed
	{ 7, OperandInfo402 },	// Inst #2509 = VLD1d64TPseudoWB_register
	{ 6, OperandInfo391 },	// Inst #2510 = VLD1d64Twb_fixed
	{ 7, OperandInfo392 },	// Inst #2511 = VLD1d64Twb_register
	{ 6, OperandInfo391 },	// Inst #2512 = VLD1d64wb_fixed
	{ 7, OperandInfo392 },	// Inst #2513 = VLD1d64wb_register
	{ 5, OperandInfo99 },	// Inst #2514 = VLD1d8
	{ 5, OperandInfo99 },	// Inst #2515 = VLD1d8Q
	{ 5, OperandInfo400 },	// Inst #2516 = VLD1d8QPseudo
	{ 6, OperandInfo401 },	// Inst #2517 = VLD1d8QPseudoWB_fixed
	{ 7, OperandInfo402 },	// Inst #2518 = VLD1d8QPseudoWB_register
	{ 6, OperandInfo391 },	// Inst #2519 = VLD1d8Qwb_fixed
	{ 7, OperandInfo392 },	// Inst #2520 = VLD1d8Qwb_register
	{ 5, OperandInfo99 },	// Inst #2521 = VLD1d8T
	{ 5, OperandInfo400 },	// Inst #2522 = VLD1d8TPseudo
	{ 6, OperandInfo401 },	// Inst #2523 = VLD1d8TPseudoWB_fixed
	{ 7, OperandInfo402 },	// Inst #2524 = VLD1d8TPseudoWB_register
	{ 6, OperandInfo391 },	// Inst #2525 = VLD1d8Twb_fixed
	{ 7, OperandInfo392 },	// Inst #2526 = VLD1d8Twb_register
	{ 6, OperandInfo391 },	// Inst #2527 = VLD1d8wb_fixed
	{ 7, OperandInfo392 },	// Inst #2528 = VLD1d8wb_register
	{ 5, OperandInfo393 },	// Inst #2529 = VLD1q16
	{ 6, OperandInfo403 },	// Inst #2530 = VLD1q16HighQPseudo
	{ 8, OperandInfo404 },	// Inst #2531 = VLD1q16HighQPseudo_UPD
	{ 6, OperandInfo403 },	// Inst #2532 = VLD1q16HighTPseudo
	{ 8, OperandInfo404 },	// Inst #2533 = VLD1q16HighTPseudo_UPD
	{ 8, OperandInfo404 },	// Inst #2534 = VLD1q16LowQPseudo_UPD
	{ 8, OperandInfo404 },	// Inst #2535 = VLD1q16LowTPseudo_UPD
	{ 6, OperandInfo394 },	// Inst #2536 = VLD1q16wb_fixed
	{ 7, OperandInfo395 },	// Inst #2537 = VLD1q16wb_register
	{ 5, OperandInfo393 },	// Inst #2538 = VLD1q32
	{ 6, OperandInfo403 },	// Inst #2539 = VLD1q32HighQPseudo
	{ 8, OperandInfo404 },	// Inst #2540 = VLD1q32HighQPseudo_UPD
	{ 6, OperandInfo403 },	// Inst #2541 = VLD1q32HighTPseudo
	{ 8, OperandInfo404 },	// Inst #2542 = VLD1q32HighTPseudo_UPD
	{ 8, OperandInfo404 },	// Inst #2543 = VLD1q32LowQPseudo_UPD
	{ 8, OperandInfo404 },	// Inst #2544 = VLD1q32LowTPseudo_UPD
	{ 6, OperandInfo394 },	// Inst #2545 = VLD1q32wb_fixed
	{ 7, OperandInfo395 },	// Inst #2546 = VLD1q32wb_register
	{ 5, OperandInfo393 },	// Inst #2547 = VLD1q64
	{ 6, OperandInfo403 },	// Inst #2548 = VLD1q64HighQPseudo
	{ 8, OperandInfo404 },	// Inst #2549 = VLD1q64HighQPseudo_UPD
	{ 6, OperandInfo403 },	// Inst #2550 = VLD1q64HighTPseudo
	{ 8, OperandInfo404 },	// Inst #2551 = VLD1q64HighTPseudo_UPD
	{ 8, OperandInfo404 },	// Inst #2552 = VLD1q64LowQPseudo_UPD
	{ 8, OperandInfo404 },	// Inst #2553 = VLD1q64LowTPseudo_UPD
	{ 6, OperandInfo394 },	// Inst #2554 = VLD1q64wb_fixed
	{ 7, OperandInfo395 },	// Inst #2555 = VLD1q64wb_register
	{ 5, OperandInfo393 },	// Inst #2556 = VLD1q8
	{ 6, OperandInfo403 },	// Inst #2557 = VLD1q8HighQPseudo
	{ 8, OperandInfo404 },	// Inst #2558 = VLD1q8HighQPseudo_UPD
	{ 6, OperandInfo403 },	// Inst #2559 = VLD1q8HighTPseudo
	{ 8, OperandInfo404 },	// Inst #2560 = VLD1q8HighTPseudo_UPD
	{ 8, OperandInfo404 },	// Inst #2561 = VLD1q8LowQPseudo_UPD
	{ 8, OperandInfo404 },	// Inst #2562 = VLD1q8LowTPseudo_UPD
	{ 6, OperandInfo394 },	// Inst #2563 = VLD1q8wb_fixed
	{ 7, OperandInfo395 },	// Inst #2564 = VLD1q8wb_register
	{ 5, OperandInfo393 },	// Inst #2565 = VLD2DUPd16
	{ 6, OperandInfo394 },	// Inst #2566 = VLD2DUPd16wb_fixed
	{ 7, OperandInfo395 },	// Inst #2567 = VLD2DUPd16wb_register
	{ 5, OperandInfo405 },	// Inst #2568 = VLD2DUPd16x2
	{ 6, OperandInfo406 },	// Inst #2569 = VLD2DUPd16x2wb_fixed
	{ 7, OperandInfo407 },	// Inst #2570 = VLD2DUPd16x2wb_register
	{ 5, OperandInfo393 },	// Inst #2571 = VLD2DUPd32
	{ 6, OperandInfo394 },	// Inst #2572 = VLD2DUPd32wb_fixed
	{ 7, OperandInfo395 },	// Inst #2573 = VLD2DUPd32wb_register
	{ 5, OperandInfo405 },	// Inst #2574 = VLD2DUPd32x2
	{ 6, OperandInfo406 },	// Inst #2575 = VLD2DUPd32x2wb_fixed
	{ 7, OperandInfo407 },	// Inst #2576 = VLD2DUPd32x2wb_register
	{ 5, OperandInfo393 },	// Inst #2577 = VLD2DUPd8
	{ 6, OperandInfo394 },	// Inst #2578 = VLD2DUPd8wb_fixed
	{ 7, OperandInfo395 },	// Inst #2579 = VLD2DUPd8wb_register
	{ 5, OperandInfo405 },	// Inst #2580 = VLD2DUPd8x2
	{ 6, OperandInfo406 },	// Inst #2581 = VLD2DUPd8x2wb_fixed
	{ 7, OperandInfo407 },	// Inst #2582 = VLD2DUPd8x2wb_register
	{ 5, OperandInfo400 },	// Inst #2583 = VLD2DUPq16EvenPseudo
	{ 5, OperandInfo400 },	// Inst #2584 = VLD2DUPq16OddPseudo
	{ 6, OperandInfo401 },	// Inst #2585 = VLD2DUPq16OddPseudoWB_fixed
	{ 7, OperandInfo408 },	// Inst #2586 = VLD2DUPq16OddPseudoWB_register
	{ 5, OperandInfo400 },	// Inst #2587 = VLD2DUPq32EvenPseudo
	{ 5, OperandInfo400 },	// Inst #2588 = VLD2DUPq32OddPseudo
	{ 6, OperandInfo401 },	// Inst #2589 = VLD2DUPq32OddPseudoWB_fixed
	{ 7, OperandInfo408 },	// Inst #2590 = VLD2DUPq32OddPseudoWB_register
	{ 5, OperandInfo400 },	// Inst #2591 = VLD2DUPq8EvenPseudo
	{ 5, OperandInfo400 },	// Inst #2592 = VLD2DUPq8OddPseudo
	{ 6, OperandInfo401 },	// Inst #2593 = VLD2DUPq8OddPseudoWB_fixed
	{ 7, OperandInfo408 },	// Inst #2594 = VLD2DUPq8OddPseudoWB_register
	{ 9, OperandInfo409 },	// Inst #2595 = VLD2LNd16
	{ 7, OperandInfo398 },	// Inst #2596 = VLD2LNd16Pseudo
	{ 9, OperandInfo399 },	// Inst #2597 = VLD2LNd16Pseudo_UPD
	{ 11, OperandInfo410 }, // Inst #2598 = VLD2LNd16_UPD
	{ 9, OperandInfo409 },	// Inst #2599 = VLD2LNd32
	{ 7, OperandInfo398 },	// Inst #2600 = VLD2LNd32Pseudo
	{ 9, OperandInfo399 },	// Inst #2601 = VLD2LNd32Pseudo_UPD
	{ 11, OperandInfo410 }, // Inst #2602 = VLD2LNd32_UPD
	{ 9, OperandInfo409 },	// Inst #2603 = VLD2LNd8
	{ 7, OperandInfo398 },	// Inst #2604 = VLD2LNd8Pseudo
	{ 9, OperandInfo399 },	// Inst #2605 = VLD2LNd8Pseudo_UPD
	{ 11, OperandInfo410 }, // Inst #2606 = VLD2LNd8_UPD
	{ 9, OperandInfo409 },	// Inst #2607 = VLD2LNq16
	{ 7, OperandInfo411 },	// Inst #2608 = VLD2LNq16Pseudo
	{ 9, OperandInfo412 },	// Inst #2609 = VLD2LNq16Pseudo_UPD
	{ 11, OperandInfo410 }, // Inst #2610 = VLD2LNq16_UPD
	{ 9, OperandInfo409 },	// Inst #2611 = VLD2LNq32
	{ 7, OperandInfo411 },	// Inst #2612 = VLD2LNq32Pseudo
	{ 9, OperandInfo412 },	// Inst #2613 = VLD2LNq32Pseudo_UPD
	{ 11, OperandInfo410 }, // Inst #2614 = VLD2LNq32_UPD
	{ 5, OperandInfo393 },	// Inst #2615 = VLD2b16
	{ 6, OperandInfo394 },	// Inst #2616 = VLD2b16wb_fixed
	{ 7, OperandInfo395 },	// Inst #2617 = VLD2b16wb_register
	{ 5, OperandInfo393 },	// Inst #2618 = VLD2b32
	{ 6, OperandInfo394 },	// Inst #2619 = VLD2b32wb_fixed
	{ 7, OperandInfo395 },	// Inst #2620 = VLD2b32wb_register
	{ 5, OperandInfo393 },	// Inst #2621 = VLD2b8
	{ 6, OperandInfo394 },	// Inst #2622 = VLD2b8wb_fixed
	{ 7, OperandInfo395 },	// Inst #2623 = VLD2b8wb_register
	{ 5, OperandInfo393 },	// Inst #2624 = VLD2d16
	{ 6, OperandInfo394 },	// Inst #2625 = VLD2d16wb_fixed
	{ 7, OperandInfo395 },	// Inst #2626 = VLD2d16wb_register
	{ 5, OperandInfo393 },	// Inst #2627 = VLD2d32
	{ 6, OperandInfo394 },	// Inst #2628 = VLD2d32wb_fixed
	{ 7, OperandInfo395 },	// Inst #2629 = VLD2d32wb_register
	{ 5, OperandInfo393 },	// Inst #2630 = VLD2d8
	{ 6, OperandInfo394 },	// Inst #2631 = VLD2d8wb_fixed
	{ 7, OperandInfo395 },	// Inst #2632 = VLD2d8wb_register
	{ 5, OperandInfo99 },	// Inst #2633 = VLD2q16
	{ 5, OperandInfo400 },	// Inst #2634 = VLD2q16Pseudo
	{ 6, OperandInfo401 },	// Inst #2635 = VLD2q16PseudoWB_fixed
	{ 7, OperandInfo402 },	// Inst #2636 = VLD2q16PseudoWB_register
	{ 6, OperandInfo391 },	// Inst #2637 = VLD2q16wb_fixed
	{ 7, OperandInfo392 },	// Inst #2638 = VLD2q16wb_register
	{ 5, OperandInfo99 },	// Inst #2639 = VLD2q32
	{ 5, OperandInfo400 },	// Inst #2640 = VLD2q32Pseudo
	{ 6, OperandInfo401 },	// Inst #2641 = VLD2q32PseudoWB_fixed
	{ 7, OperandInfo402 },	// Inst #2642 = VLD2q32PseudoWB_register
	{ 6, OperandInfo391 },	// Inst #2643 = VLD2q32wb_fixed
	{ 7, OperandInfo392 },	// Inst #2644 = VLD2q32wb_register
	{ 5, OperandInfo99 },	// Inst #2645 = VLD2q8
	{ 5, OperandInfo400 },	// Inst #2646 = VLD2q8Pseudo
	{ 6, OperandInfo401 },	// Inst #2647 = VLD2q8PseudoWB_fixed
	{ 7, OperandInfo402 },	// Inst #2648 = VLD2q8PseudoWB_register
	{ 6, OperandInfo391 },	// Inst #2649 = VLD2q8wb_fixed
	{ 7, OperandInfo392 },	// Inst #2650 = VLD2q8wb_register
	{ 7, OperandInfo413 },	// Inst #2651 = VLD3DUPd16
	{ 5, OperandInfo400 },	// Inst #2652 = VLD3DUPd16Pseudo
	{ 7, OperandInfo408 },	// Inst #2653 = VLD3DUPd16Pseudo_UPD
	{ 9, OperandInfo414 },	// Inst #2654 = VLD3DUPd16_UPD
	{ 7, OperandInfo413 },	// Inst #2655 = VLD3DUPd32
	{ 5, OperandInfo400 },	// Inst #2656 = VLD3DUPd32Pseudo
	{ 7, OperandInfo408 },	// Inst #2657 = VLD3DUPd32Pseudo_UPD
	{ 9, OperandInfo414 },	// Inst #2658 = VLD3DUPd32_UPD
	{ 7, OperandInfo413 },	// Inst #2659 = VLD3DUPd8
	{ 5, OperandInfo400 },	// Inst #2660 = VLD3DUPd8Pseudo
	{ 7, OperandInfo408 },	// Inst #2661 = VLD3DUPd8Pseudo_UPD
	{ 9, OperandInfo414 },	// Inst #2662 = VLD3DUPd8_UPD
	{ 7, OperandInfo413 },	// Inst #2663 = VLD3DUPq16
	{ 6, OperandInfo403 },	// Inst #2664 = VLD3DUPq16EvenPseudo
	{ 6, OperandInfo403 },	// Inst #2665 = VLD3DUPq16OddPseudo
	{ 8, OperandInfo404 },	// Inst #2666 = VLD3DUPq16OddPseudo_UPD
	{ 9, OperandInfo414 },	// Inst #2667 = VLD3DUPq16_UPD
	{ 7, OperandInfo413 },	// Inst #2668 = VLD3DUPq32
	{ 6, OperandInfo403 },	// Inst #2669 = VLD3DUPq32EvenPseudo
	{ 6, OperandInfo403 },	// Inst #2670 = VLD3DUPq32OddPseudo
	{ 8, OperandInfo404 },	// Inst #2671 = VLD3DUPq32OddPseudo_UPD
	{ 9, OperandInfo414 },	// Inst #2672 = VLD3DUPq32_UPD
	{ 7, OperandInfo413 },	// Inst #2673 = VLD3DUPq8
	{ 6, OperandInfo403 },	// Inst #2674 = VLD3DUPq8EvenPseudo
	{ 6, OperandInfo403 },	// Inst #2675 = VLD3DUPq8OddPseudo
	{ 8, OperandInfo404 },	// Inst #2676 = VLD3DUPq8OddPseudo_UPD
	{ 9, OperandInfo414 },	// Inst #2677 = VLD3DUPq8_UPD
	{ 11, OperandInfo415 }, // Inst #2678 = VLD3LNd16
	{ 7, OperandInfo411 },	// Inst #2679 = VLD3LNd16Pseudo
	{ 9, OperandInfo412 },	// Inst #2680 = VLD3LNd16Pseudo_UPD
	{ 13, OperandInfo416 }, // Inst #2681 = VLD3LNd16_UPD
	{ 11, OperandInfo415 }, // Inst #2682 = VLD3LNd32
	{ 7, OperandInfo411 },	// Inst #2683 = VLD3LNd32Pseudo
	{ 9, OperandInfo412 },	// Inst #2684 = VLD3LNd32Pseudo_UPD
	{ 13, OperandInfo416 }, // Inst #2685 = VLD3LNd32_UPD
	{ 11, OperandInfo415 }, // Inst #2686 = VLD3LNd8
	{ 7, OperandInfo411 },	// Inst #2687 = VLD3LNd8Pseudo
	{ 9, OperandInfo412 },	// Inst #2688 = VLD3LNd8Pseudo_UPD
	{ 13, OperandInfo416 }, // Inst #2689 = VLD3LNd8_UPD
	{ 11, OperandInfo415 }, // Inst #2690 = VLD3LNq16
	{ 7, OperandInfo417 },	// Inst #2691 = VLD3LNq16Pseudo
	{ 9, OperandInfo418 },	// Inst #2692 = VLD3LNq16Pseudo_UPD
	{ 13, OperandInfo416 }, // Inst #2693 = VLD3LNq16_UPD
	{ 11, OperandInfo415 }, // Inst #2694 = VLD3LNq32
	{ 7, OperandInfo417 },	// Inst #2695 = VLD3LNq32Pseudo
	{ 9, OperandInfo418 },	// Inst #2696 = VLD3LNq32Pseudo_UPD
	{ 13, OperandInfo416 }, // Inst #2697 = VLD3LNq32_UPD
	{ 7, OperandInfo413 },	// Inst #2698 = VLD3d16
	{ 5, OperandInfo400 },	// Inst #2699 = VLD3d16Pseudo
	{ 7, OperandInfo408 },	// Inst #2700 = VLD3d16Pseudo_UPD
	{ 9, OperandInfo414 },	// Inst #2701 = VLD3d16_UPD
	{ 7, OperandInfo413 },	// Inst #2702 = VLD3d32
	{ 5, OperandInfo400 },	// Inst #2703 = VLD3d32Pseudo
	{ 7, OperandInfo408 },	// Inst #2704 = VLD3d32Pseudo_UPD
	{ 9, OperandInfo414 },	// Inst #2705 = VLD3d32_UPD
	{ 7, OperandInfo413 },	// Inst #2706 = VLD3d8
	{ 5, OperandInfo400 },	// Inst #2707 = VLD3d8Pseudo
	{ 7, OperandInfo408 },	// Inst #2708 = VLD3d8Pseudo_UPD
	{ 9, OperandInfo414 },	// Inst #2709 = VLD3d8_UPD
	{ 7, OperandInfo413 },	// Inst #2710 = VLD3q16
	{ 8, OperandInfo404 },	// Inst #2711 = VLD3q16Pseudo_UPD
	{ 9, OperandInfo414 },	// Inst #2712 = VLD3q16_UPD
	{ 6, OperandInfo403 },	// Inst #2713 = VLD3q16oddPseudo
	{ 8, OperandInfo404 },	// Inst #2714 = VLD3q16oddPseudo_UPD
	{ 7, OperandInfo413 },	// Inst #2715 = VLD3q32
	{ 8, OperandInfo404 },	// Inst #2716 = VLD3q32Pseudo_UPD
	{ 9, OperandInfo414 },	// Inst #2717 = VLD3q32_UPD
	{ 6, OperandInfo403 },	// Inst #2718 = VLD3q32oddPseudo
	{ 8, OperandInfo404 },	// Inst #2719 = VLD3q32oddPseudo_UPD
	{ 7, OperandInfo413 },	// Inst #2720 = VLD3q8
	{ 8, OperandInfo404 },	// Inst #2721 = VLD3q8Pseudo_UPD
	{ 9, OperandInfo414 },	// Inst #2722 = VLD3q8_UPD
	{ 6, OperandInfo403 },	// Inst #2723 = VLD3q8oddPseudo
	{ 8, OperandInfo404 },	// Inst #2724 = VLD3q8oddPseudo_UPD
	{ 8, OperandInfo419 },	// Inst #2725 = VLD4DUPd16
	{ 5, OperandInfo400 },	// Inst #2726 = VLD4DUPd16Pseudo
	{ 7, OperandInfo408 },	// Inst #2727 = VLD4DUPd16Pseudo_UPD
	{ 10, OperandInfo420 }, // Inst #2728 = VLD4DUPd16_UPD
	{ 8, OperandInfo419 },	// Inst #2729 = VLD4DUPd32
	{ 5, OperandInfo400 },	// Inst #2730 = VLD4DUPd32Pseudo
	{ 7, OperandInfo408 },	// Inst #2731 = VLD4DUPd32Pseudo_UPD
	{ 10, OperandInfo420 }, // Inst #2732 = VLD4DUPd32_UPD
	{ 8, OperandInfo419 },	// Inst #2733 = VLD4DUPd8
	{ 5, OperandInfo400 },	// Inst #2734 = VLD4DUPd8Pseudo
	{ 7, OperandInfo408 },	// Inst #2735 = VLD4DUPd8Pseudo_UPD
	{ 10, OperandInfo420 }, // Inst #2736 = VLD4DUPd8_UPD
	{ 8, OperandInfo419 },	// Inst #2737 = VLD4DUPq16
	{ 6, OperandInfo403 },	// Inst #2738 = VLD4DUPq16EvenPseudo
	{ 6, OperandInfo403 },	// Inst #2739 = VLD4DUPq16OddPseudo
	{ 8, OperandInfo404 },	// Inst #2740 = VLD4DUPq16OddPseudo_UPD
	{ 10, OperandInfo420 }, // Inst #2741 = VLD4DUPq16_UPD
	{ 8, OperandInfo419 },	// Inst #2742 = VLD4DUPq32
	{ 6, OperandInfo403 },	// Inst #2743 = VLD4DUPq32EvenPseudo
	{ 6, OperandInfo403 },	// Inst #2744 = VLD4DUPq32OddPseudo
	{ 8, OperandInfo404 },	// Inst #2745 = VLD4DUPq32OddPseudo_UPD
	{ 10, OperandInfo420 }, // Inst #2746 = VLD4DUPq32_UPD
	{ 8, OperandInfo419 },	// Inst #2747 = VLD4DUPq8
	{ 6, OperandInfo403 },	// Inst #2748 = VLD4DUPq8EvenPseudo
	{ 6, OperandInfo403 },	// Inst #2749 = VLD4DUPq8OddPseudo
	{ 8, OperandInfo404 },	// Inst #2750 = VLD4DUPq8OddPseudo_UPD
	{ 10, OperandInfo420 }, // Inst #2751 = VLD4DUPq8_UPD
	{ 13, OperandInfo421 }, // Inst #2752 = VLD4LNd16
	{ 7, OperandInfo411 },	// Inst #2753 = VLD4LNd16Pseudo
	{ 9, OperandInfo412 },	// Inst #2754 = VLD4LNd16Pseudo_UPD
	{ 15, OperandInfo422 }, // Inst #2755 = VLD4LNd16_UPD
	{ 13, OperandInfo421 }, // Inst #2756 = VLD4LNd32
	{ 7, OperandInfo411 },	// Inst #2757 = VLD4LNd32Pseudo
	{ 9, OperandInfo412 },	// Inst #2758 = VLD4LNd32Pseudo_UPD
	{ 15, OperandInfo422 }, // Inst #2759 = VLD4LNd32_UPD
	{ 13, OperandInfo421 }, // Inst #2760 = VLD4LNd8
	{ 7, OperandInfo411 },	// Inst #2761 = VLD4LNd8Pseudo
	{ 9, OperandInfo412 },	// Inst #2762 = VLD4LNd8Pseudo_UPD
	{ 15, OperandInfo422 }, // Inst #2763 = VLD4LNd8_UPD
	{ 13, OperandInfo421 }, // Inst #2764 = VLD4LNq16
	{ 7, OperandInfo417 },	// Inst #2765 = VLD4LNq16Pseudo
	{ 9, OperandInfo418 },	// Inst #2766 = VLD4LNq16Pseudo_UPD
	{ 15, OperandInfo422 }, // Inst #2767 = VLD4LNq16_UPD
	{ 13, OperandInfo421 }, // Inst #2768 = VLD4LNq32
	{ 7, OperandInfo417 },	// Inst #2769 = VLD4LNq32Pseudo
	{ 9, OperandInfo418 },	// Inst #2770 = VLD4LNq32Pseudo_UPD
	{ 15, OperandInfo422 }, // Inst #2771 = VLD4LNq32_UPD
	{ 8, OperandInfo419 },	// Inst #2772 = VLD4d16
	{ 5, OperandInfo400 },	// Inst #2773 = VLD4d16Pseudo
	{ 7, OperandInfo408 },	// Inst #2774 = VLD4d16Pseudo_UPD
	{ 10, OperandInfo420 }, // Inst #2775 = VLD4d16_UPD
	{ 8, OperandInfo419 },	// Inst #2776 = VLD4d32
	{ 5, OperandInfo400 },	// Inst #2777 = VLD4d32Pseudo
	{ 7, OperandInfo408 },	// Inst #2778 = VLD4d32Pseudo_UPD
	{ 10, OperandInfo420 }, // Inst #2779 = VLD4d32_UPD
	{ 8, OperandInfo419 },	// Inst #2780 = VLD4d8
	{ 5, OperandInfo400 },	// Inst #2781 = VLD4d8Pseudo
	{ 7, OperandInfo408 },	// Inst #2782 = VLD4d8Pseudo_UPD
	{ 10, OperandInfo420 }, // Inst #2783 = VLD4d8_UPD
	{ 8, OperandInfo419 },	// Inst #2784 = VLD4q16
	{ 8, OperandInfo404 },	// Inst #2785 = VLD4q16Pseudo_UPD
	{ 10, OperandInfo420 }, // Inst #2786 = VLD4q16_UPD
	{ 6, OperandInfo403 },	// Inst #2787 = VLD4q16oddPseudo
	{ 8, OperandInfo404 },	// Inst #2788 = VLD4q16oddPseudo_UPD
	{ 8, OperandInfo419 },	// Inst #2789 = VLD4q32
	{ 8, OperandInfo404 },	// Inst #2790 = VLD4q32Pseudo_UPD
	{ 10, OperandInfo420 }, // Inst #2791 = VLD4q32_UPD
	{ 6, OperandInfo403 },	// Inst #2792 = VLD4q32oddPseudo
	{ 8, OperandInfo404 },	// Inst #2793 = VLD4q32oddPseudo_UPD
	{ 8, OperandInfo419 },	// Inst #2794 = VLD4q8
	{ 8, OperandInfo404 },	// Inst #2795 = VLD4q8Pseudo_UPD
	{ 10, OperandInfo420 }, // Inst #2796 = VLD4q8_UPD
	{ 6, OperandInfo403 },	// Inst #2797 = VLD4q8oddPseudo
	{ 8, OperandInfo404 },	// Inst #2798 = VLD4q8oddPseudo_UPD
	{ 5, OperandInfo66 },	// Inst #2799 = VLDMDDB_UPD
	{ 4, OperandInfo206 },	// Inst #2800 = VLDMDIA
	{ 5, OperandInfo66 },	// Inst #2801 = VLDMDIA_UPD
	{ 4, OperandInfo423 },	// Inst #2802 = VLDMQIA
	{ 5, OperandInfo66 },	// Inst #2803 = VLDMSDB_UPD
	{ 4, OperandInfo206 },	// Inst #2804 = VLDMSIA
	{ 5, OperandInfo66 },	// Inst #2805 = VLDMSIA_UPD
	{ 5, OperandInfo99 },	// Inst #2806 = VLDRD
	{ 5, OperandInfo424 },	// Inst #2807 = VLDRH
	{ 5, OperandInfo425 },	// Inst #2808 = VLDRS
	{ 4, OperandInfo426 },	// Inst #2809 = VLDR_FPCXTNS_off
	{ 5, OperandInfo427 },	// Inst #2810 = VLDR_FPCXTNS_post
	{ 5, OperandInfo427 },	// Inst #2811 = VLDR_FPCXTNS_pre
	{ 4, OperandInfo426 },	// Inst #2812 = VLDR_FPCXTS_off
	{ 5, OperandInfo427 },	// Inst #2813 = VLDR_FPCXTS_post
	{ 5, OperandInfo427 },	// Inst #2814 = VLDR_FPCXTS_pre
	{ 4, OperandInfo426 },	// Inst #2815 = VLDR_FPSCR_NZCVQC_off
	{ 5, OperandInfo427 },	// Inst #2816 = VLDR_FPSCR_NZCVQC_post
	{ 5, OperandInfo427 },	// Inst #2817 = VLDR_FPSCR_NZCVQC_pre
	{ 4, OperandInfo426 },	// Inst #2818 = VLDR_FPSCR_off
	{ 5, OperandInfo427 },	// Inst #2819 = VLDR_FPSCR_post
	{ 5, OperandInfo427 },	// Inst #2820 = VLDR_FPSCR_pre
	{ 5, OperandInfo428 },	// Inst #2821 = VLDR_P0_off
	{ 6, OperandInfo429 },	// Inst #2822 = VLDR_P0_post
	{ 6, OperandInfo429 },	// Inst #2823 = VLDR_P0_pre
	{ 4, OperandInfo426 },	// Inst #2824 = VLDR_VPR_off
	{ 5, OperandInfo427 },	// Inst #2825 = VLDR_VPR_post
	{ 5, OperandInfo427 },	// Inst #2826 = VLDR_VPR_pre
	{ 3, OperandInfo239 },	// Inst #2827 = VLLDM
	{ 3, OperandInfo239 },	// Inst #2828 = VLSTM
	{ 5, OperandInfo340 },	// Inst #2829 = VMAXfd
	{ 5, OperandInfo341 },	// Inst #2830 = VMAXfq
	{ 5, OperandInfo340 },	// Inst #2831 = VMAXhd
	{ 5, OperandInfo341 },	// Inst #2832 = VMAXhq
	{ 5, OperandInfo341 },	// Inst #2833 = VMAXsv16i8
	{ 5, OperandInfo340 },	// Inst #2834 = VMAXsv2i32
	{ 5, OperandInfo340 },	// Inst #2835 = VMAXsv4i16
	{ 5, OperandInfo341 },	// Inst #2836 = VMAXsv4i32
	{ 5, OperandInfo341 },	// Inst #2837 = VMAXsv8i16
	{ 5, OperandInfo340 },	// Inst #2838 = VMAXsv8i8
	{ 5, OperandInfo341 },	// Inst #2839 = VMAXuv16i8
	{ 5, OperandInfo340 },	// Inst #2840 = VMAXuv2i32
	{ 5, OperandInfo340 },	// Inst #2841 = VMAXuv4i16
	{ 5, OperandInfo341 },	// Inst #2842 = VMAXuv4i32
	{ 5, OperandInfo341 },	// Inst #2843 = VMAXuv8i16
	{ 5, OperandInfo340 },	// Inst #2844 = VMAXuv8i8
	{ 5, OperandInfo340 },	// Inst #2845 = VMINfd
	{ 5, OperandInfo341 },	// Inst #2846 = VMINfq
	{ 5, OperandInfo340 },	// Inst #2847 = VMINhd
	{ 5, OperandInfo341 },	// Inst #2848 = VMINhq
	{ 5, OperandInfo341 },	// Inst #2849 = VMINsv16i8
	{ 5, OperandInfo340 },	// Inst #2850 = VMINsv2i32
	{ 5, OperandInfo340 },	// Inst #2851 = VMINsv4i16
	{ 5, OperandInfo341 },	// Inst #2852 = VMINsv4i32
	{ 5, OperandInfo341 },	// Inst #2853 = VMINsv8i16
	{ 5, OperandInfo340 },	// Inst #2854 = VMINsv8i8
	{ 5, OperandInfo341 },	// Inst #2855 = VMINuv16i8
	{ 5, OperandInfo340 },	// Inst #2856 = VMINuv2i32
	{ 5, OperandInfo340 },	// Inst #2857 = VMINuv4i16
	{ 5, OperandInfo341 },	// Inst #2858 = VMINuv4i32
	{ 5, OperandInfo341 },	// Inst #2859 = VMINuv8i16
	{ 5, OperandInfo340 },	// Inst #2860 = VMINuv8i8
	{ 6, OperandInfo338 },	// Inst #2861 = VMLAD
	{ 6, OperandInfo381 },	// Inst #2862 = VMLAH
	{ 7, OperandInfo430 },	// Inst #2863 = VMLALslsv2i32
	{ 7, OperandInfo431 },	// Inst #2864 = VMLALslsv4i16
	{ 7, OperandInfo430 },	// Inst #2865 = VMLALsluv2i32
	{ 7, OperandInfo431 },	// Inst #2866 = VMLALsluv4i16
	{ 6, OperandInfo336 },	// Inst #2867 = VMLALsv2i64
	{ 6, OperandInfo336 },	// Inst #2868 = VMLALsv4i32
	{ 6, OperandInfo336 },	// Inst #2869 = VMLALsv8i16
	{ 6, OperandInfo336 },	// Inst #2870 = VMLALuv2i64
	{ 6, OperandInfo336 },	// Inst #2871 = VMLALuv4i32
	{ 6, OperandInfo336 },	// Inst #2872 = VMLALuv8i16
	{ 6, OperandInfo386 },	// Inst #2873 = VMLAS
	{ 6, OperandInfo338 },	// Inst #2874 = VMLAfd
	{ 6, OperandInfo337 },	// Inst #2875 = VMLAfq
	{ 6, OperandInfo338 },	// Inst #2876 = VMLAhd
	{ 6, OperandInfo337 },	// Inst #2877 = VMLAhq
	{ 7, OperandInfo432 },	// Inst #2878 = VMLAslfd
	{ 7, OperandInfo433 },	// Inst #2879 = VMLAslfq
	{ 7, OperandInfo434 },	// Inst #2880 = VMLAslhd
	{ 7, OperandInfo435 },	// Inst #2881 = VMLAslhq
	{ 7, OperandInfo432 },	// Inst #2882 = VMLAslv2i32
	{ 7, OperandInfo434 },	// Inst #2883 = VMLAslv4i16
	{ 7, OperandInfo433 },	// Inst #2884 = VMLAslv4i32
	{ 7, OperandInfo435 },	// Inst #2885 = VMLAslv8i16
	{ 6, OperandInfo337 },	// Inst #2886 = VMLAv16i8
	{ 6, OperandInfo338 },	// Inst #2887 = VMLAv2i32
	{ 6, OperandInfo338 },	// Inst #2888 = VMLAv4i16
	{ 6, OperandInfo337 },	// Inst #2889 = VMLAv4i32
	{ 6, OperandInfo337 },	// Inst #2890 = VMLAv8i16
	{ 6, OperandInfo338 },	// Inst #2891 = VMLAv8i8
	{ 6, OperandInfo338 },	// Inst #2892 = VMLSD
	{ 6, OperandInfo381 },	// Inst #2893 = VMLSH
	{ 7, OperandInfo430 },	// Inst #2894 = VMLSLslsv2i32
	{ 7, OperandInfo431 },	// Inst #2895 = VMLSLslsv4i16
	{ 7, OperandInfo430 },	// Inst #2896 = VMLSLsluv2i32
	{ 7, OperandInfo431 },	// Inst #2897 = VMLSLsluv4i16
	{ 6, OperandInfo336 },	// Inst #2898 = VMLSLsv2i64
	{ 6, OperandInfo336 },	// Inst #2899 = VMLSLsv4i32
	{ 6, OperandInfo336 },	// Inst #2900 = VMLSLsv8i16
	{ 6, OperandInfo336 },	// Inst #2901 = VMLSLuv2i64
	{ 6, OperandInfo336 },	// Inst #2902 = VMLSLuv4i32
	{ 6, OperandInfo336 },	// Inst #2903 = VMLSLuv8i16
	{ 6, OperandInfo386 },	// Inst #2904 = VMLSS
	{ 6, OperandInfo338 },	// Inst #2905 = VMLSfd
	{ 6, OperandInfo337 },	// Inst #2906 = VMLSfq
	{ 6, OperandInfo338 },	// Inst #2907 = VMLShd
	{ 6, OperandInfo337 },	// Inst #2908 = VMLShq
	{ 7, OperandInfo432 },	// Inst #2909 = VMLSslfd
	{ 7, OperandInfo433 },	// Inst #2910 = VMLSslfq
	{ 7, OperandInfo434 },	// Inst #2911 = VMLSslhd
	{ 7, OperandInfo435 },	// Inst #2912 = VMLSslhq
	{ 7, OperandInfo432 },	// Inst #2913 = VMLSslv2i32
	{ 7, OperandInfo434 },	// Inst #2914 = VMLSslv4i16
	{ 7, OperandInfo433 },	// Inst #2915 = VMLSslv4i32
	{ 7, OperandInfo435 },	// Inst #2916 = VMLSslv8i16
	{ 6, OperandInfo337 },	// Inst #2917 = VMLSv16i8
	{ 6, OperandInfo338 },	// Inst #2918 = VMLSv2i32
	{ 6, OperandInfo338 },	// Inst #2919 = VMLSv4i16
	{ 6, OperandInfo337 },	// Inst #2920 = VMLSv4i32
	{ 6, OperandInfo337 },	// Inst #2921 = VMLSv8i16
	{ 6, OperandInfo338 },	// Inst #2922 = VMLSv8i8
	{ 4, OperandInfo162 },	// Inst #2923 = VMMLA
	{ 4, OperandInfo342 },	// Inst #2924 = VMOVD
	{ 5, OperandInfo436 },	// Inst #2925 = VMOVDRR
	{ 2, OperandInfo369 },	// Inst #2926 = VMOVH
	{ 4, OperandInfo437 },	// Inst #2927 = VMOVHR
	{ 4, OperandInfo375 },	// Inst #2928 = VMOVLsv2i64
	{ 4, OperandInfo375 },	// Inst #2929 = VMOVLsv4i32
	{ 4, OperandInfo375 },	// Inst #2930 = VMOVLsv8i16
	{ 4, OperandInfo375 },	// Inst #2931 = VMOVLuv2i64
	{ 4, OperandInfo375 },	// Inst #2932 = VMOVLuv4i32
	{ 4, OperandInfo375 },	// Inst #2933 = VMOVLuv8i16
	{ 4, OperandInfo163 },	// Inst #2934 = VMOVNv2i32
	{ 4, OperandInfo163 },	// Inst #2935 = VMOVNv4i16
	{ 4, OperandInfo163 },	// Inst #2936 = VMOVNv8i8
	{ 4, OperandInfo438 },	// Inst #2937 = VMOVRH
	{ 5, OperandInfo439 },	// Inst #2938 = VMOVRRD
	{ 6, OperandInfo440 },	// Inst #2939 = VMOVRRS
	{ 4, OperandInfo441 },	// Inst #2940 = VMOVRS
	{ 4, OperandInfo344 },	// Inst #2941 = VMOVS
	{ 4, OperandInfo442 },	// Inst #2942 = VMOVSR
	{ 6, OperandInfo443 },	// Inst #2943 = VMOVSRR
	{ 4, OperandInfo444 },	// Inst #2944 = VMOVv16i8
	{ 4, OperandInfo203 },	// Inst #2945 = VMOVv1i64
	{ 4, OperandInfo203 },	// Inst #2946 = VMOVv2f32
	{ 4, OperandInfo203 },	// Inst #2947 = VMOVv2i32
	{ 4, OperandInfo444 },	// Inst #2948 = VMOVv2i64
	{ 4, OperandInfo444 },	// Inst #2949 = VMOVv4f32
	{ 4, OperandInfo203 },	// Inst #2950 = VMOVv4i16
	{ 4, OperandInfo444 },	// Inst #2951 = VMOVv4i32
	{ 4, OperandInfo444 },	// Inst #2952 = VMOVv8i16
	{ 4, OperandInfo203 },	// Inst #2953 = VMOVv8i8
	{ 3, OperandInfo239 },	// Inst #2954 = VMRS
	{ 3, OperandInfo137 },	// Inst #2955 = VMRS_FPCXTNS
	{ 3, OperandInfo137 },	// Inst #2956 = VMRS_FPCXTS
	{ 3, OperandInfo239 },	// Inst #2957 = VMRS_FPEXC
	{ 3, OperandInfo239 },	// Inst #2958 = VMRS_FPINST
	{ 3, OperandInfo239 },	// Inst #2959 = VMRS_FPINST2
	{ 4, OperandInfo445 },	// Inst #2960 = VMRS_FPSCR_NZCVQC
	{ 3, OperandInfo239 },	// Inst #2961 = VMRS_FPSID
	{ 3, OperandInfo239 },	// Inst #2962 = VMRS_MVFR0
	{ 3, OperandInfo239 },	// Inst #2963 = VMRS_MVFR1
	{ 3, OperandInfo239 },	// Inst #2964 = VMRS_MVFR2
	{ 4, OperandInfo446 },	// Inst #2965 = VMRS_P0
	{ 3, OperandInfo137 },	// Inst #2966 = VMRS_VPR
	{ 3, OperandInfo239 },	// Inst #2967 = VMSR
	{ 3, OperandInfo137 },	// Inst #2968 = VMSR_FPCXTNS
	{ 3, OperandInfo137 },	// Inst #2969 = VMSR_FPCXTS
	{ 3, OperandInfo239 },	// Inst #2970 = VMSR_FPEXC
	{ 3, OperandInfo239 },	// Inst #2971 = VMSR_FPINST
	{ 3, OperandInfo239 },	// Inst #2972 = VMSR_FPINST2
	{ 4, OperandInfo447 },	// Inst #2973 = VMSR_FPSCR_NZCVQC
	{ 3, OperandInfo239 },	// Inst #2974 = VMSR_FPSID
	{ 4, OperandInfo448 },	// Inst #2975 = VMSR_P0
	{ 3, OperandInfo137 },	// Inst #2976 = VMSR_VPR
	{ 5, OperandInfo340 },	// Inst #2977 = VMULD
	{ 5, OperandInfo346 },	// Inst #2978 = VMULH
	{ 3, OperandInfo384 },	// Inst #2979 = VMULLp64
	{ 5, OperandInfo339 },	// Inst #2980 = VMULLp8
	{ 6, OperandInfo449 },	// Inst #2981 = VMULLslsv2i32
	{ 6, OperandInfo450 },	// Inst #2982 = VMULLslsv4i16
	{ 6, OperandInfo449 },	// Inst #2983 = VMULLsluv2i32
	{ 6, OperandInfo450 },	// Inst #2984 = VMULLsluv4i16
	{ 5, OperandInfo339 },	// Inst #2985 = VMULLsv2i64
	{ 5, OperandInfo339 },	// Inst #2986 = VMULLsv4i32
	{ 5, OperandInfo339 },	// Inst #2987 = VMULLsv8i16
	{ 5, OperandInfo339 },	// Inst #2988 = VMULLuv2i64
	{ 5, OperandInfo339 },	// Inst #2989 = VMULLuv4i32
	{ 5, OperandInfo339 },	// Inst #2990 = VMULLuv8i16
	{ 5, OperandInfo348 },	// Inst #2991 = VMULS
	{ 5, OperandInfo340 },	// Inst #2992 = VMULfd
	{ 5, OperandInfo341 },	// Inst #2993 = VMULfq
	{ 5, OperandInfo340 },	// Inst #2994 = VMULhd
	{ 5, OperandInfo341 },	// Inst #2995 = VMULhq
	{ 5, OperandInfo340 },	// Inst #2996 = VMULpd
	{ 5, OperandInfo341 },	// Inst #2997 = VMULpq
	{ 6, OperandInfo451 },	// Inst #2998 = VMULslfd
	{ 6, OperandInfo452 },	// Inst #2999 = VMULslfq
	{ 6, OperandInfo453 },	// Inst #3000 = VMULslhd
	{ 6, OperandInfo454 },	// Inst #3001 = VMULslhq
	{ 6, OperandInfo451 },	// Inst #3002 = VMULslv2i32
	{ 6, OperandInfo453 },	// Inst #3003 = VMULslv4i16
	{ 6, OperandInfo452 },	// Inst #3004 = VMULslv4i32
	{ 6, OperandInfo454 },	// Inst #3005 = VMULslv8i16
	{ 5, OperandInfo341 },	// Inst #3006 = VMULv16i8
	{ 5, OperandInfo340 },	// Inst #3007 = VMULv2i32
	{ 5, OperandInfo340 },	// Inst #3008 = VMULv4i16
	{ 5, OperandInfo341 },	// Inst #3009 = VMULv4i32
	{ 5, OperandInfo341 },	// Inst #3010 = VMULv8i16
	{ 5, OperandInfo340 },	// Inst #3011 = VMULv8i8
	{ 4, OperandInfo342 },	// Inst #3012 = VMVNd
	{ 4, OperandInfo345 },	// Inst #3013 = VMVNq
	{ 4, OperandInfo203 },	// Inst #3014 = VMVNv2i32
	{ 4, OperandInfo203 },	// Inst #3015 = VMVNv4i16
	{ 4, OperandInfo444 },	// Inst #3016 = VMVNv4i32
	{ 4, OperandInfo444 },	// Inst #3017 = VMVNv8i16
	{ 4, OperandInfo342 },	// Inst #3018 = VNEGD
	{ 4, OperandInfo343 },	// Inst #3019 = VNEGH
	{ 4, OperandInfo344 },	// Inst #3020 = VNEGS
	{ 4, OperandInfo345 },	// Inst #3021 = VNEGf32q
	{ 4, OperandInfo342 },	// Inst #3022 = VNEGfd
	{ 4, OperandInfo342 },	// Inst #3023 = VNEGhd
	{ 4, OperandInfo345 },	// Inst #3024 = VNEGhq
	{ 4, OperandInfo342 },	// Inst #3025 = VNEGs16d
	{ 4, OperandInfo345 },	// Inst #3026 = VNEGs16q
	{ 4, OperandInfo342 },	// Inst #3027 = VNEGs32d
	{ 4, OperandInfo345 },	// Inst #3028 = VNEGs32q
	{ 4, OperandInfo342 },	// Inst #3029 = VNEGs8d
	{ 4, OperandInfo345 },	// Inst #3030 = VNEGs8q
	{ 6, OperandInfo338 },	// Inst #3031 = VNMLAD
	{ 6, OperandInfo381 },	// Inst #3032 = VNMLAH
	{ 6, OperandInfo386 },	// Inst #3033 = VNMLAS
	{ 6, OperandInfo338 },	// Inst #3034 = VNMLSD
	{ 6, OperandInfo381 },	// Inst #3035 = VNMLSH
	{ 6, OperandInfo386 },	// Inst #3036 = VNMLSS
	{ 5, OperandInfo340 },	// Inst #3037 = VNMULD
	{ 5, OperandInfo346 },	// Inst #3038 = VNMULH
	{ 5, OperandInfo348 },	// Inst #3039 = VNMULS
	{ 5, OperandInfo340 },	// Inst #3040 = VORNd
	{ 5, OperandInfo341 },	// Inst #3041 = VORNq
	{ 5, OperandInfo340 },	// Inst #3042 = VORRd
	{ 5, OperandInfo351 },	// Inst #3043 = VORRiv2i32
	{ 5, OperandInfo351 },	// Inst #3044 = VORRiv4i16
	{ 5, OperandInfo352 },	// Inst #3045 = VORRiv4i32
	{ 5, OperandInfo352 },	// Inst #3046 = VORRiv8i16
	{ 5, OperandInfo341 },	// Inst #3047 = VORRq
	{ 5, OperandInfo455 },	// Inst #3048 = VPADALsv16i8
	{ 5, OperandInfo102 },	// Inst #3049 = VPADALsv2i32
	{ 5, OperandInfo102 },	// Inst #3050 = VPADALsv4i16
	{ 5, OperandInfo455 },	// Inst #3051 = VPADALsv4i32
	{ 5, OperandInfo455 },	// Inst #3052 = VPADALsv8i16
	{ 5, OperandInfo102 },	// Inst #3053 = VPADALsv8i8
	{ 5, OperandInfo455 },	// Inst #3054 = VPADALuv16i8
	{ 5, OperandInfo102 },	// Inst #3055 = VPADALuv2i32
	{ 5, OperandInfo102 },	// Inst #3056 = VPADALuv4i16
	{ 5, OperandInfo455 },	// Inst #3057 = VPADALuv4i32
	{ 5, OperandInfo455 },	// Inst #3058 = VPADALuv8i16
	{ 5, OperandInfo102 },	// Inst #3059 = VPADALuv8i8
	{ 4, OperandInfo345 },	// Inst #3060 = VPADDLsv16i8
	{ 4, OperandInfo342 },	// Inst #3061 = VPADDLsv2i32
	{ 4, OperandInfo342 },	// Inst #3062 = VPADDLsv4i16
	{ 4, OperandInfo345 },	// Inst #3063 = VPADDLsv4i32
	{ 4, OperandInfo345 },	// Inst #3064 = VPADDLsv8i16
	{ 4, OperandInfo342 },	// Inst #3065 = VPADDLsv8i8
	{ 4, OperandInfo345 },	// Inst #3066 = VPADDLuv16i8
	{ 4, OperandInfo342 },	// Inst #3067 = VPADDLuv2i32
	{ 4, OperandInfo342 },	// Inst #3068 = VPADDLuv4i16
	{ 4, OperandInfo345 },	// Inst #3069 = VPADDLuv4i32
	{ 4, OperandInfo345 },	// Inst #3070 = VPADDLuv8i16
	{ 4, OperandInfo342 },	// Inst #3071 = VPADDLuv8i8
	{ 5, OperandInfo340 },	// Inst #3072 = VPADDf
	{ 5, OperandInfo340 },	// Inst #3073 = VPADDh
	{ 5, OperandInfo340 },	// Inst #3074 = VPADDi16
	{ 5, OperandInfo340 },	// Inst #3075 = VPADDi32
	{ 5, OperandInfo340 },	// Inst #3076 = VPADDi8
	{ 5, OperandInfo340 },	// Inst #3077 = VPMAXf
	{ 5, OperandInfo340 },	// Inst #3078 = VPMAXh
	{ 5, OperandInfo340 },	// Inst #3079 = VPMAXs16
	{ 5, OperandInfo340 },	// Inst #3080 = VPMAXs32
	{ 5, OperandInfo340 },	// Inst #3081 = VPMAXs8
	{ 5, OperandInfo340 },	// Inst #3082 = VPMAXu16
	{ 5, OperandInfo340 },	// Inst #3083 = VPMAXu32
	{ 5, OperandInfo340 },	// Inst #3084 = VPMAXu8
	{ 5, OperandInfo340 },	// Inst #3085 = VPMINf
	{ 5, OperandInfo340 },	// Inst #3086 = VPMINh
	{ 5, OperandInfo340 },	// Inst #3087 = VPMINs16
	{ 5, OperandInfo340 },	// Inst #3088 = VPMINs32
	{ 5, OperandInfo340 },	// Inst #3089 = VPMINs8
	{ 5, OperandInfo340 },	// Inst #3090 = VPMINu16
	{ 5, OperandInfo340 },	// Inst #3091 = VPMINu32
	{ 5, OperandInfo340 },	// Inst #3092 = VPMINu8
	{ 4, OperandInfo345 },	// Inst #3093 = VQABSv16i8
	{ 4, OperandInfo342 },	// Inst #3094 = VQABSv2i32
	{ 4, OperandInfo342 },	// Inst #3095 = VQABSv4i16
	{ 4, OperandInfo345 },	// Inst #3096 = VQABSv4i32
	{ 4, OperandInfo345 },	// Inst #3097 = VQABSv8i16
	{ 4, OperandInfo342 },	// Inst #3098 = VQABSv8i8
	{ 5, OperandInfo341 },	// Inst #3099 = VQADDsv16i8
	{ 5, OperandInfo340 },	// Inst #3100 = VQADDsv1i64
	{ 5, OperandInfo340 },	// Inst #3101 = VQADDsv2i32
	{ 5, OperandInfo341 },	// Inst #3102 = VQADDsv2i64
	{ 5, OperandInfo340 },	// Inst #3103 = VQADDsv4i16
	{ 5, OperandInfo341 },	// Inst #3104 = VQADDsv4i32
	{ 5, OperandInfo341 },	// Inst #3105 = VQADDsv8i16
	{ 5, OperandInfo340 },	// Inst #3106 = VQADDsv8i8
	{ 5, OperandInfo341 },	// Inst #3107 = VQADDuv16i8
	{ 5, OperandInfo340 },	// Inst #3108 = VQADDuv1i64
	{ 5, OperandInfo340 },	// Inst #3109 = VQADDuv2i32
	{ 5, OperandInfo341 },	// Inst #3110 = VQADDuv2i64
	{ 5, OperandInfo340 },	// Inst #3111 = VQADDuv4i16
	{ 5, OperandInfo341 },	// Inst #3112 = VQADDuv4i32
	{ 5, OperandInfo341 },	// Inst #3113 = VQADDuv8i16
	{ 5, OperandInfo340 },	// Inst #3114 = VQADDuv8i8
	{ 7, OperandInfo430 },	// Inst #3115 = VQDMLALslv2i32
	{ 7, OperandInfo431 },	// Inst #3116 = VQDMLALslv4i16
	{ 6, OperandInfo336 },	// Inst #3117 = VQDMLALv2i64
	{ 6, OperandInfo336 },	// Inst #3118 = VQDMLALv4i32
	{ 7, OperandInfo430 },	// Inst #3119 = VQDMLSLslv2i32
	{ 7, OperandInfo431 },	// Inst #3120 = VQDMLSLslv4i16
	{ 6, OperandInfo336 },	// Inst #3121 = VQDMLSLv2i64
	{ 6, OperandInfo336 },	// Inst #3122 = VQDMLSLv4i32
	{ 6, OperandInfo451 },	// Inst #3123 = VQDMULHslv2i32
	{ 6, OperandInfo453 },	// Inst #3124 = VQDMULHslv4i16
	{ 6, OperandInfo452 },	// Inst #3125 = VQDMULHslv4i32
	{ 6, OperandInfo454 },	// Inst #3126 = VQDMULHslv8i16
	{ 5, OperandInfo340 },	// Inst #3127 = VQDMULHv2i32
	{ 5, OperandInfo340 },	// Inst #3128 = VQDMULHv4i16
	{ 5, OperandInfo341 },	// Inst #3129 = VQDMULHv4i32
	{ 5, OperandInfo341 },	// Inst #3130 = VQDMULHv8i16
	{ 6, OperandInfo449 },	// Inst #3131 = VQDMULLslv2i32
	{ 6, OperandInfo450 },	// Inst #3132 = VQDMULLslv4i16
	{ 5, OperandInfo339 },	// Inst #3133 = VQDMULLv2i64
	{ 5, OperandInfo339 },	// Inst #3134 = VQDMULLv4i32
	{ 4, OperandInfo163 },	// Inst #3135 = VQMOVNsuv2i32
	{ 4, OperandInfo163 },	// Inst #3136 = VQMOVNsuv4i16
	{ 4, OperandInfo163 },	// Inst #3137 = VQMOVNsuv8i8
	{ 4, OperandInfo163 },	// Inst #3138 = VQMOVNsv2i32
	{ 4, OperandInfo163 },	// Inst #3139 = VQMOVNsv4i16
	{ 4, OperandInfo163 },	// Inst #3140 = VQMOVNsv8i8
	{ 4, OperandInfo163 },	// Inst #3141 = VQMOVNuv2i32
	{ 4, OperandInfo163 },	// Inst #3142 = VQMOVNuv4i16
	{ 4, OperandInfo163 },	// Inst #3143 = VQMOVNuv8i8
	{ 4, OperandInfo345 },	// Inst #3144 = VQNEGv16i8
	{ 4, OperandInfo342 },	// Inst #3145 = VQNEGv2i32
	{ 4, OperandInfo342 },	// Inst #3146 = VQNEGv4i16
	{ 4, OperandInfo345 },	// Inst #3147 = VQNEGv4i32
	{ 4, OperandInfo345 },	// Inst #3148 = VQNEGv8i16
	{ 4, OperandInfo342 },	// Inst #3149 = VQNEGv8i8
	{ 7, OperandInfo432 },	// Inst #3150 = VQRDMLAHslv2i32
	{ 7, OperandInfo434 },	// Inst #3151 = VQRDMLAHslv4i16
	{ 7, OperandInfo433 },	// Inst #3152 = VQRDMLAHslv4i32
	{ 7, OperandInfo435 },	// Inst #3153 = VQRDMLAHslv8i16
	{ 6, OperandInfo338 },	// Inst #3154 = VQRDMLAHv2i32
	{ 6, OperandInfo338 },	// Inst #3155 = VQRDMLAHv4i16
	{ 6, OperandInfo337 },	// Inst #3156 = VQRDMLAHv4i32
	{ 6, OperandInfo337 },	// Inst #3157 = VQRDMLAHv8i16
	{ 7, OperandInfo432 },	// Inst #3158 = VQRDMLSHslv2i32
	{ 7, OperandInfo434 },	// Inst #3159 = VQRDMLSHslv4i16
	{ 7, OperandInfo433 },	// Inst #3160 = VQRDMLSHslv4i32
	{ 7, OperandInfo435 },	// Inst #3161 = VQRDMLSHslv8i16
	{ 6, OperandInfo338 },	// Inst #3162 = VQRDMLSHv2i32
	{ 6, OperandInfo338 },	// Inst #3163 = VQRDMLSHv4i16
	{ 6, OperandInfo337 },	// Inst #3164 = VQRDMLSHv4i32
	{ 6, OperandInfo337 },	// Inst #3165 = VQRDMLSHv8i16
	{ 6, OperandInfo451 },	// Inst #3166 = VQRDMULHslv2i32
	{ 6, OperandInfo453 },	// Inst #3167 = VQRDMULHslv4i16
	{ 6, OperandInfo452 },	// Inst #3168 = VQRDMULHslv4i32
	{ 6, OperandInfo454 },	// Inst #3169 = VQRDMULHslv8i16
	{ 5, OperandInfo340 },	// Inst #3170 = VQRDMULHv2i32
	{ 5, OperandInfo340 },	// Inst #3171 = VQRDMULHv4i16
	{ 5, OperandInfo341 },	// Inst #3172 = VQRDMULHv4i32
	{ 5, OperandInfo341 },	// Inst #3173 = VQRDMULHv8i16
	{ 5, OperandInfo341 },	// Inst #3174 = VQRSHLsv16i8
	{ 5, OperandInfo340 },	// Inst #3175 = VQRSHLsv1i64
	{ 5, OperandInfo340 },	// Inst #3176 = VQRSHLsv2i32
	{ 5, OperandInfo341 },	// Inst #3177 = VQRSHLsv2i64
	{ 5, OperandInfo340 },	// Inst #3178 = VQRSHLsv4i16
	{ 5, OperandInfo341 },	// Inst #3179 = VQRSHLsv4i32
	{ 5, OperandInfo341 },	// Inst #3180 = VQRSHLsv8i16
	{ 5, OperandInfo340 },	// Inst #3181 = VQRSHLsv8i8
	{ 5, OperandInfo341 },	// Inst #3182 = VQRSHLuv16i8
	{ 5, OperandInfo340 },	// Inst #3183 = VQRSHLuv1i64
	{ 5, OperandInfo340 },	// Inst #3184 = VQRSHLuv2i32
	{ 5, OperandInfo341 },	// Inst #3185 = VQRSHLuv2i64
	{ 5, OperandInfo340 },	// Inst #3186 = VQRSHLuv4i16
	{ 5, OperandInfo341 },	// Inst #3187 = VQRSHLuv4i32
	{ 5, OperandInfo341 },	// Inst #3188 = VQRSHLuv8i16
	{ 5, OperandInfo340 },	// Inst #3189 = VQRSHLuv8i8
	{ 5, OperandInfo456 },	// Inst #3190 = VQRSHRNsv2i32
	{ 5, OperandInfo456 },	// Inst #3191 = VQRSHRNsv4i16
	{ 5, OperandInfo456 },	// Inst #3192 = VQRSHRNsv8i8
	{ 5, OperandInfo456 },	// Inst #3193 = VQRSHRNuv2i32
	{ 5, OperandInfo456 },	// Inst #3194 = VQRSHRNuv4i16
	{ 5, OperandInfo456 },	// Inst #3195 = VQRSHRNuv8i8
	{ 5, OperandInfo456 },	// Inst #3196 = VQRSHRUNv2i32
	{ 5, OperandInfo456 },	// Inst #3197 = VQRSHRUNv4i16
	{ 5, OperandInfo456 },	// Inst #3198 = VQRSHRUNv8i8
	{ 5, OperandInfo457 },	// Inst #3199 = VQSHLsiv16i8
	{ 5, OperandInfo458 },	// Inst #3200 = VQSHLsiv1i64
	{ 5, OperandInfo458 },	// Inst #3201 = VQSHLsiv2i32
	{ 5, OperandInfo457 },	// Inst #3202 = VQSHLsiv2i64
	{ 5, OperandInfo458 },	// Inst #3203 = VQSHLsiv4i16
	{ 5, OperandInfo457 },	// Inst #3204 = VQSHLsiv4i32
	{ 5, OperandInfo457 },	// Inst #3205 = VQSHLsiv8i16
	{ 5, OperandInfo458 },	// Inst #3206 = VQSHLsiv8i8
	{ 5, OperandInfo457 },	// Inst #3207 = VQSHLsuv16i8
	{ 5, OperandInfo458 },	// Inst #3208 = VQSHLsuv1i64
	{ 5, OperandInfo458 },	// Inst #3209 = VQSHLsuv2i32
	{ 5, OperandInfo457 },	// Inst #3210 = VQSHLsuv2i64
	{ 5, OperandInfo458 },	// Inst #3211 = VQSHLsuv4i16
	{ 5, OperandInfo457 },	// Inst #3212 = VQSHLsuv4i32
	{ 5, OperandInfo457 },	// Inst #3213 = VQSHLsuv8i16
	{ 5, OperandInfo458 },	// Inst #3214 = VQSHLsuv8i8
	{ 5, OperandInfo341 },	// Inst #3215 = VQSHLsv16i8
	{ 5, OperandInfo340 },	// Inst #3216 = VQSHLsv1i64
	{ 5, OperandInfo340 },	// Inst #3217 = VQSHLsv2i32
	{ 5, OperandInfo341 },	// Inst #3218 = VQSHLsv2i64
	{ 5, OperandInfo340 },	// Inst #3219 = VQSHLsv4i16
	{ 5, OperandInfo341 },	// Inst #3220 = VQSHLsv4i32
	{ 5, OperandInfo341 },	// Inst #3221 = VQSHLsv8i16
	{ 5, OperandInfo340 },	// Inst #3222 = VQSHLsv8i8
	{ 5, OperandInfo457 },	// Inst #3223 = VQSHLuiv16i8
	{ 5, OperandInfo458 },	// Inst #3224 = VQSHLuiv1i64
	{ 5, OperandInfo458 },	// Inst #3225 = VQSHLuiv2i32
	{ 5, OperandInfo457 },	// Inst #3226 = VQSHLuiv2i64
	{ 5, OperandInfo458 },	// Inst #3227 = VQSHLuiv4i16
	{ 5, OperandInfo457 },	// Inst #3228 = VQSHLuiv4i32
	{ 5, OperandInfo457 },	// Inst #3229 = VQSHLuiv8i16
	{ 5, OperandInfo458 },	// Inst #3230 = VQSHLuiv8i8
	{ 5, OperandInfo341 },	// Inst #3231 = VQSHLuv16i8
	{ 5, OperandInfo340 },	// Inst #3232 = VQSHLuv1i64
	{ 5, OperandInfo340 },	// Inst #3233 = VQSHLuv2i32
	{ 5, OperandInfo341 },	// Inst #3234 = VQSHLuv2i64
	{ 5, OperandInfo340 },	// Inst #3235 = VQSHLuv4i16
	{ 5, OperandInfo341 },	// Inst #3236 = VQSHLuv4i32
	{ 5, OperandInfo341 },	// Inst #3237 = VQSHLuv8i16
	{ 5, OperandInfo340 },	// Inst #3238 = VQSHLuv8i8
	{ 5, OperandInfo456 },	// Inst #3239 = VQSHRNsv2i32
	{ 5, OperandInfo456 },	// Inst #3240 = VQSHRNsv4i16
	{ 5, OperandInfo456 },	// Inst #3241 = VQSHRNsv8i8
	{ 5, OperandInfo456 },	// Inst #3242 = VQSHRNuv2i32
	{ 5, OperandInfo456 },	// Inst #3243 = VQSHRNuv4i16
	{ 5, OperandInfo456 },	// Inst #3244 = VQSHRNuv8i8
	{ 5, OperandInfo456 },	// Inst #3245 = VQSHRUNv2i32
	{ 5, OperandInfo456 },	// Inst #3246 = VQSHRUNv4i16
	{ 5, OperandInfo456 },	// Inst #3247 = VQSHRUNv8i8
	{ 5, OperandInfo341 },	// Inst #3248 = VQSUBsv16i8
	{ 5, OperandInfo340 },	// Inst #3249 = VQSUBsv1i64
	{ 5, OperandInfo340 },	// Inst #3250 = VQSUBsv2i32
	{ 5, OperandInfo341 },	// Inst #3251 = VQSUBsv2i64
	{ 5, OperandInfo340 },	// Inst #3252 = VQSUBsv4i16
	{ 5, OperandInfo341 },	// Inst #3253 = VQSUBsv4i32
	{ 5, OperandInfo341 },	// Inst #3254 = VQSUBsv8i16
	{ 5, OperandInfo340 },	// Inst #3255 = VQSUBsv8i8
	{ 5, OperandInfo341 },	// Inst #3256 = VQSUBuv16i8
	{ 5, OperandInfo340 },	// Inst #3257 = VQSUBuv1i64
	{ 5, OperandInfo340 },	// Inst #3258 = VQSUBuv2i32
	{ 5, OperandInfo341 },	// Inst #3259 = VQSUBuv2i64
	{ 5, OperandInfo340 },	// Inst #3260 = VQSUBuv4i16
	{ 5, OperandInfo341 },	// Inst #3261 = VQSUBuv4i32
	{ 5, OperandInfo341 },	// Inst #3262 = VQSUBuv8i16
	{ 5, OperandInfo340 },	// Inst #3263 = VQSUBuv8i8
	{ 5, OperandInfo347 },	// Inst #3264 = VRADDHNv2i32
	{ 5, OperandInfo347 },	// Inst #3265 = VRADDHNv4i16
	{ 5, OperandInfo347 },	// Inst #3266 = VRADDHNv8i8
	{ 4, OperandInfo342 },	// Inst #3267 = VRECPEd
	{ 4, OperandInfo342 },	// Inst #3268 = VRECPEfd
	{ 4, OperandInfo345 },	// Inst #3269 = VRECPEfq
	{ 4, OperandInfo342 },	// Inst #3270 = VRECPEhd
	{ 4, OperandInfo345 },	// Inst #3271 = VRECPEhq
	{ 4, OperandInfo345 },	// Inst #3272 = VRECPEq
	{ 5, OperandInfo340 },	// Inst #3273 = VRECPSfd
	{ 5, OperandInfo341 },	// Inst #3274 = VRECPSfq
	{ 5, OperandInfo340 },	// Inst #3275 = VRECPShd
	{ 5, OperandInfo341 },	// Inst #3276 = VRECPShq
	{ 4, OperandInfo342 },	// Inst #3277 = VREV16d8
	{ 4, OperandInfo345 },	// Inst #3278 = VREV16q8
	{ 4, OperandInfo342 },	// Inst #3279 = VREV32d16
	{ 4, OperandInfo342 },	// Inst #3280 = VREV32d8
	{ 4, OperandInfo345 },	// Inst #3281 = VREV32q16
	{ 4, OperandInfo345 },	// Inst #3282 = VREV32q8
	{ 4, OperandInfo342 },	// Inst #3283 = VREV64d16
	{ 4, OperandInfo342 },	// Inst #3284 = VREV64d32
	{ 4, OperandInfo342 },	// Inst #3285 = VREV64d8
	{ 4, OperandInfo345 },	// Inst #3286 = VREV64q16
	{ 4, OperandInfo345 },	// Inst #3287 = VREV64q32
	{ 4, OperandInfo345 },	// Inst #3288 = VREV64q8
	{ 5, OperandInfo341 },	// Inst #3289 = VRHADDsv16i8
	{ 5, OperandInfo340 },	// Inst #3290 = VRHADDsv2i32
	{ 5, OperandInfo340 },	// Inst #3291 = VRHADDsv4i16
	{ 5, OperandInfo341 },	// Inst #3292 = VRHADDsv4i32
	{ 5, OperandInfo341 },	// Inst #3293 = VRHADDsv8i16
	{ 5, OperandInfo340 },	// Inst #3294 = VRHADDsv8i8
	{ 5, OperandInfo341 },	// Inst #3295 = VRHADDuv16i8
	{ 5, OperandInfo340 },	// Inst #3296 = VRHADDuv2i32
	{ 5, OperandInfo340 },	// Inst #3297 = VRHADDuv4i16
	{ 5, OperandInfo341 },	// Inst #3298 = VRHADDuv4i32
	{ 5, OperandInfo341 },	// Inst #3299 = VRHADDuv8i16
	{ 5, OperandInfo340 },	// Inst #3300 = VRHADDuv8i8
	{ 2, OperandInfo366 },	// Inst #3301 = VRINTAD
	{ 2, OperandInfo459 },	// Inst #3302 = VRINTAH
	{ 2, OperandInfo366 },	// Inst #3303 = VRINTANDf
	{ 2, OperandInfo366 },	// Inst #3304 = VRINTANDh
	{ 2, OperandInfo158 },	// Inst #3305 = VRINTANQf
	{ 2, OperandInfo158 },	// Inst #3306 = VRINTANQh
	{ 2, OperandInfo369 },	// Inst #3307 = VRINTAS
	{ 2, OperandInfo366 },	// Inst #3308 = VRINTMD
	{ 2, OperandInfo459 },	// Inst #3309 = VRINTMH
	{ 2, OperandInfo366 },	// Inst #3310 = VRINTMNDf
	{ 2, OperandInfo366 },	// Inst #3311 = VRINTMNDh
	{ 2, OperandInfo158 },	// Inst #3312 = VRINTMNQf
	{ 2, OperandInfo158 },	// Inst #3313 = VRINTMNQh
	{ 2, OperandInfo369 },	// Inst #3314 = VRINTMS
	{ 2, OperandInfo366 },	// Inst #3315 = VRINTND
	{ 2, OperandInfo459 },	// Inst #3316 = VRINTNH
	{ 2, OperandInfo366 },	// Inst #3317 = VRINTNNDf
	{ 2, OperandInfo366 },	// Inst #3318 = VRINTNNDh
	{ 2, OperandInfo158 },	// Inst #3319 = VRINTNNQf
	{ 2, OperandInfo158 },	// Inst #3320 = VRINTNNQh
	{ 2, OperandInfo369 },	// Inst #3321 = VRINTNS
	{ 2, OperandInfo366 },	// Inst #3322 = VRINTPD
	{ 2, OperandInfo459 },	// Inst #3323 = VRINTPH
	{ 2, OperandInfo366 },	// Inst #3324 = VRINTPNDf
	{ 2, OperandInfo366 },	// Inst #3325 = VRINTPNDh
	{ 2, OperandInfo158 },	// Inst #3326 = VRINTPNQf
	{ 2, OperandInfo158 },	// Inst #3327 = VRINTPNQh
	{ 2, OperandInfo369 },	// Inst #3328 = VRINTPS
	{ 4, OperandInfo342 },	// Inst #3329 = VRINTRD
	{ 4, OperandInfo343 },	// Inst #3330 = VRINTRH
	{ 4, OperandInfo344 },	// Inst #3331 = VRINTRS
	{ 4, OperandInfo342 },	// Inst #3332 = VRINTXD
	{ 4, OperandInfo343 },	// Inst #3333 = VRINTXH
	{ 2, OperandInfo366 },	// Inst #3334 = VRINTXNDf
	{ 2, OperandInfo366 },	// Inst #3335 = VRINTXNDh
	{ 2, OperandInfo158 },	// Inst #3336 = VRINTXNQf
	{ 2, OperandInfo158 },	// Inst #3337 = VRINTXNQh
	{ 4, OperandInfo344 },	// Inst #3338 = VRINTXS
	{ 4, OperandInfo342 },	// Inst #3339 = VRINTZD
	{ 4, OperandInfo343 },	// Inst #3340 = VRINTZH
	{ 2, OperandInfo366 },	// Inst #3341 = VRINTZNDf
	{ 2, OperandInfo366 },	// Inst #3342 = VRINTZNDh
	{ 2, OperandInfo158 },	// Inst #3343 = VRINTZNQf
	{ 2, OperandInfo158 },	// Inst #3344 = VRINTZNQh
	{ 4, OperandInfo344 },	// Inst #3345 = VRINTZS
	{ 5, OperandInfo341 },	// Inst #3346 = VRSHLsv16i8
	{ 5, OperandInfo340 },	// Inst #3347 = VRSHLsv1i64
	{ 5, OperandInfo340 },	// Inst #3348 = VRSHLsv2i32
	{ 5, OperandInfo341 },	// Inst #3349 = VRSHLsv2i64
	{ 5, OperandInfo340 },	// Inst #3350 = VRSHLsv4i16
	{ 5, OperandInfo341 },	// Inst #3351 = VRSHLsv4i32
	{ 5, OperandInfo341 },	// Inst #3352 = VRSHLsv8i16
	{ 5, OperandInfo340 },	// Inst #3353 = VRSHLsv8i8
	{ 5, OperandInfo341 },	// Inst #3354 = VRSHLuv16i8
	{ 5, OperandInfo340 },	// Inst #3355 = VRSHLuv1i64
	{ 5, OperandInfo340 },	// Inst #3356 = VRSHLuv2i32
	{ 5, OperandInfo341 },	// Inst #3357 = VRSHLuv2i64
	{ 5, OperandInfo340 },	// Inst #3358 = VRSHLuv4i16
	{ 5, OperandInfo341 },	// Inst #3359 = VRSHLuv4i32
	{ 5, OperandInfo341 },	// Inst #3360 = VRSHLuv8i16
	{ 5, OperandInfo340 },	// Inst #3361 = VRSHLuv8i8
	{ 5, OperandInfo456 },	// Inst #3362 = VRSHRNv2i32
	{ 5, OperandInfo456 },	// Inst #3363 = VRSHRNv4i16
	{ 5, OperandInfo456 },	// Inst #3364 = VRSHRNv8i8
	{ 5, OperandInfo374 },	// Inst #3365 = VRSHRsv16i8
	{ 5, OperandInfo373 },	// Inst #3366 = VRSHRsv1i64
	{ 5, OperandInfo373 },	// Inst #3367 = VRSHRsv2i32
	{ 5, OperandInfo374 },	// Inst #3368 = VRSHRsv2i64
	{ 5, OperandInfo373 },	// Inst #3369 = VRSHRsv4i16
	{ 5, OperandInfo374 },	// Inst #3370 = VRSHRsv4i32
	{ 5, OperandInfo374 },	// Inst #3371 = VRSHRsv8i16
	{ 5, OperandInfo373 },	// Inst #3372 = VRSHRsv8i8
	{ 5, OperandInfo374 },	// Inst #3373 = VRSHRuv16i8
	{ 5, OperandInfo373 },	// Inst #3374 = VRSHRuv1i64
	{ 5, OperandInfo373 },	// Inst #3375 = VRSHRuv2i32
	{ 5, OperandInfo374 },	// Inst #3376 = VRSHRuv2i64
	{ 5, OperandInfo373 },	// Inst #3377 = VRSHRuv4i16
	{ 5, OperandInfo374 },	// Inst #3378 = VRSHRuv4i32
	{ 5, OperandInfo374 },	// Inst #3379 = VRSHRuv8i16
	{ 5, OperandInfo373 },	// Inst #3380 = VRSHRuv8i8
	{ 4, OperandInfo342 },	// Inst #3381 = VRSQRTEd
	{ 4, OperandInfo342 },	// Inst #3382 = VRSQRTEfd
	{ 4, OperandInfo345 },	// Inst #3383 = VRSQRTEfq
	{ 4, OperandInfo342 },	// Inst #3384 = VRSQRTEhd
	{ 4, OperandInfo345 },	// Inst #3385 = VRSQRTEhq
	{ 4, OperandInfo345 },	// Inst #3386 = VRSQRTEq
	{ 5, OperandInfo340 },	// Inst #3387 = VRSQRTSfd
	{ 5, OperandInfo341 },	// Inst #3388 = VRSQRTSfq
	{ 5, OperandInfo340 },	// Inst #3389 = VRSQRTShd
	{ 5, OperandInfo341 },	// Inst #3390 = VRSQRTShq
	{ 6, OperandInfo460 },	// Inst #3391 = VRSRAsv16i8
	{ 6, OperandInfo461 },	// Inst #3392 = VRSRAsv1i64
	{ 6, OperandInfo461 },	// Inst #3393 = VRSRAsv2i32
	{ 6, OperandInfo460 },	// Inst #3394 = VRSRAsv2i64
	{ 6, OperandInfo461 },	// Inst #3395 = VRSRAsv4i16
	{ 6, OperandInfo460 },	// Inst #3396 = VRSRAsv4i32
	{ 6, OperandInfo460 },	// Inst #3397 = VRSRAsv8i16
	{ 6, OperandInfo461 },	// Inst #3398 = VRSRAsv8i8
	{ 6, OperandInfo460 },	// Inst #3399 = VRSRAuv16i8
	{ 6, OperandInfo461 },	// Inst #3400 = VRSRAuv1i64
	{ 6, OperandInfo461 },	// Inst #3401 = VRSRAuv2i32
	{ 6, OperandInfo460 },	// Inst #3402 = VRSRAuv2i64
	{ 6, OperandInfo461 },	// Inst #3403 = VRSRAuv4i16
	{ 6, OperandInfo460 },	// Inst #3404 = VRSRAuv4i32
	{ 6, OperandInfo460 },	// Inst #3405 = VRSRAuv8i16
	{ 6, OperandInfo461 },	// Inst #3406 = VRSRAuv8i8
	{ 5, OperandInfo347 },	// Inst #3407 = VRSUBHNv2i32
	{ 5, OperandInfo347 },	// Inst #3408 = VRSUBHNv4i16
	{ 5, OperandInfo347 },	// Inst #3409 = VRSUBHNv8i8
	{ 3, OperandInfo150 },	// Inst #3410 = VSCCLRMD
	{ 3, OperandInfo150 },	// Inst #3411 = VSCCLRMS
	{ 4, OperandInfo161 },	// Inst #3412 = VSDOTD
	{ 5, OperandInfo159 },	// Inst #3413 = VSDOTDI
	{ 4, OperandInfo162 },	// Inst #3414 = VSDOTQ
	{ 5, OperandInfo160 },	// Inst #3415 = VSDOTQI
	{ 3, OperandInfo310 },	// Inst #3416 = VSELEQD
	{ 3, OperandInfo387 },	// Inst #3417 = VSELEQH
	{ 3, OperandInfo388 },	// Inst #3418 = VSELEQS
	{ 3, OperandInfo310 },	// Inst #3419 = VSELGED
	{ 3, OperandInfo387 },	// Inst #3420 = VSELGEH
	{ 3, OperandInfo388 },	// Inst #3421 = VSELGES
	{ 3, OperandInfo310 },	// Inst #3422 = VSELGTD
	{ 3, OperandInfo387 },	// Inst #3423 = VSELGTH
	{ 3, OperandInfo388 },	// Inst #3424 = VSELGTS
	{ 3, OperandInfo310 },	// Inst #3425 = VSELVSD
	{ 3, OperandInfo387 },	// Inst #3426 = VSELVSH
	{ 3, OperandInfo388 },	// Inst #3427 = VSELVSS
	{ 6, OperandInfo462 },	// Inst #3428 = VSETLNi16
	{ 6, OperandInfo462 },	// Inst #3429 = VSETLNi32
	{ 6, OperandInfo462 },	// Inst #3430 = VSETLNi8
	{ 5, OperandInfo378 },	// Inst #3431 = VSHLLi16
	{ 5, OperandInfo378 },	// Inst #3432 = VSHLLi32
	{ 5, OperandInfo378 },	// Inst #3433 = VSHLLi8
	{ 5, OperandInfo378 },	// Inst #3434 = VSHLLsv2i64
	{ 5, OperandInfo378 },	// Inst #3435 = VSHLLsv4i32
	{ 5, OperandInfo378 },	// Inst #3436 = VSHLLsv8i16
	{ 5, OperandInfo378 },	// Inst #3437 = VSHLLuv2i64
	{ 5, OperandInfo378 },	// Inst #3438 = VSHLLuv4i32
	{ 5, OperandInfo378 },	// Inst #3439 = VSHLLuv8i16
	{ 5, OperandInfo457 },	// Inst #3440 = VSHLiv16i8
	{ 5, OperandInfo458 },	// Inst #3441 = VSHLiv1i64
	{ 5, OperandInfo458 },	// Inst #3442 = VSHLiv2i32
	{ 5, OperandInfo457 },	// Inst #3443 = VSHLiv2i64
	{ 5, OperandInfo458 },	// Inst #3444 = VSHLiv4i16
	{ 5, OperandInfo457 },	// Inst #3445 = VSHLiv4i32
	{ 5, OperandInfo457 },	// Inst #3446 = VSHLiv8i16
	{ 5, OperandInfo458 },	// Inst #3447 = VSHLiv8i8
	{ 5, OperandInfo341 },	// Inst #3448 = VSHLsv16i8
	{ 5, OperandInfo340 },	// Inst #3449 = VSHLsv1i64
	{ 5, OperandInfo340 },	// Inst #3450 = VSHLsv2i32
	{ 5, OperandInfo341 },	// Inst #3451 = VSHLsv2i64
	{ 5, OperandInfo340 },	// Inst #3452 = VSHLsv4i16
	{ 5, OperandInfo341 },	// Inst #3453 = VSHLsv4i32
	{ 5, OperandInfo341 },	// Inst #3454 = VSHLsv8i16
	{ 5, OperandInfo340 },	// Inst #3455 = VSHLsv8i8
	{ 5, OperandInfo341 },	// Inst #3456 = VSHLuv16i8
	{ 5, OperandInfo340 },	// Inst #3457 = VSHLuv1i64
	{ 5, OperandInfo340 },	// Inst #3458 = VSHLuv2i32
	{ 5, OperandInfo341 },	// Inst #3459 = VSHLuv2i64
	{ 5, OperandInfo340 },	// Inst #3460 = VSHLuv4i16
	{ 5, OperandInfo341 },	// Inst #3461 = VSHLuv4i32
	{ 5, OperandInfo341 },	// Inst #3462 = VSHLuv8i16
	{ 5, OperandInfo340 },	// Inst #3463 = VSHLuv8i8
	{ 5, OperandInfo456 },	// Inst #3464 = VSHRNv2i32
	{ 5, OperandInfo456 },	// Inst #3465 = VSHRNv4i16
	{ 5, OperandInfo456 },	// Inst #3466 = VSHRNv8i8
	{ 5, OperandInfo374 },	// Inst #3467 = VSHRsv16i8
	{ 5, OperandInfo373 },	// Inst #3468 = VSHRsv1i64
	{ 5, OperandInfo373 },	// Inst #3469 = VSHRsv2i32
	{ 5, OperandInfo374 },	// Inst #3470 = VSHRsv2i64
	{ 5, OperandInfo373 },	// Inst #3471 = VSHRsv4i16
	{ 5, OperandInfo374 },	// Inst #3472 = VSHRsv4i32
	{ 5, OperandInfo374 },	// Inst #3473 = VSHRsv8i16
	{ 5, OperandInfo373 },	// Inst #3474 = VSHRsv8i8
	{ 5, OperandInfo374 },	// Inst #3475 = VSHRuv16i8
	{ 5, OperandInfo373 },	// Inst #3476 = VSHRuv1i64
	{ 5, OperandInfo373 },	// Inst #3477 = VSHRuv2i32
	{ 5, OperandInfo374 },	// Inst #3478 = VSHRuv2i64
	{ 5, OperandInfo373 },	// Inst #3479 = VSHRuv4i16
	{ 5, OperandInfo374 },	// Inst #3480 = VSHRuv4i32
	{ 5, OperandInfo374 },	// Inst #3481 = VSHRuv8i16
	{ 5, OperandInfo373 },	// Inst #3482 = VSHRuv8i8
	{ 5, OperandInfo463 },	// Inst #3483 = VSHTOD
	{ 5, OperandInfo464 },	// Inst #3484 = VSHTOH
	{ 5, OperandInfo464 },	// Inst #3485 = VSHTOS
	{ 4, OperandInfo371 },	// Inst #3486 = VSITOD
	{ 4, OperandInfo465 },	// Inst #3487 = VSITOH
	{ 4, OperandInfo344 },	// Inst #3488 = VSITOS
	{ 6, OperandInfo466 },	// Inst #3489 = VSLIv16i8
	{ 6, OperandInfo467 },	// Inst #3490 = VSLIv1i64
	{ 6, OperandInfo467 },	// Inst #3491 = VSLIv2i32
	{ 6, OperandInfo466 },	// Inst #3492 = VSLIv2i64
	{ 6, OperandInfo467 },	// Inst #3493 = VSLIv4i16
	{ 6, OperandInfo466 },	// Inst #3494 = VSLIv4i32
	{ 6, OperandInfo466 },	// Inst #3495 = VSLIv8i16
	{ 6, OperandInfo467 },	// Inst #3496 = VSLIv8i8
	{ 5, OperandInfo463 },	// Inst #3497 = VSLTOD
	{ 5, OperandInfo464 },	// Inst #3498 = VSLTOH
	{ 5, OperandInfo464 },	// Inst #3499 = VSLTOS
	{ 4, OperandInfo162 },	// Inst #3500 = VSMMLA
	{ 4, OperandInfo342 },	// Inst #3501 = VSQRTD
	{ 4, OperandInfo343 },	// Inst #3502 = VSQRTH
	{ 4, OperandInfo344 },	// Inst #3503 = VSQRTS
	{ 6, OperandInfo460 },	// Inst #3504 = VSRAsv16i8
	{ 6, OperandInfo461 },	// Inst #3505 = VSRAsv1i64
	{ 6, OperandInfo461 },	// Inst #3506 = VSRAsv2i32
	{ 6, OperandInfo460 },	// Inst #3507 = VSRAsv2i64
	{ 6, OperandInfo461 },	// Inst #3508 = VSRAsv4i16
	{ 6, OperandInfo460 },	// Inst #3509 = VSRAsv4i32
	{ 6, OperandInfo460 },	// Inst #3510 = VSRAsv8i16
	{ 6, OperandInfo461 },	// Inst #3511 = VSRAsv8i8
	{ 6, OperandInfo460 },	// Inst #3512 = VSRAuv16i8
	{ 6, OperandInfo461 },	// Inst #3513 = VSRAuv1i64
	{ 6, OperandInfo461 },	// Inst #3514 = VSRAuv2i32
	{ 6, OperandInfo460 },	// Inst #3515 = VSRAuv2i64
	{ 6, OperandInfo461 },	// Inst #3516 = VSRAuv4i16
	{ 6, OperandInfo460 },	// Inst #3517 = VSRAuv4i32
	{ 6, OperandInfo460 },	// Inst #3518 = VSRAuv8i16
	{ 6, OperandInfo461 },	// Inst #3519 = VSRAuv8i8
	{ 6, OperandInfo460 },	// Inst #3520 = VSRIv16i8
	{ 6, OperandInfo461 },	// Inst #3521 = VSRIv1i64
	{ 6, OperandInfo461 },	// Inst #3522 = VSRIv2i32
	{ 6, OperandInfo460 },	// Inst #3523 = VSRIv2i64
	{ 6, OperandInfo461 },	// Inst #3524 = VSRIv4i16
	{ 6, OperandInfo460 },	// Inst #3525 = VSRIv4i32
	{ 6, OperandInfo460 },	// Inst #3526 = VSRIv8i16
	{ 6, OperandInfo461 },	// Inst #3527 = VSRIv8i8
	{ 6, OperandInfo468 },	// Inst #3528 = VST1LNd16
	{ 8, OperandInfo469 },	// Inst #3529 = VST1LNd16_UPD
	{ 6, OperandInfo468 },	// Inst #3530 = VST1LNd32
	{ 8, OperandInfo469 },	// Inst #3531 = VST1LNd32_UPD
	{ 6, OperandInfo468 },	// Inst #3532 = VST1LNd8
	{ 8, OperandInfo469 },	// Inst #3533 = VST1LNd8_UPD
	{ 6, OperandInfo470 },	// Inst #3534 = VST1LNq16Pseudo
	{ 8, OperandInfo471 },	// Inst #3535 = VST1LNq16Pseudo_UPD
	{ 6, OperandInfo470 },	// Inst #3536 = VST1LNq32Pseudo
	{ 8, OperandInfo471 },	// Inst #3537 = VST1LNq32Pseudo_UPD
	{ 6, OperandInfo470 },	// Inst #3538 = VST1LNq8Pseudo
	{ 8, OperandInfo471 },	// Inst #3539 = VST1LNq8Pseudo_UPD
	{ 5, OperandInfo472 },	// Inst #3540 = VST1d16
	{ 5, OperandInfo472 },	// Inst #3541 = VST1d16Q
	{ 5, OperandInfo473 },	// Inst #3542 = VST1d16QPseudo
	{ 6, OperandInfo474 },	// Inst #3543 = VST1d16QPseudoWB_fixed
	{ 7, OperandInfo475 },	// Inst #3544 = VST1d16QPseudoWB_register
	{ 6, OperandInfo476 },	// Inst #3545 = VST1d16Qwb_fixed
	{ 7, OperandInfo477 },	// Inst #3546 = VST1d16Qwb_register
	{ 5, OperandInfo472 },	// Inst #3547 = VST1d16T
	{ 5, OperandInfo473 },	// Inst #3548 = VST1d16TPseudo
	{ 6, OperandInfo474 },	// Inst #3549 = VST1d16TPseudoWB_fixed
	{ 7, OperandInfo475 },	// Inst #3550 = VST1d16TPseudoWB_register
	{ 6, OperandInfo476 },	// Inst #3551 = VST1d16Twb_fixed
	{ 7, OperandInfo477 },	// Inst #3552 = VST1d16Twb_register
	{ 6, OperandInfo476 },	// Inst #3553 = VST1d16wb_fixed
	{ 7, OperandInfo477 },	// Inst #3554 = VST1d16wb_register
	{ 5, OperandInfo472 },	// Inst #3555 = VST1d32
	{ 5, OperandInfo472 },	// Inst #3556 = VST1d32Q
	{ 5, OperandInfo473 },	// Inst #3557 = VST1d32QPseudo
	{ 6, OperandInfo474 },	// Inst #3558 = VST1d32QPseudoWB_fixed
	{ 7, OperandInfo475 },	// Inst #3559 = VST1d32QPseudoWB_register
	{ 6, OperandInfo476 },	// Inst #3560 = VST1d32Qwb_fixed
	{ 7, OperandInfo477 },	// Inst #3561 = VST1d32Qwb_register
	{ 5, OperandInfo472 },	// Inst #3562 = VST1d32T
	{ 5, OperandInfo473 },	// Inst #3563 = VST1d32TPseudo
	{ 6, OperandInfo474 },	// Inst #3564 = VST1d32TPseudoWB_fixed
	{ 7, OperandInfo475 },	// Inst #3565 = VST1d32TPseudoWB_register
	{ 6, OperandInfo476 },	// Inst #3566 = VST1d32Twb_fixed
	{ 7, OperandInfo477 },	// Inst #3567 = VST1d32Twb_register
	{ 6, OperandInfo476 },	// Inst #3568 = VST1d32wb_fixed
	{ 7, OperandInfo477 },	// Inst #3569 = VST1d32wb_register
	{ 5, OperandInfo472 },	// Inst #3570 = VST1d64
	{ 5, OperandInfo472 },	// Inst #3571 = VST1d64Q
	{ 5, OperandInfo473 },	// Inst #3572 = VST1d64QPseudo
	{ 6, OperandInfo474 },	// Inst #3573 = VST1d64QPseudoWB_fixed
	{ 7, OperandInfo475 },	// Inst #3574 = VST1d64QPseudoWB_register
	{ 6, OperandInfo476 },	// Inst #3575 = VST1d64Qwb_fixed
	{ 7, OperandInfo477 },	// Inst #3576 = VST1d64Qwb_register
	{ 5, OperandInfo472 },	// Inst #3577 = VST1d64T
	{ 5, OperandInfo473 },	// Inst #3578 = VST1d64TPseudo
	{ 6, OperandInfo474 },	// Inst #3579 = VST1d64TPseudoWB_fixed
	{ 7, OperandInfo475 },	// Inst #3580 = VST1d64TPseudoWB_register
	{ 6, OperandInfo476 },	// Inst #3581 = VST1d64Twb_fixed
	{ 7, OperandInfo477 },	// Inst #3582 = VST1d64Twb_register
	{ 6, OperandInfo476 },	// Inst #3583 = VST1d64wb_fixed
	{ 7, OperandInfo477 },	// Inst #3584 = VST1d64wb_register
	{ 5, OperandInfo472 },	// Inst #3585 = VST1d8
	{ 5, OperandInfo472 },	// Inst #3586 = VST1d8Q
	{ 5, OperandInfo473 },	// Inst #3587 = VST1d8QPseudo
	{ 6, OperandInfo474 },	// Inst #3588 = VST1d8QPseudoWB_fixed
	{ 7, OperandInfo475 },	// Inst #3589 = VST1d8QPseudoWB_register
	{ 6, OperandInfo476 },	// Inst #3590 = VST1d8Qwb_fixed
	{ 7, OperandInfo477 },	// Inst #3591 = VST1d8Qwb_register
	{ 5, OperandInfo472 },	// Inst #3592 = VST1d8T
	{ 5, OperandInfo473 },	// Inst #3593 = VST1d8TPseudo
	{ 6, OperandInfo474 },	// Inst #3594 = VST1d8TPseudoWB_fixed
	{ 7, OperandInfo475 },	// Inst #3595 = VST1d8TPseudoWB_register
	{ 6, OperandInfo476 },	// Inst #3596 = VST1d8Twb_fixed
	{ 7, OperandInfo477 },	// Inst #3597 = VST1d8Twb_register
	{ 6, OperandInfo476 },	// Inst #3598 = VST1d8wb_fixed
	{ 7, OperandInfo477 },	// Inst #3599 = VST1d8wb_register
	{ 5, OperandInfo478 },	// Inst #3600 = VST1q16
	{ 5, OperandInfo479 },	// Inst #3601 = VST1q16HighQPseudo
	{ 7, OperandInfo480 },	// Inst #3602 = VST1q16HighQPseudo_UPD
	{ 5, OperandInfo479 },	// Inst #3603 = VST1q16HighTPseudo
	{ 7, OperandInfo480 },	// Inst #3604 = VST1q16HighTPseudo_UPD
	{ 7, OperandInfo480 },	// Inst #3605 = VST1q16LowQPseudo_UPD
	{ 7, OperandInfo480 },	// Inst #3606 = VST1q16LowTPseudo_UPD
	{ 6, OperandInfo481 },	// Inst #3607 = VST1q16wb_fixed
	{ 7, OperandInfo482 },	// Inst #3608 = VST1q16wb_register
	{ 5, OperandInfo478 },	// Inst #3609 = VST1q32
	{ 5, OperandInfo479 },	// Inst #3610 = VST1q32HighQPseudo
	{ 7, OperandInfo480 },	// Inst #3611 = VST1q32HighQPseudo_UPD
	{ 5, OperandInfo479 },	// Inst #3612 = VST1q32HighTPseudo
	{ 7, OperandInfo480 },	// Inst #3613 = VST1q32HighTPseudo_UPD
	{ 7, OperandInfo480 },	// Inst #3614 = VST1q32LowQPseudo_UPD
	{ 7, OperandInfo480 },	// Inst #3615 = VST1q32LowTPseudo_UPD
	{ 6, OperandInfo481 },	// Inst #3616 = VST1q32wb_fixed
	{ 7, OperandInfo482 },	// Inst #3617 = VST1q32wb_register
	{ 5, OperandInfo478 },	// Inst #3618 = VST1q64
	{ 5, OperandInfo479 },	// Inst #3619 = VST1q64HighQPseudo
	{ 7, OperandInfo480 },	// Inst #3620 = VST1q64HighQPseudo_UPD
	{ 5, OperandInfo479 },	// Inst #3621 = VST1q64HighTPseudo
	{ 7, OperandInfo480 },	// Inst #3622 = VST1q64HighTPseudo_UPD
	{ 7, OperandInfo480 },	// Inst #3623 = VST1q64LowQPseudo_UPD
	{ 7, OperandInfo480 },	// Inst #3624 = VST1q64LowTPseudo_UPD
	{ 6, OperandInfo481 },	// Inst #3625 = VST1q64wb_fixed
	{ 7, OperandInfo482 },	// Inst #3626 = VST1q64wb_register
	{ 5, OperandInfo478 },	// Inst #3627 = VST1q8
	{ 5, OperandInfo479 },	// Inst #3628 = VST1q8HighQPseudo
	{ 7, OperandInfo480 },	// Inst #3629 = VST1q8HighQPseudo_UPD
	{ 5, OperandInfo479 },	// Inst #3630 = VST1q8HighTPseudo
	{ 7, OperandInfo480 },	// Inst #3631 = VST1q8HighTPseudo_UPD
	{ 7, OperandInfo480 },	// Inst #3632 = VST1q8LowQPseudo_UPD
	{ 7, OperandInfo480 },	// Inst #3633 = VST1q8LowTPseudo_UPD
	{ 6, OperandInfo481 },	// Inst #3634 = VST1q8wb_fixed
	{ 7, OperandInfo482 },	// Inst #3635 = VST1q8wb_register
	{ 7, OperandInfo483 },	// Inst #3636 = VST2LNd16
	{ 6, OperandInfo470 },	// Inst #3637 = VST2LNd16Pseudo
	{ 8, OperandInfo471 },	// Inst #3638 = VST2LNd16Pseudo_UPD
	{ 9, OperandInfo484 },	// Inst #3639 = VST2LNd16_UPD
	{ 7, OperandInfo483 },	// Inst #3640 = VST2LNd32
	{ 6, OperandInfo470 },	// Inst #3641 = VST2LNd32Pseudo
	{ 8, OperandInfo471 },	// Inst #3642 = VST2LNd32Pseudo_UPD
	{ 9, OperandInfo484 },	// Inst #3643 = VST2LNd32_UPD
	{ 7, OperandInfo483 },	// Inst #3644 = VST2LNd8
	{ 6, OperandInfo470 },	// Inst #3645 = VST2LNd8Pseudo
	{ 8, OperandInfo471 },	// Inst #3646 = VST2LNd8Pseudo_UPD
	{ 9, OperandInfo484 },	// Inst #3647 = VST2LNd8_UPD
	{ 7, OperandInfo483 },	// Inst #3648 = VST2LNq16
	{ 6, OperandInfo485 },	// Inst #3649 = VST2LNq16Pseudo
	{ 8, OperandInfo486 },	// Inst #3650 = VST2LNq16Pseudo_UPD
	{ 9, OperandInfo484 },	// Inst #3651 = VST2LNq16_UPD
	{ 7, OperandInfo483 },	// Inst #3652 = VST2LNq32
	{ 6, OperandInfo485 },	// Inst #3653 = VST2LNq32Pseudo
	{ 8, OperandInfo486 },	// Inst #3654 = VST2LNq32Pseudo_UPD
	{ 9, OperandInfo484 },	// Inst #3655 = VST2LNq32_UPD
	{ 5, OperandInfo478 },	// Inst #3656 = VST2b16
	{ 6, OperandInfo481 },	// Inst #3657 = VST2b16wb_fixed
	{ 7, OperandInfo482 },	// Inst #3658 = VST2b16wb_register
	{ 5, OperandInfo478 },	// Inst #3659 = VST2b32
	{ 6, OperandInfo481 },	// Inst #3660 = VST2b32wb_fixed
	{ 7, OperandInfo482 },	// Inst #3661 = VST2b32wb_register
	{ 5, OperandInfo478 },	// Inst #3662 = VST2b8
	{ 6, OperandInfo481 },	// Inst #3663 = VST2b8wb_fixed
	{ 7, OperandInfo482 },	// Inst #3664 = VST2b8wb_register
	{ 5, OperandInfo478 },	// Inst #3665 = VST2d16
	{ 6, OperandInfo481 },	// Inst #3666 = VST2d16wb_fixed
	{ 7, OperandInfo482 },	// Inst #3667 = VST2d16wb_register
	{ 5, OperandInfo478 },	// Inst #3668 = VST2d32
	{ 6, OperandInfo481 },	// Inst #3669 = VST2d32wb_fixed
	{ 7, OperandInfo482 },	// Inst #3670 = VST2d32wb_register
	{ 5, OperandInfo478 },	// Inst #3671 = VST2d8
	{ 6, OperandInfo481 },	// Inst #3672 = VST2d8wb_fixed
	{ 7, OperandInfo482 },	// Inst #3673 = VST2d8wb_register
	{ 5, OperandInfo472 },	// Inst #3674 = VST2q16
	{ 5, OperandInfo473 },	// Inst #3675 = VST2q16Pseudo
	{ 6, OperandInfo474 },	// Inst #3676 = VST2q16PseudoWB_fixed
	{ 7, OperandInfo487 },	// Inst #3677 = VST2q16PseudoWB_register
	{ 6, OperandInfo476 },	// Inst #3678 = VST2q16wb_fixed
	{ 7, OperandInfo477 },	// Inst #3679 = VST2q16wb_register
	{ 5, OperandInfo472 },	// Inst #3680 = VST2q32
	{ 5, OperandInfo473 },	// Inst #3681 = VST2q32Pseudo
	{ 6, OperandInfo474 },	// Inst #3682 = VST2q32PseudoWB_fixed
	{ 7, OperandInfo487 },	// Inst #3683 = VST2q32PseudoWB_register
	{ 6, OperandInfo476 },	// Inst #3684 = VST2q32wb_fixed
	{ 7, OperandInfo477 },	// Inst #3685 = VST2q32wb_register
	{ 5, OperandInfo472 },	// Inst #3686 = VST2q8
	{ 5, OperandInfo473 },	// Inst #3687 = VST2q8Pseudo
	{ 6, OperandInfo474 },	// Inst #3688 = VST2q8PseudoWB_fixed
	{ 7, OperandInfo487 },	// Inst #3689 = VST2q8PseudoWB_register
	{ 6, OperandInfo476 },	// Inst #3690 = VST2q8wb_fixed
	{ 7, OperandInfo477 },	// Inst #3691 = VST2q8wb_register
	{ 8, OperandInfo488 },	// Inst #3692 = VST3LNd16
	{ 6, OperandInfo485 },	// Inst #3693 = VST3LNd16Pseudo
	{ 8, OperandInfo486 },	// Inst #3694 = VST3LNd16Pseudo_UPD
	{ 10, OperandInfo489 }, // Inst #3695 = VST3LNd16_UPD
	{ 8, OperandInfo488 },	// Inst #3696 = VST3LNd32
	{ 6, OperandInfo485 },	// Inst #3697 = VST3LNd32Pseudo
	{ 8, OperandInfo486 },	// Inst #3698 = VST3LNd32Pseudo_UPD
	{ 10, OperandInfo489 }, // Inst #3699 = VST3LNd32_UPD
	{ 8, OperandInfo488 },	// Inst #3700 = VST3LNd8
	{ 6, OperandInfo485 },	// Inst #3701 = VST3LNd8Pseudo
	{ 8, OperandInfo486 },	// Inst #3702 = VST3LNd8Pseudo_UPD
	{ 10, OperandInfo489 }, // Inst #3703 = VST3LNd8_UPD
	{ 8, OperandInfo488 },	// Inst #3704 = VST3LNq16
	{ 6, OperandInfo490 },	// Inst #3705 = VST3LNq16Pseudo
	{ 8, OperandInfo491 },	// Inst #3706 = VST3LNq16Pseudo_UPD
	{ 10, OperandInfo489 }, // Inst #3707 = VST3LNq16_UPD
	{ 8, OperandInfo488 },	// Inst #3708 = VST3LNq32
	{ 6, OperandInfo490 },	// Inst #3709 = VST3LNq32Pseudo
	{ 8, OperandInfo491 },	// Inst #3710 = VST3LNq32Pseudo_UPD
	{ 10, OperandInfo489 }, // Inst #3711 = VST3LNq32_UPD
	{ 7, OperandInfo492 },	// Inst #3712 = VST3d16
	{ 5, OperandInfo473 },	// Inst #3713 = VST3d16Pseudo
	{ 7, OperandInfo475 },	// Inst #3714 = VST3d16Pseudo_UPD
	{ 9, OperandInfo493 },	// Inst #3715 = VST3d16_UPD
	{ 7, OperandInfo492 },	// Inst #3716 = VST3d32
	{ 5, OperandInfo473 },	// Inst #3717 = VST3d32Pseudo
	{ 7, OperandInfo475 },	// Inst #3718 = VST3d32Pseudo_UPD
	{ 9, OperandInfo493 },	// Inst #3719 = VST3d32_UPD
	{ 7, OperandInfo492 },	// Inst #3720 = VST3d8
	{ 5, OperandInfo473 },	// Inst #3721 = VST3d8Pseudo
	{ 7, OperandInfo475 },	// Inst #3722 = VST3d8Pseudo_UPD
	{ 9, OperandInfo493 },	// Inst #3723 = VST3d8_UPD
	{ 7, OperandInfo492 },	// Inst #3724 = VST3q16
	{ 7, OperandInfo480 },	// Inst #3725 = VST3q16Pseudo_UPD
	{ 9, OperandInfo493 },	// Inst #3726 = VST3q16_UPD
	{ 5, OperandInfo479 },	// Inst #3727 = VST3q16oddPseudo
	{ 7, OperandInfo480 },	// Inst #3728 = VST3q16oddPseudo_UPD
	{ 7, OperandInfo492 },	// Inst #3729 = VST3q32
	{ 7, OperandInfo480 },	// Inst #3730 = VST3q32Pseudo_UPD
	{ 9, OperandInfo493 },	// Inst #3731 = VST3q32_UPD
	{ 5, OperandInfo479 },	// Inst #3732 = VST3q32oddPseudo
	{ 7, OperandInfo480 },	// Inst #3733 = VST3q32oddPseudo_UPD
	{ 7, OperandInfo492 },	// Inst #3734 = VST3q8
	{ 7, OperandInfo480 },	// Inst #3735 = VST3q8Pseudo_UPD
	{ 9, OperandInfo493 },	// Inst #3736 = VST3q8_UPD
	{ 5, OperandInfo479 },	// Inst #3737 = VST3q8oddPseudo
	{ 7, OperandInfo480 },	// Inst #3738 = VST3q8oddPseudo_UPD
	{ 9, OperandInfo494 },	// Inst #3739 = VST4LNd16
	{ 6, OperandInfo485 },	// Inst #3740 = VST4LNd16Pseudo
	{ 8, OperandInfo486 },	// Inst #3741 = VST4LNd16Pseudo_UPD
	{ 11, OperandInfo495 }, // Inst #3742 = VST4LNd16_UPD
	{ 9, OperandInfo494 },	// Inst #3743 = VST4LNd32
	{ 6, OperandInfo485 },	// Inst #3744 = VST4LNd32Pseudo
	{ 8, OperandInfo486 },	// Inst #3745 = VST4LNd32Pseudo_UPD
	{ 11, OperandInfo495 }, // Inst #3746 = VST4LNd32_UPD
	{ 9, OperandInfo494 },	// Inst #3747 = VST4LNd8
	{ 6, OperandInfo485 },	// Inst #3748 = VST4LNd8Pseudo
	{ 8, OperandInfo486 },	// Inst #3749 = VST4LNd8Pseudo_UPD
	{ 11, OperandInfo495 }, // Inst #3750 = VST4LNd8_UPD
	{ 9, OperandInfo494 },	// Inst #3751 = VST4LNq16
	{ 6, OperandInfo490 },	// Inst #3752 = VST4LNq16Pseudo
	{ 8, OperandInfo491 },	// Inst #3753 = VST4LNq16Pseudo_UPD
	{ 11, OperandInfo495 }, // Inst #3754 = VST4LNq16_UPD
	{ 9, OperandInfo494 },	// Inst #3755 = VST4LNq32
	{ 6, OperandInfo490 },	// Inst #3756 = VST4LNq32Pseudo
	{ 8, OperandInfo491 },	// Inst #3757 = VST4LNq32Pseudo_UPD
	{ 11, OperandInfo495 }, // Inst #3758 = VST4LNq32_UPD
	{ 8, OperandInfo496 },	// Inst #3759 = VST4d16
	{ 5, OperandInfo473 },	// Inst #3760 = VST4d16Pseudo
	{ 7, OperandInfo475 },	// Inst #3761 = VST4d16Pseudo_UPD
	{ 10, OperandInfo497 }, // Inst #3762 = VST4d16_UPD
	{ 8, OperandInfo496 },	// Inst #3763 = VST4d32
	{ 5, OperandInfo473 },	// Inst #3764 = VST4d32Pseudo
	{ 7, OperandInfo475 },	// Inst #3765 = VST4d32Pseudo_UPD
	{ 10, OperandInfo497 }, // Inst #3766 = VST4d32_UPD
	{ 8, OperandInfo496 },	// Inst #3767 = VST4d8
	{ 5, OperandInfo473 },	// Inst #3768 = VST4d8Pseudo
	{ 7, OperandInfo475 },	// Inst #3769 = VST4d8Pseudo_UPD
	{ 10, OperandInfo497 }, // Inst #3770 = VST4d8_UPD
	{ 8, OperandInfo496 },	// Inst #3771 = VST4q16
	{ 7, OperandInfo480 },	// Inst #3772 = VST4q16Pseudo_UPD
	{ 10, OperandInfo497 }, // Inst #3773 = VST4q16_UPD
	{ 5, OperandInfo479 },	// Inst #3774 = VST4q16oddPseudo
	{ 7, OperandInfo480 },	// Inst #3775 = VST4q16oddPseudo_UPD
	{ 8, OperandInfo496 },	// Inst #3776 = VST4q32
	{ 7, OperandInfo480 },	// Inst #3777 = VST4q32Pseudo_UPD
	{ 10, OperandInfo497 }, // Inst #3778 = VST4q32_UPD
	{ 5, OperandInfo479 },	// Inst #3779 = VST4q32oddPseudo
	{ 7, OperandInfo480 },	// Inst #3780 = VST4q32oddPseudo_UPD
	{ 8, OperandInfo496 },	// Inst #3781 = VST4q8
	{ 7, OperandInfo480 },	// Inst #3782 = VST4q8Pseudo_UPD
	{ 10, OperandInfo497 }, // Inst #3783 = VST4q8_UPD
	{ 5, OperandInfo479 },	// Inst #3784 = VST4q8oddPseudo
	{ 7, OperandInfo480 },	// Inst #3785 = VST4q8oddPseudo_UPD
	{ 5, OperandInfo66 },	// Inst #3786 = VSTMDDB_UPD
	{ 4, OperandInfo206 },	// Inst #3787 = VSTMDIA
	{ 5, OperandInfo66 },	// Inst #3788 = VSTMDIA_UPD
	{ 4, OperandInfo423 },	// Inst #3789 = VSTMQIA
	{ 5, OperandInfo66 },	// Inst #3790 = VSTMSDB_UPD
	{ 4, OperandInfo206 },	// Inst #3791 = VSTMSIA
	{ 5, OperandInfo66 },	// Inst #3792 = VSTMSIA_UPD
	{ 5, OperandInfo99 },	// Inst #3793 = VSTRD
	{ 5, OperandInfo424 },	// Inst #3794 = VSTRH
	{ 5, OperandInfo425 },	// Inst #3795 = VSTRS
	{ 4, OperandInfo426 },	// Inst #3796 = VSTR_FPCXTNS_off
	{ 5, OperandInfo427 },	// Inst #3797 = VSTR_FPCXTNS_post
	{ 5, OperandInfo427 },	// Inst #3798 = VSTR_FPCXTNS_pre
	{ 4, OperandInfo426 },	// Inst #3799 = VSTR_FPCXTS_off
	{ 5, OperandInfo427 },	// Inst #3800 = VSTR_FPCXTS_post
	{ 5, OperandInfo427 },	// Inst #3801 = VSTR_FPCXTS_pre
	{ 4, OperandInfo426 },	// Inst #3802 = VSTR_FPSCR_NZCVQC_off
	{ 5, OperandInfo427 },	// Inst #3803 = VSTR_FPSCR_NZCVQC_post
	{ 5, OperandInfo427 },	// Inst #3804 = VSTR_FPSCR_NZCVQC_pre
	{ 4, OperandInfo426 },	// Inst #3805 = VSTR_FPSCR_off
	{ 5, OperandInfo427 },	// Inst #3806 = VSTR_FPSCR_post
	{ 5, OperandInfo427 },	// Inst #3807 = VSTR_FPSCR_pre
	{ 5, OperandInfo428 },	// Inst #3808 = VSTR_P0_off
	{ 6, OperandInfo498 },	// Inst #3809 = VSTR_P0_post
	{ 6, OperandInfo498 },	// Inst #3810 = VSTR_P0_pre
	{ 4, OperandInfo426 },	// Inst #3811 = VSTR_VPR_off
	{ 5, OperandInfo427 },	// Inst #3812 = VSTR_VPR_post
	{ 5, OperandInfo427 },	// Inst #3813 = VSTR_VPR_pre
	{ 5, OperandInfo340 },	// Inst #3814 = VSUBD
	{ 5, OperandInfo346 },	// Inst #3815 = VSUBH
	{ 5, OperandInfo347 },	// Inst #3816 = VSUBHNv2i32
	{ 5, OperandInfo347 },	// Inst #3817 = VSUBHNv4i16
	{ 5, OperandInfo347 },	// Inst #3818 = VSUBHNv8i8
	{ 5, OperandInfo339 },	// Inst #3819 = VSUBLsv2i64
	{ 5, OperandInfo339 },	// Inst #3820 = VSUBLsv4i32
	{ 5, OperandInfo339 },	// Inst #3821 = VSUBLsv8i16
	{ 5, OperandInfo339 },	// Inst #3822 = VSUBLuv2i64
	{ 5, OperandInfo339 },	// Inst #3823 = VSUBLuv4i32
	{ 5, OperandInfo339 },	// Inst #3824 = VSUBLuv8i16
	{ 5, OperandInfo348 },	// Inst #3825 = VSUBS
	{ 5, OperandInfo349 },	// Inst #3826 = VSUBWsv2i64
	{ 5, OperandInfo349 },	// Inst #3827 = VSUBWsv4i32
	{ 5, OperandInfo349 },	// Inst #3828 = VSUBWsv8i16
	{ 5, OperandInfo349 },	// Inst #3829 = VSUBWuv2i64
	{ 5, OperandInfo349 },	// Inst #3830 = VSUBWuv4i32
	{ 5, OperandInfo349 },	// Inst #3831 = VSUBWuv8i16
	{ 5, OperandInfo340 },	// Inst #3832 = VSUBfd
	{ 5, OperandInfo341 },	// Inst #3833 = VSUBfq
	{ 5, OperandInfo340 },	// Inst #3834 = VSUBhd
	{ 5, OperandInfo341 },	// Inst #3835 = VSUBhq
	{ 5, OperandInfo341 },	// Inst #3836 = VSUBv16i8
	{ 5, OperandInfo340 },	// Inst #3837 = VSUBv1i64
	{ 5, OperandInfo340 },	// Inst #3838 = VSUBv2i32
	{ 5, OperandInfo341 },	// Inst #3839 = VSUBv2i64
	{ 5, OperandInfo340 },	// Inst #3840 = VSUBv4i16
	{ 5, OperandInfo341 },	// Inst #3841 = VSUBv4i32
	{ 5, OperandInfo341 },	// Inst #3842 = VSUBv8i16
	{ 5, OperandInfo340 },	// Inst #3843 = VSUBv8i8
	{ 5, OperandInfo159 },	// Inst #3844 = VSUDOTDI
	{ 5, OperandInfo160 },	// Inst #3845 = VSUDOTQI
	{ 6, OperandInfo499 },	// Inst #3846 = VSWPd
	{ 6, OperandInfo500 },	// Inst #3847 = VSWPq
	{ 5, OperandInfo340 },	// Inst #3848 = VTBL1
	{ 5, OperandInfo501 },	// Inst #3849 = VTBL2
	{ 5, OperandInfo340 },	// Inst #3850 = VTBL3
	{ 5, OperandInfo502 },	// Inst #3851 = VTBL3Pseudo
	{ 5, OperandInfo340 },	// Inst #3852 = VTBL4
	{ 5, OperandInfo502 },	// Inst #3853 = VTBL4Pseudo
	{ 6, OperandInfo338 },	// Inst #3854 = VTBX1
	{ 6, OperandInfo503 },	// Inst #3855 = VTBX2
	{ 6, OperandInfo338 },	// Inst #3856 = VTBX3
	{ 6, OperandInfo504 },	// Inst #3857 = VTBX3Pseudo
	{ 6, OperandInfo338 },	// Inst #3858 = VTBX4
	{ 6, OperandInfo504 },	// Inst #3859 = VTBX4Pseudo
	{ 5, OperandInfo463 },	// Inst #3860 = VTOSHD
	{ 5, OperandInfo464 },	// Inst #3861 = VTOSHH
	{ 5, OperandInfo464 },	// Inst #3862 = VTOSHS
	{ 4, OperandInfo372 },	// Inst #3863 = VTOSIRD
	{ 4, OperandInfo344 },	// Inst #3864 = VTOSIRH
	{ 4, OperandInfo344 },	// Inst #3865 = VTOSIRS
	{ 4, OperandInfo372 },	// Inst #3866 = VTOSIZD
	{ 4, OperandInfo505 },	// Inst #3867 = VTOSIZH
	{ 4, OperandInfo344 },	// Inst #3868 = VTOSIZS
	{ 5, OperandInfo463 },	// Inst #3869 = VTOSLD
	{ 5, OperandInfo464 },	// Inst #3870 = VTOSLH
	{ 5, OperandInfo464 },	// Inst #3871 = VTOSLS
	{ 5, OperandInfo463 },	// Inst #3872 = VTOUHD
	{ 5, OperandInfo464 },	// Inst #3873 = VTOUHH
	{ 5, OperandInfo464 },	// Inst #3874 = VTOUHS
	{ 4, OperandInfo372 },	// Inst #3875 = VTOUIRD
	{ 4, OperandInfo344 },	// Inst #3876 = VTOUIRH
	{ 4, OperandInfo344 },	// Inst #3877 = VTOUIRS
	{ 4, OperandInfo372 },	// Inst #3878 = VTOUIZD
	{ 4, OperandInfo505 },	// Inst #3879 = VTOUIZH
	{ 4, OperandInfo344 },	// Inst #3880 = VTOUIZS
	{ 5, OperandInfo463 },	// Inst #3881 = VTOULD
	{ 5, OperandInfo464 },	// Inst #3882 = VTOULH
	{ 5, OperandInfo464 },	// Inst #3883 = VTOULS
	{ 6, OperandInfo499 },	// Inst #3884 = VTRNd16
	{ 6, OperandInfo499 },	// Inst #3885 = VTRNd32
	{ 6, OperandInfo499 },	// Inst #3886 = VTRNd8
	{ 6, OperandInfo500 },	// Inst #3887 = VTRNq16
	{ 6, OperandInfo500 },	// Inst #3888 = VTRNq32
	{ 6, OperandInfo500 },	// Inst #3889 = VTRNq8
	{ 5, OperandInfo341 },	// Inst #3890 = VTSTv16i8
	{ 5, OperandInfo340 },	// Inst #3891 = VTSTv2i32
	{ 5, OperandInfo340 },	// Inst #3892 = VTSTv4i16
	{ 5, OperandInfo341 },	// Inst #3893 = VTSTv4i32
	{ 5, OperandInfo341 },	// Inst #3894 = VTSTv8i16
	{ 5, OperandInfo340 },	// Inst #3895 = VTSTv8i8
	{ 4, OperandInfo161 },	// Inst #3896 = VUDOTD
	{ 5, OperandInfo159 },	// Inst #3897 = VUDOTDI
	{ 4, OperandInfo162 },	// Inst #3898 = VUDOTQ
	{ 5, OperandInfo160 },	// Inst #3899 = VUDOTQI
	{ 5, OperandInfo463 },	// Inst #3900 = VUHTOD
	{ 5, OperandInfo464 },	// Inst #3901 = VUHTOH
	{ 5, OperandInfo464 },	// Inst #3902 = VUHTOS
	{ 4, OperandInfo371 },	// Inst #3903 = VUITOD
	{ 4, OperandInfo465 },	// Inst #3904 = VUITOH
	{ 4, OperandInfo344 },	// Inst #3905 = VUITOS
	{ 5, OperandInfo463 },	// Inst #3906 = VULTOD
	{ 5, OperandInfo464 },	// Inst #3907 = VULTOH
	{ 5, OperandInfo464 },	// Inst #3908 = VULTOS
	{ 4, OperandInfo162 },	// Inst #3909 = VUMMLA
	{ 4, OperandInfo161 },	// Inst #3910 = VUSDOTD
	{ 5, OperandInfo159 },	// Inst #3911 = VUSDOTDI
	{ 4, OperandInfo162 },	// Inst #3912 = VUSDOTQ
	{ 5, OperandInfo160 },	// Inst #3913 = VUSDOTQI
	{ 4, OperandInfo162 },	// Inst #3914 = VUSMMLA
	{ 6, OperandInfo499 },	// Inst #3915 = VUZPd16
	{ 6, OperandInfo499 },	// Inst #3916 = VUZPd8
	{ 6, OperandInfo500 },	// Inst #3917 = VUZPq16
	{ 6, OperandInfo500 },	// Inst #3918 = VUZPq32
	{ 6, OperandInfo500 },	// Inst #3919 = VUZPq8
	{ 6, OperandInfo499 },	// Inst #3920 = VZIPd16
	{ 6, OperandInfo499 },	// Inst #3921 = VZIPd8
	{ 6, OperandInfo500 },	// Inst #3922 = VZIPq16
	{ 6, OperandInfo500 },	// Inst #3923 = VZIPq32
	{ 6, OperandInfo500 },	// Inst #3924 = VZIPq8
	{ 4, OperandInfo206 },	// Inst #3925 = sysLDMDA
	{ 5, OperandInfo66 },	// Inst #3926 = sysLDMDA_UPD
	{ 4, OperandInfo206 },	// Inst #3927 = sysLDMDB
	{ 5, OperandInfo66 },	// Inst #3928 = sysLDMDB_UPD
	{ 4, OperandInfo206 },	// Inst #3929 = sysLDMIA
	{ 5, OperandInfo66 },	// Inst #3930 = sysLDMIA_UPD
	{ 4, OperandInfo206 },	// Inst #3931 = sysLDMIB
	{ 5, OperandInfo66 },	// Inst #3932 = sysLDMIB_UPD
	{ 4, OperandInfo206 },	// Inst #3933 = sysSTMDA
	{ 5, OperandInfo66 },	// Inst #3934 = sysSTMDA_UPD
	{ 4, OperandInfo206 },	// Inst #3935 = sysSTMDB
	{ 5, OperandInfo66 },	// Inst #3936 = sysSTMDB_UPD
	{ 4, OperandInfo206 },	// Inst #3937 = sysSTMIA
	{ 5, OperandInfo66 },	// Inst #3938 = sysSTMIA_UPD
	{ 4, OperandInfo206 },	// Inst #3939 = sysSTMIB
	{ 5, OperandInfo66 },	// Inst #3940 = sysSTMIB_UPD
	{ 6, OperandInfo506 },	// Inst #3941 = t2ADCri
	{ 6, OperandInfo507 },	// Inst #3942 = t2ADCrr
	{ 7, OperandInfo508 },	// Inst #3943 = t2ADCrs
	{ 6, OperandInfo509 },	// Inst #3944 = t2ADDri
	{ 5, OperandInfo510 },	// Inst #3945 = t2ADDri12
	{ 6, OperandInfo511 },	// Inst #3946 = t2ADDrr
	{ 7, OperandInfo512 },	// Inst #3947 = t2ADDrs
	{ 6, OperandInfo513 },	// Inst #3948 = t2ADDspImm
	{ 5, OperandInfo514 },	// Inst #3949 = t2ADDspImm12
	{ 4, OperandInfo515 },	// Inst #3950 = t2ADR
	{ 6, OperandInfo506 },	// Inst #3951 = t2ANDri
	{ 6, OperandInfo507 },	// Inst #3952 = t2ANDrr
	{ 7, OperandInfo508 },	// Inst #3953 = t2ANDrs
	{ 6, OperandInfo506 },	// Inst #3954 = t2ASRri
	{ 6, OperandInfo507 },	// Inst #3955 = t2ASRrr
	{ 0, 0 },		// Inst #3956 = t2AUT
	{ 5, OperandInfo516 },	// Inst #3957 = t2AUTG
	{ 3, OperandInfo141 },	// Inst #3958 = t2B
	{ 5, OperandInfo120 },	// Inst #3959 = t2BFC
	{ 6, OperandInfo517 },	// Inst #3960 = t2BFI
	{ 4, OperandInfo518 },	// Inst #3961 = t2BFLi
	{ 4, OperandInfo519 },	// Inst #3962 = t2BFLr
	{ 4, OperandInfo518 },	// Inst #3963 = t2BFi
	{ 4, OperandInfo520 },	// Inst #3964 = t2BFic
	{ 4, OperandInfo519 },	// Inst #3965 = t2BFr
	{ 6, OperandInfo506 },	// Inst #3966 = t2BICri
	{ 6, OperandInfo507 },	// Inst #3967 = t2BICrr
	{ 7, OperandInfo508 },	// Inst #3968 = t2BICrs
	{ 0, 0 },		// Inst #3969 = t2BTI
	{ 5, OperandInfo521 },	// Inst #3970 = t2BXAUT
	{ 3, OperandInfo239 },	// Inst #3971 = t2BXJ
	{ 3, OperandInfo141 },	// Inst #3972 = t2Bcc
	{ 8, OperandInfo195 },	// Inst #3973 = t2CDP
	{ 8, OperandInfo195 },	// Inst #3974 = t2CDP2
	{ 2, OperandInfo139 },	// Inst #3975 = t2CLREX
	{ 3, OperandInfo150 },	// Inst #3976 = t2CLRM
	{ 4, OperandInfo522 },	// Inst #3977 = t2CLZ
	{ 4, OperandInfo113 },	// Inst #3978 = t2CMNri
	{ 4, OperandInfo523 },	// Inst #3979 = t2CMNzrr
	{ 5, OperandInfo524 },	// Inst #3980 = t2CMNzrs
	{ 4, OperandInfo113 },	// Inst #3981 = t2CMPri
	{ 4, OperandInfo523 },	// Inst #3982 = t2CMPrr
	{ 5, OperandInfo524 },	// Inst #3983 = t2CMPrs
	{ 1, OperandInfo2 },	// Inst #3984 = t2CPS1p
	{ 2, OperandInfo7 },	// Inst #3985 = t2CPS2p
	{ 3, OperandInfo4 },	// Inst #3986 = t2CPS3p
	{ 3, OperandInfo85 },	// Inst #3987 = t2CRC32B
	{ 3, OperandInfo85 },	// Inst #3988 = t2CRC32CB
	{ 3, OperandInfo85 },	// Inst #3989 = t2CRC32CH
	{ 3, OperandInfo85 },	// Inst #3990 = t2CRC32CW
	{ 3, OperandInfo85 },	// Inst #3991 = t2CRC32H
	{ 3, OperandInfo85 },	// Inst #3992 = t2CRC32W
	{ 4, OperandInfo525 },	// Inst #3993 = t2CSEL
	{ 4, OperandInfo525 },	// Inst #3994 = t2CSINC
	{ 4, OperandInfo525 },	// Inst #3995 = t2CSINV
	{ 4, OperandInfo525 },	// Inst #3996 = t2CSNEG
	{ 3, OperandInfo202 },	// Inst #3997 = t2DBG
	{ 2, OperandInfo139 },	// Inst #3998 = t2DCPS1
	{ 2, OperandInfo139 },	// Inst #3999 = t2DCPS2
	{ 2, OperandInfo139 },	// Inst #4000 = t2DCPS3
	{ 2, OperandInfo111 },	// Inst #4001 = t2DLS
	{ 3, OperandInfo202 },	// Inst #4002 = t2DMB
	{ 3, OperandInfo202 },	// Inst #4003 = t2DSB
	{ 6, OperandInfo506 },	// Inst #4004 = t2EORri
	{ 6, OperandInfo507 },	// Inst #4005 = t2EORrr
	{ 7, OperandInfo508 },	// Inst #4006 = t2EORrs
	{ 3, OperandInfo202 },	// Inst #4007 = t2HINT
	{ 1, OperandInfo2 },	// Inst #4008 = t2HVC
	{ 3, OperandInfo202 },	// Inst #4009 = t2ISB
	{ 2, OperandInfo7 },	// Inst #4010 = t2IT
	{ 2, OperandInfo151 },	// Inst #4011 = t2Int_eh_sjlj_setjmp
	{ 2, OperandInfo151 },	// Inst #4012 = t2Int_eh_sjlj_setjmp_nofp
	{ 4, OperandInfo526 },	// Inst #4013 = t2LDA
	{ 4, OperandInfo526 },	// Inst #4014 = t2LDAB
	{ 4, OperandInfo526 },	// Inst #4015 = t2LDAEX
	{ 4, OperandInfo526 },	// Inst #4016 = t2LDAEXB
	{ 5, OperandInfo527 },	// Inst #4017 = t2LDAEXD
	{ 4, OperandInfo526 },	// Inst #4018 = t2LDAEXH
	{ 4, OperandInfo526 },	// Inst #4019 = t2LDAH
	{ 6, OperandInfo211 },	// Inst #4020 = t2LDC2L_OFFSET
	{ 6, OperandInfo212 },	// Inst #4021 = t2LDC2L_OPTION
	{ 6, OperandInfo211 },	// Inst #4022 = t2LDC2L_POST
	{ 7, OperandInfo213 },	// Inst #4023 = t2LDC2L_PRE
	{ 6, OperandInfo211 },	// Inst #4024 = t2LDC2_OFFSET
	{ 6, OperandInfo212 },	// Inst #4025 = t2LDC2_OPTION
	{ 6, OperandInfo211 },	// Inst #4026 = t2LDC2_POST
	{ 7, OperandInfo213 },	// Inst #4027 = t2LDC2_PRE
	{ 6, OperandInfo211 },	// Inst #4028 = t2LDCL_OFFSET
	{ 6, OperandInfo212 },	// Inst #4029 = t2LDCL_OPTION
	{ 6, OperandInfo211 },	// Inst #4030 = t2LDCL_POST
	{ 7, OperandInfo213 },	// Inst #4031 = t2LDCL_PRE
	{ 6, OperandInfo211 },	// Inst #4032 = t2LDC_OFFSET
	{ 6, OperandInfo212 },	// Inst #4033 = t2LDC_OPTION
	{ 6, OperandInfo211 },	// Inst #4034 = t2LDC_POST
	{ 7, OperandInfo213 },	// Inst #4035 = t2LDC_PRE
	{ 4, OperandInfo206 },	// Inst #4036 = t2LDMDB
	{ 5, OperandInfo66 },	// Inst #4037 = t2LDMDB_UPD
	{ 4, OperandInfo206 },	// Inst #4038 = t2LDMIA
	{ 5, OperandInfo66 },	// Inst #4039 = t2LDMIA_UPD
	{ 5, OperandInfo528 },	// Inst #4040 = t2LDRBT
	{ 6, OperandInfo215 },	// Inst #4041 = t2LDRB_POST
	{ 6, OperandInfo215 },	// Inst #4042 = t2LDRB_PRE
	{ 5, OperandInfo216 },	// Inst #4043 = t2LDRBi12
	{ 5, OperandInfo216 },	// Inst #4044 = t2LDRBi8
	{ 4, OperandInfo529 },	// Inst #4045 = t2LDRBpci
	{ 6, OperandInfo530 },	// Inst #4046 = t2LDRBs
	{ 7, OperandInfo531 },	// Inst #4047 = t2LDRD_POST
	{ 7, OperandInfo531 },	// Inst #4048 = t2LDRD_PRE
	{ 6, OperandInfo532 },	// Inst #4049 = t2LDRDi8
	{ 5, OperandInfo533 },	// Inst #4050 = t2LDREX
	{ 4, OperandInfo526 },	// Inst #4051 = t2LDREXB
	{ 5, OperandInfo527 },	// Inst #4052 = t2LDREXD
	{ 4, OperandInfo526 },	// Inst #4053 = t2LDREXH
	{ 5, OperandInfo528 },	// Inst #4054 = t2LDRHT
	{ 6, OperandInfo215 },	// Inst #4055 = t2LDRH_POST
	{ 6, OperandInfo215 },	// Inst #4056 = t2LDRH_PRE
	{ 5, OperandInfo216 },	// Inst #4057 = t2LDRHi12
	{ 5, OperandInfo216 },	// Inst #4058 = t2LDRHi8
	{ 4, OperandInfo529 },	// Inst #4059 = t2LDRHpci
	{ 6, OperandInfo530 },	// Inst #4060 = t2LDRHs
	{ 5, OperandInfo528 },	// Inst #4061 = t2LDRSBT
	{ 6, OperandInfo215 },	// Inst #4062 = t2LDRSB_POST
	{ 6, OperandInfo215 },	// Inst #4063 = t2LDRSB_PRE
	{ 5, OperandInfo216 },	// Inst #4064 = t2LDRSBi12
	{ 5, OperandInfo216 },	// Inst #4065 = t2LDRSBi8
	{ 4, OperandInfo529 },	// Inst #4066 = t2LDRSBpci
	{ 6, OperandInfo530 },	// Inst #4067 = t2LDRSBs
	{ 5, OperandInfo528 },	// Inst #4068 = t2LDRSHT
	{ 6, OperandInfo215 },	// Inst #4069 = t2LDRSH_POST
	{ 6, OperandInfo215 },	// Inst #4070 = t2LDRSH_PRE
	{ 5, OperandInfo216 },	// Inst #4071 = t2LDRSHi12
	{ 5, OperandInfo216 },	// Inst #4072 = t2LDRSHi8
	{ 4, OperandInfo529 },	// Inst #4073 = t2LDRSHpci
	{ 6, OperandInfo530 },	// Inst #4074 = t2LDRSHs
	{ 5, OperandInfo528 },	// Inst #4075 = t2LDRT
	{ 6, OperandInfo215 },	// Inst #4076 = t2LDR_POST
	{ 6, OperandInfo215 },	// Inst #4077 = t2LDR_PRE
	{ 5, OperandInfo87 },	// Inst #4078 = t2LDRi12
	{ 5, OperandInfo87 },	// Inst #4079 = t2LDRi8
	{ 4, OperandInfo534 },	// Inst #4080 = t2LDRpci
	{ 6, OperandInfo535 },	// Inst #4081 = t2LDRs
	{ 1, OperandInfo53 },	// Inst #4082 = t2LE
	{ 3, OperandInfo118 },	// Inst #4083 = t2LEUpdate
	{ 6, OperandInfo506 },	// Inst #4084 = t2LSLri
	{ 6, OperandInfo507 },	// Inst #4085 = t2LSLrr
	{ 6, OperandInfo506 },	// Inst #4086 = t2LSRri
	{ 6, OperandInfo507 },	// Inst #4087 = t2LSRrr
	{ 8, OperandInfo224 },	// Inst #4088 = t2MCR
	{ 8, OperandInfo224 },	// Inst #4089 = t2MCR2
	{ 7, OperandInfo536 },	// Inst #4090 = t2MCRR
	{ 7, OperandInfo536 },	// Inst #4091 = t2MCRR2
	{ 6, OperandInfo537 },	// Inst #4092 = t2MLA
	{ 6, OperandInfo537 },	// Inst #4093 = t2MLS
	{ 5, OperandInfo120 },	// Inst #4094 = t2MOVTi16
	{ 5, OperandInfo538 },	// Inst #4095 = t2MOVi
	{ 4, OperandInfo515 },	// Inst #4096 = t2MOVi16
	{ 5, OperandInfo539 },	// Inst #4097 = t2MOVr
	{ 4, OperandInfo522 },	// Inst #4098 = t2MOVsra_flag
	{ 4, OperandInfo522 },	// Inst #4099 = t2MOVsrl_flag
	{ 8, OperandInfo235 },	// Inst #4100 = t2MRC
	{ 8, OperandInfo235 },	// Inst #4101 = t2MRC2
	{ 7, OperandInfo540 },	// Inst #4102 = t2MRRC
	{ 7, OperandInfo540 },	// Inst #4103 = t2MRRC2
	{ 3, OperandInfo137 },	// Inst #4104 = t2MRS_AR
	{ 4, OperandInfo515 },	// Inst #4105 = t2MRS_M
	{ 4, OperandInfo515 },	// Inst #4106 = t2MRSbanked
	{ 3, OperandInfo137 },	// Inst #4107 = t2MRSsys_AR
	{ 4, OperandInfo541 },	// Inst #4108 = t2MSR_AR
	{ 4, OperandInfo541 },	// Inst #4109 = t2MSR_M
	{ 4, OperandInfo541 },	// Inst #4110 = t2MSRbanked
	{ 5, OperandInfo542 },	// Inst #4111 = t2MUL
	{ 5, OperandInfo538 },	// Inst #4112 = t2MVNi
	{ 5, OperandInfo543 },	// Inst #4113 = t2MVNr
	{ 6, OperandInfo544 },	// Inst #4114 = t2MVNs
	{ 6, OperandInfo506 },	// Inst #4115 = t2ORNri
	{ 6, OperandInfo507 },	// Inst #4116 = t2ORNrr
	{ 7, OperandInfo508 },	// Inst #4117 = t2ORNrs
	{ 6, OperandInfo506 },	// Inst #4118 = t2ORRri
	{ 6, OperandInfo507 },	// Inst #4119 = t2ORRrr
	{ 7, OperandInfo508 },	// Inst #4120 = t2ORRrs
	{ 0, 0 },		// Inst #4121 = t2PAC
	{ 0, 0 },		// Inst #4122 = t2PACBTI
	{ 5, OperandInfo545 },	// Inst #4123 = t2PACG
	{ 6, OperandInfo546 },	// Inst #4124 = t2PKHBT
	{ 6, OperandInfo546 },	// Inst #4125 = t2PKHTB
	{ 4, OperandInfo547 },	// Inst #4126 = t2PLDWi12
	{ 4, OperandInfo547 },	// Inst #4127 = t2PLDWi8
	{ 5, OperandInfo548 },	// Inst #4128 = t2PLDWs
	{ 4, OperandInfo547 },	// Inst #4129 = t2PLDi12
	{ 4, OperandInfo547 },	// Inst #4130 = t2PLDi8
	{ 3, OperandInfo549 },	// Inst #4131 = t2PLDpci
	{ 5, OperandInfo548 },	// Inst #4132 = t2PLDs
	{ 4, OperandInfo547 },	// Inst #4133 = t2PLIi12
	{ 4, OperandInfo547 },	// Inst #4134 = t2PLIi8
	{ 3, OperandInfo549 },	// Inst #4135 = t2PLIpci
	{ 5, OperandInfo548 },	// Inst #4136 = t2PLIs
	{ 5, OperandInfo542 },	// Inst #4137 = t2QADD
	{ 5, OperandInfo542 },	// Inst #4138 = t2QADD16
	{ 5, OperandInfo542 },	// Inst #4139 = t2QADD8
	{ 5, OperandInfo542 },	// Inst #4140 = t2QASX
	{ 5, OperandInfo542 },	// Inst #4141 = t2QDADD
	{ 5, OperandInfo542 },	// Inst #4142 = t2QDSUB
	{ 5, OperandInfo542 },	// Inst #4143 = t2QSAX
	{ 5, OperandInfo542 },	// Inst #4144 = t2QSUB
	{ 5, OperandInfo542 },	// Inst #4145 = t2QSUB16
	{ 5, OperandInfo542 },	// Inst #4146 = t2QSUB8
	{ 4, OperandInfo522 },	// Inst #4147 = t2RBIT
	{ 4, OperandInfo522 },	// Inst #4148 = t2REV
	{ 4, OperandInfo522 },	// Inst #4149 = t2REV16
	{ 4, OperandInfo522 },	// Inst #4150 = t2REVSH
	{ 3, OperandInfo137 },	// Inst #4151 = t2RFEDB
	{ 3, OperandInfo137 },	// Inst #4152 = t2RFEDBW
	{ 3, OperandInfo137 },	// Inst #4153 = t2RFEIA
	{ 3, OperandInfo137 },	// Inst #4154 = t2RFEIAW
	{ 6, OperandInfo506 },	// Inst #4155 = t2RORri
	{ 6, OperandInfo507 },	// Inst #4156 = t2RORrr
	{ 5, OperandInfo543 },	// Inst #4157 = t2RRX
	{ 6, OperandInfo506 },	// Inst #4158 = t2RSBri
	{ 6, OperandInfo507 },	// Inst #4159 = t2RSBrr
	{ 7, OperandInfo508 },	// Inst #4160 = t2RSBrs
	{ 5, OperandInfo542 },	// Inst #4161 = t2SADD16
	{ 5, OperandInfo542 },	// Inst #4162 = t2SADD8
	{ 5, OperandInfo542 },	// Inst #4163 = t2SASX
	{ 0, 0 },		// Inst #4164 = t2SB
	{ 6, OperandInfo506 },	// Inst #4165 = t2SBCri
	{ 6, OperandInfo507 },	// Inst #4166 = t2SBCrr
	{ 7, OperandInfo508 },	// Inst #4167 = t2SBCrs
	{ 6, OperandInfo550 },	// Inst #4168 = t2SBFX
	{ 5, OperandInfo542 },	// Inst #4169 = t2SDIV
	{ 5, OperandInfo47 },	// Inst #4170 = t2SEL
	{ 1, OperandInfo2 },	// Inst #4171 = t2SETPAN
	{ 2, OperandInfo139 },	// Inst #4172 = t2SG
	{ 5, OperandInfo542 },	// Inst #4173 = t2SHADD16
	{ 5, OperandInfo542 },	// Inst #4174 = t2SHADD8
	{ 5, OperandInfo542 },	// Inst #4175 = t2SHASX
	{ 5, OperandInfo542 },	// Inst #4176 = t2SHSAX
	{ 5, OperandInfo542 },	// Inst #4177 = t2SHSUB16
	{ 5, OperandInfo542 },	// Inst #4178 = t2SHSUB8
	{ 3, OperandInfo202 },	// Inst #4179 = t2SMC
	{ 6, OperandInfo537 },	// Inst #4180 = t2SMLABB
	{ 6, OperandInfo537 },	// Inst #4181 = t2SMLABT
	{ 6, OperandInfo537 },	// Inst #4182 = t2SMLAD
	{ 6, OperandInfo537 },	// Inst #4183 = t2SMLADX
	{ 8, OperandInfo551 },	// Inst #4184 = t2SMLAL
	{ 8, OperandInfo551 },	// Inst #4185 = t2SMLALBB
	{ 8, OperandInfo551 },	// Inst #4186 = t2SMLALBT
	{ 8, OperandInfo551 },	// Inst #4187 = t2SMLALD
	{ 8, OperandInfo551 },	// Inst #4188 = t2SMLALDX
	{ 8, OperandInfo551 },	// Inst #4189 = t2SMLALTB
	{ 8, OperandInfo551 },	// Inst #4190 = t2SMLALTT
	{ 6, OperandInfo537 },	// Inst #4191 = t2SMLATB
	{ 6, OperandInfo537 },	// Inst #4192 = t2SMLATT
	{ 6, OperandInfo537 },	// Inst #4193 = t2SMLAWB
	{ 6, OperandInfo537 },	// Inst #4194 = t2SMLAWT
	{ 6, OperandInfo537 },	// Inst #4195 = t2SMLSD
	{ 6, OperandInfo537 },	// Inst #4196 = t2SMLSDX
	{ 8, OperandInfo551 },	// Inst #4197 = t2SMLSLD
	{ 8, OperandInfo551 },	// Inst #4198 = t2SMLSLDX
	{ 6, OperandInfo537 },	// Inst #4199 = t2SMMLA
	{ 6, OperandInfo537 },	// Inst #4200 = t2SMMLAR
	{ 6, OperandInfo537 },	// Inst #4201 = t2SMMLS
	{ 6, OperandInfo537 },	// Inst #4202 = t2SMMLSR
	{ 5, OperandInfo542 },	// Inst #4203 = t2SMMUL
	{ 5, OperandInfo542 },	// Inst #4204 = t2SMMULR
	{ 5, OperandInfo542 },	// Inst #4205 = t2SMUAD
	{ 5, OperandInfo542 },	// Inst #4206 = t2SMUADX
	{ 5, OperandInfo542 },	// Inst #4207 = t2SMULBB
	{ 5, OperandInfo542 },	// Inst #4208 = t2SMULBT
	{ 6, OperandInfo537 },	// Inst #4209 = t2SMULL
	{ 5, OperandInfo542 },	// Inst #4210 = t2SMULTB
	{ 5, OperandInfo542 },	// Inst #4211 = t2SMULTT
	{ 5, OperandInfo542 },	// Inst #4212 = t2SMULWB
	{ 5, OperandInfo542 },	// Inst #4213 = t2SMULWT
	{ 5, OperandInfo542 },	// Inst #4214 = t2SMUSD
	{ 5, OperandInfo542 },	// Inst #4215 = t2SMUSDX
	{ 3, OperandInfo202 },	// Inst #4216 = t2SRSDB
	{ 3, OperandInfo202 },	// Inst #4217 = t2SRSDB_UPD
	{ 3, OperandInfo202 },	// Inst #4218 = t2SRSIA
	{ 3, OperandInfo202 },	// Inst #4219 = t2SRSIA_UPD
	{ 6, OperandInfo552 },	// Inst #4220 = t2SSAT
	{ 5, OperandInfo553 },	// Inst #4221 = t2SSAT16
	{ 5, OperandInfo542 },	// Inst #4222 = t2SSAX
	{ 5, OperandInfo542 },	// Inst #4223 = t2SSUB16
	{ 5, OperandInfo542 },	// Inst #4224 = t2SSUB8
	{ 6, OperandInfo211 },	// Inst #4225 = t2STC2L_OFFSET
	{ 6, OperandInfo212 },	// Inst #4226 = t2STC2L_OPTION
	{ 6, OperandInfo211 },	// Inst #4227 = t2STC2L_POST
	{ 7, OperandInfo213 },	// Inst #4228 = t2STC2L_PRE
	{ 6, OperandInfo211 },	// Inst #4229 = t2STC2_OFFSET
	{ 6, OperandInfo212 },	// Inst #4230 = t2STC2_OPTION
	{ 6, OperandInfo211 },	// Inst #4231 = t2STC2_POST
	{ 7, OperandInfo213 },	// Inst #4232 = t2STC2_PRE
	{ 6, OperandInfo211 },	// Inst #4233 = t2STCL_OFFSET
	{ 6, OperandInfo212 },	// Inst #4234 = t2STCL_OPTION
	{ 6, OperandInfo211 },	// Inst #4235 = t2STCL_POST
	{ 7, OperandInfo213 },	// Inst #4236 = t2STCL_PRE
	{ 6, OperandInfo211 },	// Inst #4237 = t2STC_OFFSET
	{ 6, OperandInfo212 },	// Inst #4238 = t2STC_OPTION
	{ 6, OperandInfo211 },	// Inst #4239 = t2STC_POST
	{ 7, OperandInfo213 },	// Inst #4240 = t2STC_PRE
	{ 4, OperandInfo526 },	// Inst #4241 = t2STL
	{ 4, OperandInfo526 },	// Inst #4242 = t2STLB
	{ 5, OperandInfo554 },	// Inst #4243 = t2STLEX
	{ 5, OperandInfo554 },	// Inst #4244 = t2STLEXB
	{ 6, OperandInfo555 },	// Inst #4245 = t2STLEXD
	{ 5, OperandInfo554 },	// Inst #4246 = t2STLEXH
	{ 4, OperandInfo526 },	// Inst #4247 = t2STLH
	{ 4, OperandInfo206 },	// Inst #4248 = t2STMDB
	{ 5, OperandInfo66 },	// Inst #4249 = t2STMDB_UPD
	{ 4, OperandInfo206 },	// Inst #4250 = t2STMIA
	{ 5, OperandInfo66 },	// Inst #4251 = t2STMIA_UPD
	{ 5, OperandInfo528 },	// Inst #4252 = t2STRBT
	{ 6, OperandInfo556 },	// Inst #4253 = t2STRB_POST
	{ 6, OperandInfo556 },	// Inst #4254 = t2STRB_PRE
	{ 5, OperandInfo528 },	// Inst #4255 = t2STRBi12
	{ 5, OperandInfo528 },	// Inst #4256 = t2STRBi8
	{ 6, OperandInfo557 },	// Inst #4257 = t2STRBs
	{ 7, OperandInfo558 },	// Inst #4258 = t2STRD_POST
	{ 7, OperandInfo558 },	// Inst #4259 = t2STRD_PRE
	{ 6, OperandInfo532 },	// Inst #4260 = t2STRDi8
	{ 6, OperandInfo559 },	// Inst #4261 = t2STREX
	{ 5, OperandInfo554 },	// Inst #4262 = t2STREXB
	{ 6, OperandInfo555 },	// Inst #4263 = t2STREXD
	{ 5, OperandInfo554 },	// Inst #4264 = t2STREXH
	{ 5, OperandInfo528 },	// Inst #4265 = t2STRHT
	{ 6, OperandInfo556 },	// Inst #4266 = t2STRH_POST
	{ 6, OperandInfo556 },	// Inst #4267 = t2STRH_PRE
	{ 5, OperandInfo528 },	// Inst #4268 = t2STRHi12
	{ 5, OperandInfo528 },	// Inst #4269 = t2STRHi8
	{ 6, OperandInfo557 },	// Inst #4270 = t2STRHs
	{ 5, OperandInfo528 },	// Inst #4271 = t2STRT
	{ 6, OperandInfo560 },	// Inst #4272 = t2STR_POST
	{ 6, OperandInfo560 },	// Inst #4273 = t2STR_PRE
	{ 5, OperandInfo87 },	// Inst #4274 = t2STRi12
	{ 5, OperandInfo87 },	// Inst #4275 = t2STRi8
	{ 6, OperandInfo535 },	// Inst #4276 = t2STRs
	{ 3, OperandInfo202 },	// Inst #4277 = t2SUBS_PC_LR
	{ 6, OperandInfo509 },	// Inst #4278 = t2SUBri
	{ 5, OperandInfo510 },	// Inst #4279 = t2SUBri12
	{ 6, OperandInfo511 },	// Inst #4280 = t2SUBrr
	{ 7, OperandInfo512 },	// Inst #4281 = t2SUBrs
	{ 6, OperandInfo513 },	// Inst #4282 = t2SUBspImm
	{ 5, OperandInfo514 },	// Inst #4283 = t2SUBspImm12
	{ 6, OperandInfo546 },	// Inst #4284 = t2SXTAB
	{ 6, OperandInfo546 },	// Inst #4285 = t2SXTAB16
	{ 6, OperandInfo546 },	// Inst #4286 = t2SXTAH
	{ 5, OperandInfo126 },	// Inst #4287 = t2SXTB
	{ 5, OperandInfo126 },	// Inst #4288 = t2SXTB16
	{ 5, OperandInfo126 },	// Inst #4289 = t2SXTH
	{ 4, OperandInfo561 },	// Inst #4290 = t2TBB
	{ 4, OperandInfo561 },	// Inst #4291 = t2TBH
	{ 4, OperandInfo515 },	// Inst #4292 = t2TEQri
	{ 4, OperandInfo522 },	// Inst #4293 = t2TEQrr
	{ 5, OperandInfo123 },	// Inst #4294 = t2TEQrs
	{ 3, OperandInfo202 },	// Inst #4295 = t2TSB
	{ 4, OperandInfo515 },	// Inst #4296 = t2TSTri
	{ 4, OperandInfo522 },	// Inst #4297 = t2TSTrr
	{ 5, OperandInfo123 },	// Inst #4298 = t2TSTrs
	{ 4, OperandInfo562 },	// Inst #4299 = t2TT
	{ 4, OperandInfo562 },	// Inst #4300 = t2TTA
	{ 4, OperandInfo562 },	// Inst #4301 = t2TTAT
	{ 4, OperandInfo562 },	// Inst #4302 = t2TTT
	{ 5, OperandInfo542 },	// Inst #4303 = t2UADD16
	{ 5, OperandInfo542 },	// Inst #4304 = t2UADD8
	{ 5, OperandInfo542 },	// Inst #4305 = t2UASX
	{ 6, OperandInfo550 },	// Inst #4306 = t2UBFX
	{ 1, OperandInfo2 },	// Inst #4307 = t2UDF
	{ 5, OperandInfo542 },	// Inst #4308 = t2UDIV
	{ 5, OperandInfo542 },	// Inst #4309 = t2UHADD16
	{ 5, OperandInfo542 },	// Inst #4310 = t2UHADD8
	{ 5, OperandInfo542 },	// Inst #4311 = t2UHASX
	{ 5, OperandInfo542 },	// Inst #4312 = t2UHSAX
	{ 5, OperandInfo542 },	// Inst #4313 = t2UHSUB16
	{ 5, OperandInfo542 },	// Inst #4314 = t2UHSUB8
	{ 8, OperandInfo551 },	// Inst #4315 = t2UMAAL
	{ 8, OperandInfo551 },	// Inst #4316 = t2UMLAL
	{ 6, OperandInfo537 },	// Inst #4317 = t2UMULL
	{ 5, OperandInfo542 },	// Inst #4318 = t2UQADD16
	{ 5, OperandInfo542 },	// Inst #4319 = t2UQADD8
	{ 5, OperandInfo542 },	// Inst #4320 = t2UQASX
	{ 5, OperandInfo542 },	// Inst #4321 = t2UQSAX
	{ 5, OperandInfo542 },	// Inst #4322 = t2UQSUB16
	{ 5, OperandInfo542 },	// Inst #4323 = t2UQSUB8
	{ 5, OperandInfo542 },	// Inst #4324 = t2USAD8
	{ 6, OperandInfo537 },	// Inst #4325 = t2USADA8
	{ 6, OperandInfo552 },	// Inst #4326 = t2USAT
	{ 5, OperandInfo553 },	// Inst #4327 = t2USAT16
	{ 5, OperandInfo542 },	// Inst #4328 = t2USAX
	{ 5, OperandInfo542 },	// Inst #4329 = t2USUB16
	{ 5, OperandInfo542 },	// Inst #4330 = t2USUB8
	{ 6, OperandInfo546 },	// Inst #4331 = t2UXTAB
	{ 6, OperandInfo546 },	// Inst #4332 = t2UXTAB16
	{ 6, OperandInfo546 },	// Inst #4333 = t2UXTAH
	{ 5, OperandInfo126 },	// Inst #4334 = t2UXTB
	{ 5, OperandInfo126 },	// Inst #4335 = t2UXTB16
	{ 5, OperandInfo126 },	// Inst #4336 = t2UXTH
	{ 3, OperandInfo129 },	// Inst #4337 = t2WLS
	{ 6, OperandInfo563 },	// Inst #4338 = tADC
	{ 5, OperandInfo75 },	// Inst #4339 = tADDhirr
	{ 6, OperandInfo564 },	// Inst #4340 = tADDi3
	{ 6, OperandInfo565 },	// Inst #4341 = tADDi8
	{ 5, OperandInfo566 },	// Inst #4342 = tADDrSP
	{ 5, OperandInfo567 },	// Inst #4343 = tADDrSPi
	{ 6, OperandInfo568 },	// Inst #4344 = tADDrr
	{ 5, OperandInfo569 },	// Inst #4345 = tADDspi
	{ 5, OperandInfo570 },	// Inst #4346 = tADDspr
	{ 4, OperandInfo571 },	// Inst #4347 = tADR
	{ 6, OperandInfo563 },	// Inst #4348 = tAND
	{ 6, OperandInfo564 },	// Inst #4349 = tASRri
	{ 6, OperandInfo563 },	// Inst #4350 = tASRrr
	{ 3, OperandInfo141 },	// Inst #4351 = tB
	{ 6, OperandInfo563 },	// Inst #4352 = tBIC
	{ 1, OperandInfo2 },	// Inst #4353 = tBKPT
	{ 3, OperandInfo110 },	// Inst #4354 = tBL
	{ 3, OperandInfo572 },	// Inst #4355 = tBLXNSr
	{ 3, OperandInfo110 },	// Inst #4356 = tBLXi
	{ 3, OperandInfo573 },	// Inst #4357 = tBLXr
	{ 3, OperandInfo137 },	// Inst #4358 = tBX
	{ 3, OperandInfo137 },	// Inst #4359 = tBXNS
	{ 3, OperandInfo141 },	// Inst #4360 = tBcc
	{ 2, OperandInfo574 },	// Inst #4361 = tCBNZ
	{ 2, OperandInfo574 },	// Inst #4362 = tCBZ
	{ 4, OperandInfo575 },	// Inst #4363 = tCMNz
	{ 4, OperandInfo197 },	// Inst #4364 = tCMPhir
	{ 4, OperandInfo145 },	// Inst #4365 = tCMPi8
	{ 4, OperandInfo575 },	// Inst #4366 = tCMPr
	{ 2, OperandInfo7 },	// Inst #4367 = tCPS
	{ 6, OperandInfo563 },	// Inst #4368 = tEOR
	{ 3, OperandInfo202 },	// Inst #4369 = tHINT
	{ 1, OperandInfo2 },	// Inst #4370 = tHLT
	{ 2, OperandInfo45 },	// Inst #4371 = tInt_WIN_eh_sjlj_longjmp
	{ 2, OperandInfo151 },	// Inst #4372 = tInt_eh_sjlj_longjmp
	{ 2, OperandInfo151 },	// Inst #4373 = tInt_eh_sjlj_setjmp
	{ 4, OperandInfo576 },	// Inst #4374 = tLDMIA
	{ 5, OperandInfo577 },	// Inst #4375 = tLDRBi
	{ 5, OperandInfo578 },	// Inst #4376 = tLDRBr
	{ 5, OperandInfo577 },	// Inst #4377 = tLDRHi
	{ 5, OperandInfo578 },	// Inst #4378 = tLDRHr
	{ 5, OperandInfo578 },	// Inst #4379 = tLDRSB
	{ 5, OperandInfo578 },	// Inst #4380 = tLDRSH
	{ 5, OperandInfo577 },	// Inst #4381 = tLDRi
	{ 4, OperandInfo579 },	// Inst #4382 = tLDRpci
	{ 5, OperandInfo578 },	// Inst #4383 = tLDRr
	{ 5, OperandInfo580 },	// Inst #4384 = tLDRspi
	{ 6, OperandInfo564 },	// Inst #4385 = tLSLri
	{ 6, OperandInfo563 },	// Inst #4386 = tLSLrr
	{ 6, OperandInfo564 },	// Inst #4387 = tLSRri
	{ 6, OperandInfo563 },	// Inst #4388 = tLSRrr
	{ 2, OperandInfo151 },	// Inst #4389 = tMOVSr
	{ 5, OperandInfo581 },	// Inst #4390 = tMOVi8
	{ 4, OperandInfo197 },	// Inst #4391 = tMOVr
	{ 6, OperandInfo582 },	// Inst #4392 = tMUL
	{ 5, OperandInfo583 },	// Inst #4393 = tMVN
	{ 6, OperandInfo563 },	// Inst #4394 = tORR
	{ 3, OperandInfo584 },	// Inst #4395 = tPICADD
	{ 3, OperandInfo150 },	// Inst #4396 = tPOP
	{ 3, OperandInfo150 },	// Inst #4397 = tPUSH
	{ 4, OperandInfo575 },	// Inst #4398 = tREV
	{ 4, OperandInfo575 },	// Inst #4399 = tREV16
	{ 4, OperandInfo575 },	// Inst #4400 = tREVSH
	{ 6, OperandInfo563 },	// Inst #4401 = tROR
	{ 5, OperandInfo583 },	// Inst #4402 = tRSB
	{ 6, OperandInfo563 },	// Inst #4403 = tSBC
	{ 1, OperandInfo2 },	// Inst #4404 = tSETEND
	{ 5, OperandInfo144 },	// Inst #4405 = tSTMIA_UPD
	{ 5, OperandInfo577 },	// Inst #4406 = tSTRBi
	{ 5, OperandInfo578 },	// Inst #4407 = tSTRBr
	{ 5, OperandInfo577 },	// Inst #4408 = tSTRHi
	{ 5, OperandInfo578 },	// Inst #4409 = tSTRHr
	{ 5, OperandInfo577 },	// Inst #4410 = tSTRi
	{ 5, OperandInfo578 },	// Inst #4411 = tSTRr
	{ 5, OperandInfo580 },	// Inst #4412 = tSTRspi
	{ 6, OperandInfo564 },	// Inst #4413 = tSUBi3
	{ 6, OperandInfo565 },	// Inst #4414 = tSUBi8
	{ 6, OperandInfo568 },	// Inst #4415 = tSUBrr
	{ 5, OperandInfo569 },	// Inst #4416 = tSUBspi
	{ 3, OperandInfo202 },	// Inst #4417 = tSVC
	{ 4, OperandInfo575 },	// Inst #4418 = tSXTB
	{ 4, OperandInfo575 },	// Inst #4419 = tSXTH
	{ 0, 0 },		// Inst #4420 = tTRAP
	{ 4, OperandInfo575 },	// Inst #4421 = tTST
	{ 1, OperandInfo2 },	// Inst #4422 = tUDF
	{ 4, OperandInfo575 },	// Inst #4423 = tUXTB
	{ 4, OperandInfo575 },	// Inst #4424 = tUXTH
	{ 0, 0 },		// Inst #4425 = t__brkdiv0
};

#endif				// GET_INSTRINFO_MC_DESC
