test_cases:
  -
    input:
      bytes: [ 0x86, 0x48, 0x60, 0xf4, 0x4d, 0x0f, 0xe2, 0xf4, 0xed, 0xff, 0xff, 0xeb, 0x04, 0xe0, 0x2d, 0xe5, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x83, 0x22, 0xe5, 0xf1, 0x02, 0x03, 0x0e, 0x00, 0x00, 0xa0, 0xe3, 0x02, 0x30, 0xc1, 0xe7, 0x00, 0x00, 0x53, 0xe3, 0x00, 0x02, 0x01, 0xf1, 0x05, 0x40, 0xd0, 0xe8, 0xf4, 0x80, 0x00, 0x00 ]
      arch: "arm"
      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
      address: 0x80001000
    expected:
      insns:
      -
        asm_text: "vld2.32 {d20, d21}, [r0], r6"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: d20
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: d21
                access: CS_AC_WRITE
              -
                type: ARM_OP_MEM
                mem_base: r0
                mem_index: r6
                access: CS_AC_READ_WRITE
            post_indexed: 1
            vector_size: 32
          writeback: 1
          regs_read: [ r0, r6 ]
          regs_write: [ r0, d20, d21 ]
      -
        asm_text: "vld4.16 {d16[], d17[], d18[], d19[]}, [r2]!"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: d16
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: d17
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: d18
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: d19
                access: CS_AC_WRITE
              -
                type: ARM_OP_MEM
                mem_base: r2
                access: CS_AC_READ_WRITE
            post_indexed: -1
            vector_size: 16
          writeback: 1
          regs_read: [ r2 ]
          regs_write: [ r2, d16, d17, d18, d19 ]
      -
        asm_text: "bl 0x80000fc4"
        details:
          arm:
            operands:
              -
                type: ARM_OP_IMM
                imm: 0x80000fc4
                access: CS_AC_READ
          regs_read: [ r13 ]
          regs_write: [ r14 ]
      -
        asm_text: "str lr, [sp, #-4]!"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r14
                access: CS_AC_READ
              -
                type: ARM_OP_MEM
                mem_base: r13
                mem_disp: 0x4
                access: CS_AC_WRITE
                subtracted: 1
            post_indexed: -1
          writeback: 1
          regs_read: [ r14, r13 ]
          regs_write: [ r13 ]
      -
        asm_text: "andeq r0, r0, r0"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r0
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: r0
                access: CS_AC_READ
              -
                type: ARM_OP_REG
                reg: r0
                access: CS_AC_READ
            cc: ARMCC_EQ
          regs_read: [ cpsr, r0 ]
          regs_write: [ r0 ]
      -
        asm_text: "str r8, [r2, #-0x3e0]!"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r8
                access: CS_AC_READ
              -
                type: ARM_OP_MEM
                mem_base: r2
                mem_disp: 0x3e0
                access: CS_AC_WRITE
                subtracted: 1
            post_indexed: -1
          writeback: 1
          regs_read: [ r8, r2 ]
          regs_write: [ r2 ]
      -
        asm_text: "mcreq p2, #0, r0, c3, c1, #7"
        details:
          arm:
            operands:
              -
                type: ARM_OP_PIMM
                imm: 2
                access: CS_AC_READ
              -
                type: ARM_OP_IMM
                imm: 0x0
                access: CS_AC_READ
              -
                type: ARM_OP_REG
                reg: r0
                access: CS_AC_READ
              -
                type: ARM_OP_CIMM
                imm: 3
                access: CS_AC_READ
              -
                type: ARM_OP_CIMM
                imm: 1
                access: CS_AC_READ
              -
                type: ARM_OP_IMM
                imm: 0x7
                access: CS_AC_READ
            cc: ARMCC_EQ
          regs_read: [ cpsr, r0 ]
      -
        asm_text: "mov r0, #0"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r0
                access: CS_AC_WRITE
              -
                type: ARM_OP_IMM
                imm: 0x0
                access: CS_AC_READ
          regs_write: [ r0 ]
      -
        asm_text: "strb r3, [r1, r2]"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r3
                access: CS_AC_READ
              -
                type: ARM_OP_MEM
                mem_base: r1
                mem_index: r2
                access: CS_AC_WRITE
          regs_read: [ r3, r1, r2 ]
      -
        asm_text: "cmp r3, #0"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r3
                access: CS_AC_READ
              -
                type: ARM_OP_IMM
                imm: 0x0
                access: CS_AC_READ
            update_flags: 1
          regs_read: [ r3 ]
          regs_write: [ cpsr ]
      -
        asm_text: "setend be"
        details:
          arm:
            operands:
              -
                type: ARM_OP_SETEND
                setend: ARM_SETEND_BE
      -
        asm_text: "ldm r0, {r0, r2, lr} ^"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r0
                access: CS_AC_READ
              -
                type: ARM_OP_REG
                reg: r0
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: r2
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: r14
                access: CS_AC_WRITE
          regs_read: [ r0 ]
          regs_write: [ r0, r2, r14 ]
      -
        asm_text: "strdeq r8, r9, [r0], -r4"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r8
                access: CS_AC_READ
              -
                type: ARM_OP_REG
                reg: r9
                access: CS_AC_READ
              -
                type: ARM_OP_MEM
                mem_base: r0
                mem_index: r4
                access: CS_AC_WRITE
                subtracted: 1
            cc: ARMCC_EQ
            post_indexed: 1
          writeback: 1
          regs_read: [ cpsr, r8, r9, r0, r4 ]
          regs_write: [ r0 ]

  -
    input:
      bytes: [ 0x60, 0xf9, 0x1f, 0x04, 0xe0, 0xf9, 0x4f, 0x07, 0x70, 0x47, 0x00, 0xf0, 0x10, 0xe8, 0xeb, 0x46, 0x83, 0xb0, 0xc9, 0x68, 0x1f, 0xb1, 0x30, 0xbf, 0xaf, 0xf3, 0x20, 0x84, 0x52, 0xf8, 0x23, 0xf0 ]
      arch: "arm"
      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
      address: 0x80001000
    expected:
      insns:
      -
        asm_text: "vld3.8 {d16, d17, d18}, [r0:0x40]"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: d16
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: d17
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: d18
                access: CS_AC_WRITE
              -
                type: ARM_OP_MEM
                mem_base: r0
                mem_align: 0x40
                access: CS_AC_READ
            vector_size: 8
          regs_read: [ r0 ]
          regs_write: [ d16, d17, d18 ]
      -
        asm_text: "vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0]"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: d16
                neon_lane: 1
                access: CS_AC_READ_WRITE
              -
                type: ARM_OP_REG
                reg: d17
                neon_lane: 1
                access: CS_AC_READ_WRITE
              -
                type: ARM_OP_REG
                reg: d18
                neon_lane: 1
                access: CS_AC_READ_WRITE
              -
                type: ARM_OP_REG
                reg: d19
                neon_lane: 1
                access: CS_AC_READ_WRITE
              -
                type: ARM_OP_MEM
                mem_base: r0
                access: CS_AC_READ
            vector_size: 16
          regs_read: [ d16, d17, d18, d19, r0 ]
          regs_write: [ d16, d17, d18, d19 ]
      -
        asm_text: "bx lr"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r14
                access: CS_AC_READ
          regs_read: [ r14 ]
      -
        asm_text: "blx 0x8000102c"
        details:
          arm:
            operands:
              -
                type: ARM_OP_IMM
                imm: 0x8000102c
                access: CS_AC_READ
          regs_read: [ r13 ]
          regs_write: [ r14 ]
      -
        asm_text: "mov r11, sp"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r11
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: r13
                access: CS_AC_READ
          regs_read: [ r13 ]
          regs_write: [ r11 ]
      -
        asm_text: "sub sp, #0xc"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r13
                access: CS_AC_READ_WRITE
              -
                type: ARM_OP_IMM
                imm: 0xc
                access: CS_AC_READ
            post_indexed: -1
          writeback: 1
          regs_read: [ r13 ]
          regs_write: [ r13 ]
      -
        asm_text: "ldr r1, [r1, #0xc]"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r1
                access: CS_AC_WRITE
              -
                type: ARM_OP_MEM
                mem_base: r1
                mem_disp: 0xc
                access: CS_AC_READ
          regs_read: [ r1 ]
          regs_write: [ r1 ]
      -
        asm_text: "cbz r7, 0x8000101e"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r7
                access: CS_AC_READ
              -
                type: ARM_OP_IMM
                imm: 0x8000101e
                access: CS_AC_READ
          regs_read: [ r7 ]
      -
        asm_text: "wfi"
      -
        asm_text: "cpsie.w f"
        details:
          arm:
            cps_mode: ARM_CPSMODE_IE
            cps_flag: ARM_CPSFLAG_F
      -
        asm_text: "ldr.w pc, [r2, r3, lsl #2]"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r15
                access: CS_AC_WRITE
              -
                type: ARM_OP_MEM
                mem_base: r2
                mem_index: r3
                shift_type: ARM_SFT_LSL
                shift_value: 2
          regs_read: [ r2, r3 ]
          regs_write: [ r15 ]

  -
    input:
      bytes: [ 0xd1, 0xe8, 0x00, 0xf0, 0xf0, 0x24, 0x04, 0x07, 0x1f, 0x3c, 0xf2, 0xc0, 0x00, 0x00, 0x4f, 0xf0, 0x00, 0x01, 0x46, 0x6c ]
      arch: "arm"
      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
      address: 0x80001000
    expected:
      insns:
      -
        asm_text: "tbb [r1, r0]"
        details:
          arm:
            operands:
              -
                type: ARM_OP_MEM
                mem_base: r1
                mem_index: r0
                access: CS_AC_READ
          regs_read: [ r1, r0 ]
      -
        asm_text: "movs r4, #0xf0"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r4
                access: CS_AC_WRITE
              -
                type: ARM_OP_IMM
                imm: 0xf0
                access: CS_AC_READ
            update_flags: 1
          regs_write: [ cpsr, r4 ]
      -
        asm_text: "lsls r4, r0, #0x1c"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r4
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: r0
                access: CS_AC_READ
              -
                type: ARM_OP_IMM
                imm: 0x1c
                access: CS_AC_READ
            update_flags: 1
          regs_read: [ r0 ]
          regs_write: [ cpsr, r4 ]
      -
        asm_text: "subs r4, #0x1f"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r4
                access: CS_AC_READ_WRITE
              -
                type: ARM_OP_IMM
                imm: 0x1f
                access: CS_AC_READ
            update_flags: 1
            post_indexed: -1
          writeback: 1
          regs_read: [ r4 ]
          regs_write: [ cpsr, r4 ]
      -
        asm_text: "stm r0!, {r1, r4, r5, r6, r7}"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r0
                access: CS_AC_READ_WRITE
              -
                type: ARM_OP_REG
                reg: r1
                access: CS_AC_READ
              -
                type: ARM_OP_REG
                reg: r4
                access: CS_AC_READ
              -
                type: ARM_OP_REG
                reg: r5
                access: CS_AC_READ
              -
                type: ARM_OP_REG
                reg: r6
                access: CS_AC_READ
              -
                type: ARM_OP_REG
                reg: r7
                access: CS_AC_READ
            post_indexed: -1
          writeback: 1
          regs_read: [ r0, r1, r4, r5, r6, r7 ]
          regs_write: [ r0 ]
      -
        asm_text: "movs r0, r0"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r0
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: r0
                access: CS_AC_READ
            update_flags: 1
          regs_read: [ r0 ]
          regs_write: [ cpsr, r0 ]
      -
        asm_text: "mov.w r1, #0"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r1
                access: CS_AC_WRITE
              -
                type: ARM_OP_IMM
                imm: 0x0
                access: CS_AC_READ
          regs_write: [ r1 ]
      -
        asm_text: "ldr r6, [r0, #0x44]"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r6
                access: CS_AC_WRITE
              -
                type: ARM_OP_MEM
                mem_base: r0
                mem_disp: 0x44
                access: CS_AC_READ
          regs_read: [ r0 ]
          regs_write: [ r6 ]

  -
    input:
      bytes: [ 0x4f, 0xf0, 0x00, 0x01, 0xbd, 0xe8, 0x00, 0x88, 0xd1, 0xe8, 0x00, 0xf0, 0x18, 0xbf, 0xad, 0xbf, 0xf3, 0xff, 0x0b, 0x0c, 0x86, 0xf3, 0x00, 0x89, 0x80, 0xf3, 0x00, 0x8c, 0x4f, 0xfa, 0x99, 0xf6, 0xd0, 0xff, 0xa2, 0x01 ]
      arch: "arm"
      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
      address: 0x80001000
    expected:
      insns:
      -
        asm_text: "mov.w r1, #0"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r1
                access: CS_AC_WRITE
              -
                type: ARM_OP_IMM
                imm: 0x0
                access: CS_AC_READ
          regs_write: [ r1 ]
      -
        asm_text: "pop.w {r11, pc}"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r11
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: r15
                access: CS_AC_WRITE
            post_indexed: -1
          writeback: 1
          regs_write: [ r11, r15 ]
      -
        asm_text: "tbb [r1, r0]"
        details:
          arm:
            operands:
              -
                type: ARM_OP_MEM
                mem_base: r1
                mem_index: r0
                access: CS_AC_READ
          regs_read: [ r1, r0 ]
      -
        asm_text: "it ne"
        details:
          arm:
            cc: ARMCC_NE
            pred_mask: 0x1
          regs_read: [ cpsr ]
          regs_write: [ itstate ]
      -
        asm_text: "iteet ge"
        details:
          arm:
            cc: ARMCC_GE
            pred_mask: 0xd
          regs_read: [ cpsr ]
          regs_write: [ itstate ]
      -
        asm_text: "vdupge.8 d16, d11[1]"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: d16
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: d11
                access: CS_AC_READ
                vector_index: 1
                vector_index_is_set: true
            cc: ARMCC_GE
            vector_size: 8
          regs_read: [ cpsr, d11 ]
          regs_write: [ d16 ]
      -
        asm_text: "msrlt cpsr_fc, r6"
        details:
          arm:
            operands:
              -
                type: ARM_OP_CPSR
                sys_psr_bits: [ ARM_FIELD_CPSR_C, ARM_FIELD_CPSR_C ]
                sys_msr_mask: 9
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: r6
                access: CS_AC_READ
            cc: ARMCC_LT
            update_flags: 1
          regs_read: [ cpsr, r6 ]
          regs_write: [ cpsr ]
      -
        asm_text: "msrlt apsr_nzcvqg, r0"
        details:
          arm:
            operands:
              -
                type: ARM_OP_SYSREG
                reg: apsr_nzcvqg
                sys_msr_mask: 12
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: r0
                access: CS_AC_READ
            cc: ARMCC_LT
            update_flags: 1
          regs_read: [ cpsr, r0 ]
          regs_write: [ cpsr ]
      -
        asm_text: "sxtbge.w r6, r9, ror #8"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r6
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: r9
                access: CS_AC_READ
                shift_type: ARM_SFT_ROR
                shift_value: 8
            cc: ARMCC_GE
          regs_read: [ cpsr, r9 ]
          regs_write: [ r6 ]
      -
        asm_text: "vaddw.u16 q8, q8, d18"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: q8
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: q8
                access: CS_AC_READ
              -
                type: ARM_OP_REG
                reg: d18
                access: CS_AC_READ
            vector_data: ARM_VECTORDATA_U16
          regs_read: [ q8, d18 ]
          regs_write: [ q8 ]

  -
    input:
      bytes: [ 0xef, 0xf3, 0x02, 0x80 ]
      arch: "arm"
      options: [ CS_MODE_THUMB, CS_MODE_MCLASS, CS_OPT_DETAIL ]
      address: 0x80001000
    expected:
      insns:
      -
        asm_text: "mrs r0, eapsr"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r0
                access: CS_AC_WRITE
              -
                type: ARM_OP_SYSREG
                reg: eapsr
                sys_msr_mask: 2
                access: CS_AC_READ
          regs_write: [ r0 ]

  -
    input:
      bytes: [ 0xe0, 0x3b, 0xb2, 0xee, 0x42, 0x00, 0x01, 0xe1, 0x51, 0xf0, 0x7f, 0xf5 ]
      arch: "arm"
      options: [ CS_MODE_ARM, CS_MODE_V8, CS_OPT_DETAIL ]
      address: 0x80001000
    expected:
      insns:
      -
        asm_text: "vcvtt.f64.f16 d3, s1"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: d3
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s1
                access: CS_AC_READ
            vector_data: ARM_VECTORDATA_F64F16
          regs_read: [ s1 ]
          regs_write: [ d3 ]
      -
        asm_text: "crc32b r0, r1, r2"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r0
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: r1
                access: CS_AC_READ
              -
                type: ARM_OP_REG
                reg: r2
                access: CS_AC_READ
          regs_read: [ r1, r2 ]
          regs_write: [ r0 ]
      -
        asm_text: "dmb oshld"
        details:
          arm:
            mem_barrier: ARM_MB_OSHLD
  -
    input:
      bytes: [ 0x90,0xe8,0x0e,0x00 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "ldm.w r0, {r1, r2, r3}"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r0
                access: CS_AC_READ
              -
                type: ARM_OP_REG
                reg: r1
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: r2
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: r3
                access: CS_AC_WRITE
          regs_read: [ r0 ]
          regs_write: [ r1, r2, r3 ]
          groups: [ IsThumb2 ]
  -
    input:
      bytes: [ 0x0e,0xc8 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "ldm r0!, {r1, r2, r3}"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r0
                access: CS_AC_READ_WRITE
              -
                type: ARM_OP_REG
                reg: r1
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: r2
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: r3
                access: CS_AC_WRITE
          writeback: 1
          regs_read: [ r0 ]
          regs_write: [ r0, r1, r2, r3 ]
          groups: [ IsThumb ]
  -
    input:
      bytes: [ 0x00,0x2a,0xf7,0xee ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "vmov.f32 s5, #1.000000e+00"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: s5
                access: CS_AC_WRITE
              -
                type: ARM_OP_FP
                fp: 1.0
          regs_write: [ s5 ]
          groups: [ HasVFP3 ]
  -
    input:
      bytes: [ 0x0f,0x00,0x71,0xe3 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "cmn r1, #0xf"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r1
                access: CS_AC_READ
              -
                type: ARM_OP_IMM
                imm: 0xf
                access: CS_AC_READ
            update_flags: 1
          regs_read: [ r1 ]
          regs_write: [ cpsr ]
          groups: [ IsARM ]
  -
    input:
      bytes: [ 0x03,0x20,0xb0,0xe1 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "movs r2, r3"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r2
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: r3
                access: CS_AC_READ
            update_flags: 1
          regs_read: [ r3 ]
          regs_write: [ cpsr, r2 ]
          groups: [ IsARM ]
  -
    input:
      bytes: [ 0xfd,0x8f ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "ldrh r5, [r7, #0x3e]"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r5
                access: CS_AC_WRITE
              -
                type: ARM_OP_MEM
                mem_base: r7
                mem_disp: 0x3e
                access: CS_AC_READ
          regs_read: [ r7 ]
          regs_write: [ r5 ]
          groups: [ IsThumb ]
  -
    input:
      bytes: [ 0x61,0xb6 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "cpsie f"
        details:
          arm:
            cps_mode: ARM_CPSMODE_IE
            cps_flag: ARM_CPSFLAG_F
          groups: [ IsThumb ]
  -
    input:
      bytes: [ 0x18,0xf8,0x03,0x1e ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "ldrbt r1, [r8, #3]"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r1
                access: CS_AC_WRITE
              -
                type: ARM_OP_MEM
                mem_base: r8
                mem_disp: 0x3
                access: CS_AC_READ
          regs_read: [ r8 ]
          regs_write: [ r1 ]
          groups: [ IsThumb2 ]
  -
    input:
      bytes: [ 0xb0,0xf8,0x01,0xf1 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "pldw [r0, #0x101]"
        details:
          arm:
            operands:
              -
                type: ARM_OP_MEM
                mem_base: r0
                mem_disp: 0x101
                access: CS_AC_READ
          regs_read: [ r0 ]
          groups: [ IsThumb2, HasV7, HasMP ]
  -
    input:
      bytes: [ 0xd3,0xe8,0x08,0xf0 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "tbb [r3, r8]"
        details:
          arm:
            operands:
              -
                type: ARM_OP_MEM
                mem_base: r3
                mem_index: r8
                access: CS_AC_READ
          regs_read: [ r3, r8 ]
          groups: [ jump, IsThumb2 ]
  -
    input:
      bytes: [ 0xd3,0xe8,0x18,0xf0 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "tbh [r3, r8, lsl #1]"
        details:
          arm:
            operands:
              -
                type: ARM_OP_MEM
                mem_base: r3
                mem_index: r8
                access: CS_AC_READ
                shift_type: ARM_SFT_LSL
                shift_value: 1
          regs_read: [ r3, r8 ]
          groups: [ jump, IsThumb2 ]
  -
    input:
      bytes: [ 0xaf,0xf3,0x43,0x85 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "cpsie i, #3"
        details:
          arm:
            operands:
              -
                type: ARM_OP_IMM
                imm: 0x3
                access: CS_AC_READ
            cps_mode: ARM_CPSMODE_IE
            cps_flag: ARM_CPSFLAG_I
          groups: [ IsThumb2, IsNotMClass ]
  -
    input:
      bytes: [ 0xbf,0xf3,0x6f,0x8f ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "isb sy"
        details:
          arm:
            mem_barrier: ARM_MB_SY
          groups: [ IsThumb, HasDB ]
  -
    input:
      bytes: [ 0x59,0xea,0x7b,0x89 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_MODE_V8, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "csel r9, r9, r11, vc"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r9
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: r9
                access: CS_AC_READ
              -
                type: ARM_OP_REG
                reg: r11
                access: CS_AC_READ
            cc: ARMCC_VC
          regs_read: [ cpsr, r9, r11 ]
          regs_write: [ r9 ]
          groups: [ HasV8_1MMainline ]
  -
    input:
      bytes: [ 0xbf,0xf3,0x56,0x8f ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "dmb nshst"
        details:
          arm:
            mem_barrier: ARM_MB_NSHST
          groups: [ IsThumb, HasDB ]
  -
    input:
      bytes: [ 0x31,0xfa,0x02,0xf2 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "lsrs.w r2, r1, r2"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r2
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: r1
                access: CS_AC_READ
              -
                type: ARM_OP_REG
                reg: r2
                access: CS_AC_READ
            update_flags: 1
          regs_read: [ r1, r2 ]
          regs_write: [ cpsr, r2 ]
          groups: [ IsThumb2 ]
  -
    input:
      bytes: [ 0x08,0xbf,0x5f,0xf0,0x0c,0x01 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "it eq"
        details:
          arm:
            cc: ARMCC_EQ
            pred_mask: 0x1
          regs_write: [ itstate ]
          groups: [ IsThumb2 ]
      -
        asm_text: "movseq.w r1, #0xc"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r1
                access: CS_AC_WRITE
              -
                type: ARM_OP_IMM
                imm: 0xc
                access: CS_AC_READ
            cc: ARMCC_EQ
            update_flags: 1
          regs_write: [ cpsr, r1 ]
          groups: [ IsThumb2 ]
  -
    input:
      bytes: [ 0x52,0xe8,0x01,0x1f ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "ldrex r1, [r2, #4]"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r1
                access: CS_AC_WRITE
              -
                type: ARM_OP_MEM
                mem_base: r2
                mem_disp: 0x4
                access: CS_AC_READ
          regs_read: [ r2 ]
          regs_write: [ r1 ]
          groups: [ IsThumb, HasV8MBaseline ]
  -
    input:
      bytes: [ 0x88,0xbf,0xdf,0xec,0x1d,0x1a ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_MODE_V8, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "it hi"
        details:
          arm:
            cc: ARMCC_HI
            pred_mask: 0x1
          groups: [ IsThumb2 ]
      -
        asm_text: "vscclrmhi {s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: s3
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s4
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s5
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s6
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s7
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s8
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s9
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s10
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s11
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s12
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s13
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s14
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s15
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s16
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s17
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s18
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s19
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s20
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s21
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s22
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s23
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s24
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s25
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s26
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s27
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s28
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s29
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s30
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: s31
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: vpr
                access: CS_AC_WRITE
            cc: ARMCC_HI
          regs_write: [ s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr ]
          groups: [ HasV8_1MMainline, Has8MSecExt ]
  -
    input:
      bytes: [ 0x9f,0xec,0x06,0x5b ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_MODE_V8, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "vscclrm {d5, d6, d7, vpr}"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: d5
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: d6
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: d7
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: vpr
                access: CS_AC_WRITE
          regs_write: [ d5, d6, d7, vpr ]
          groups: [ HasV8_1MMainline, Has8MSecExt ]
  -
    input:
      bytes: [ 0xbc,0xfd,0x7f,0xaf ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_MODE_V8, CS_MODE_MCLASS, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "vldrh.u32 q5, [r4, #0xfe]!"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: q5
                access: CS_AC_WRITE
              -
                type: ARM_OP_MEM
                mem_base: r4
                mem_disp: 0xfe
                access: CS_AC_READ
          writeback: 1
          regs_read: [ r4 ]
          regs_write: [ r4, q5 ]
          groups: [ HasMVEInt ]
  -
    input:
      bytes: [ 0x80,0xfc,0x80,0x1e ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_MODE_MCLASS, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "vst20.16 {q0, q1}, [r0]"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: q0
                access: CS_AC_READ
              -
                type: ARM_OP_REG
                reg: q1
                access: CS_AC_READ
              -
                type: ARM_OP_MEM
                mem_base: r0
                access: CS_AC_WRITE
          regs_read: [ q0, q1, r0 ]
          groups: [ HasMVEInt ]
  -
    input:
      bytes: [ 0x98,0xfc,0x4e,0x08 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_MODE_MCLASS, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "vcadd.f32 q0, q4, q7, #90"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: q0
                access: CS_AC_READ_WRITE
              -
                type: ARM_OP_REG
                reg: q4
                access: CS_AC_READ
              -
                type: ARM_OP_REG
                reg: q7
                access: CS_AC_READ
              -
                type: ARM_OP_IMM
                imm: 0x5a
                access: CS_AC_READ
          regs_read: [ q0, q4, q7 ]
          regs_write: [ q0 ]
          groups: [ HasMVEFloat ]
  -
    input:
      bytes: [ 0x94,0xfd,0x46,0x48 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_MODE_V8, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "vcadd.f32 q2, q2, q3, #270"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: q2
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: q2
                access: CS_AC_READ
              -
                type: ARM_OP_REG
                reg: q3
                access: CS_AC_READ
              -
                type: ARM_OP_IMM
                imm: 0x10e
                access: CS_AC_READ
          regs_read: [ q2, q3 ]
          regs_write: [ q2 ]
          groups: [ HasNEON, HasV8_3a ]
  -
    input:
      bytes: [ 0x9d,0xec,0x82,0x6e ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_MODE_MCLASS, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "vldrb.s16 q3, [sp, q1]"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: q3
                access: CS_AC_WRITE
              -
                type: ARM_OP_MEM
                mem_base: r13
                mem_index: q1
                access: CS_AC_READ
          regs_read: [ r13, q1 ]
          regs_write: [ q3 ]
          groups: [ HasMVEInt ]
  -
    input:
      bytes: [ 0x90,0xec,0x12,0x6f ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_MODE_MCLASS, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "vldrh.s32 q3, [r0, q1]"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: q3
                access: CS_AC_WRITE
              -
                type: ARM_OP_MEM
                mem_base: r0
                mem_index: q1
                access: CS_AC_READ
          regs_read: [ r0, q1 ]
          regs_write: [ q3 ]
          groups: [ HasMVEInt ]
  -
    input:
      bytes: [ 0x5f,0xea,0x2d,0x83 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_MODE_V8, CS_MODE_MCLASS, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "sqrshrl lr, r3, #0x40, r8"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r14
                access: CS_AC_READ_WRITE
              -
                type: ARM_OP_REG
                reg: r3
                access: CS_AC_READ_WRITE
              -
                type: ARM_OP_IMM
                imm: 0x40
                access: CS_AC_READ
              -
                type: ARM_OP_REG
                reg: r8
                access: CS_AC_READ
          writeback: 1
          regs_read: [ r14, r3, r8 ]
          regs_write: [ r14, r3 ]
          groups: [ HasV8_1MMainline, HasMVEInt ]
  -
    input:
      bytes: [ 0x82,0xfd,0x21,0xff ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_MODE_MCLASS, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "vstrd.64 q7, [q1, #0x108]"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: q7
                access: CS_AC_READ
              -
                type: ARM_OP_MEM
                mem_base: q1
                mem_disp: 0x108
                access: CS_AC_WRITE
          regs_read: [ q7, q1 ]
          groups: [ HasMVEInt ]
  -
    input:
      bytes: [ 0x06,0x16,0x72,0xe6 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "ldrbt r1, [r2], -r6, lsl #12"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r1
                access: CS_AC_WRITE
              -
                type: ARM_OP_MEM
                mem_base: r2
                mem_index: r6
                access: CS_AC_READ
                shift_type: ARM_SFT_LSL
                shift_value: 12
                subtracted: 1
          writeback: 1
          regs_read: [ r2, r6 ]
          regs_write: [ r2, r1 ]
          groups: [ IsARM ]
  -
    input:
      bytes: [ 0xf6,0x50,0x33,0xe1 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "ldrsh r5, [r3, -r6]!"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r5
                access: CS_AC_WRITE
              -
                type: ARM_OP_MEM
                mem_base: r3
                mem_index: r6
                access: CS_AC_READ
                subtracted: 1
          writeback: 1
          regs_read: [ r3, r6 ]
          regs_write: [ r3, r5 ]
          groups: [ IsARM ]
  -
    input:
      bytes: [ 0x1e,0x19,0x7a,0xfd ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "ldc2l p9, c1, [r10, #-0x78]!"
        details:
          arm:
            operands:
              -
                type: ARM_OP_PIMM
                imm: 9
                access: CS_AC_READ
              -
                type: ARM_OP_CIMM
                imm: 1
                access: CS_AC_READ
              -
                type: ARM_OP_MEM
                mem_base: r10
                mem_disp: 0x78
                access: CS_AC_READ
          regs_read: [ r10 ]
          regs_write: [ r10 ]
          groups: [ IsARM, PreV8 ]
  -
    input:
      bytes: [ 0x12,0x31,0x7c,0xfc ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "ldc2l p1, c3, [r12], #-0x48"
        details:
          arm:
            operands:
              -
                type: ARM_OP_PIMM
                imm: 1
                access: CS_AC_READ
              -
                type: ARM_OP_CIMM
                imm: 3
                access: CS_AC_READ
              -
                type: ARM_OP_MEM
                mem_base: r12
                access: CS_AC_READ
                mem_disp: 0x48
                subtracted: 1
          regs_read: [ r12 ]
          groups: [ IsARM, PreV8 ]
  -
    input:
      bytes: [ 0xa4,0xf9,0x6d,0x0e ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "vld3.16 {d0[], d2[], d4[]}, [r4]!"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: d0
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: d2
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: d4
                access: CS_AC_WRITE
              -
                type: ARM_OP_MEM
                mem_base: r4
                access: CS_AC_READ_WRITE
          writeback: 1
          regs_read: [ r4 ]
          regs_write: [ r4, d0, d2, d4 ]
  -
    input:
      bytes: [ 0x0d,0x50,0x66,0xe4 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "strbt r5, [r6], #-0xd"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r5
                access: CS_AC_READ
              -
                type: ARM_OP_MEM
                mem_base: r6
                access: CS_AC_WRITE
                mem_disp: 0xd
                subtracted: 1
          writeback: 1
          regs_read: [ r5, r6 ]
          regs_write: [ r6 ]
          groups: [ IsARM ]
  -
    input:
      bytes: [ 0x00,0x10,0x4f,0xe2 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "sub r1, pc, #0"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r1
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: r15
                access: CS_AC_READ
              -
                type: ARM_OP_IMM
                imm: 0x0
                access: CS_AC_READ
          regs_read: [ r15 ]
          regs_write: [ r1 ]
          groups: [ IsARM ]
  -
    input:
      bytes: [ 0x9f,0x51,0xd3,0xe7 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "bfc r5, #3, #0x11"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r5
                access: CS_AC_READ_WRITE
              -
                type: ARM_OP_IMM
                imm: 0x3
                access: CS_AC_READ
              -
                type: ARM_OP_IMM
                imm: 0x11
                access: CS_AC_READ
          writeback: 1
          regs_read: [ r5 ]
          regs_write: [ r5 ]
          groups: [ IsARM, HasV6T2 ]
  -
    input:
      bytes: [ 0xd8,0xe8,0xff,0x67 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "ldaexd r6, r7, [r8]"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r6
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: r7
                access: CS_AC_WRITE
              -
                type: ARM_OP_MEM
                mem_base: r8
                access: CS_AC_READ
          regs_read: [ r8 ]
          regs_write: [ r6, r7 ]
          groups: [ IsThumb, HasAcquireRelease, HasV7Clrex, IsNotMClass ]
  -
    input:
      bytes: [ 0x30,0x0f,0xa6,0xe6 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "ssat16 r0, #7, r0"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r0
                access: CS_AC_WRITE
              -
                type: ARM_OP_IMM
                imm: 0x7
                access: CS_AC_READ
              -
                type: ARM_OP_REG
                reg: r0
                access: CS_AC_READ
          regs_read: [ r0 ]
          regs_write: [ r0 ]
          groups: [ IsARM, HasV6 ]
  -
    input:
      bytes: [ 0x9a,0x8f,0xa0,0xe6 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "ssat r8, #1, r10, lsl #0x1f"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r8
                access: CS_AC_WRITE
              -
                type: ARM_OP_IMM
                imm: 0x1
                access: CS_AC_READ
              -
                type: ARM_OP_REG
                reg: r10
                access: CS_AC_READ
                shift_type: ARM_SFT_LSL
                shift_value: 31
          regs_read: [ r10 ]
          regs_write: [ r8 ]
          groups: [ IsARM, HasV6 ]
  -
    input:
      bytes: [ 0x40,0x1b,0xf5,0xee ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "vcmp.f64 d17, #0"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: d17
                access: CS_AC_READ
              -
                type: ARM_OP_IMM
                imm: 0x0
                access: CS_AC_READ
            update_flags: 1
          regs_read: [ d17 ]
          regs_write: [ fpscr_nzcv ]
          groups: [ HasVFP2, HasDPVFP ]
  -
    input:
      bytes: [ 0x05,0xf0,0x2f,0xe3 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "msr cpsr_fsxc, #5"
        details:
          arm:
            operands:
              -
                type: ARM_OP_CPSR
                sys_psr_bits: [ ARM_FIELD_CPSR_F, ARM_FIELD_CPSR_S, ARM_FIELD_CPSR_X, ARM_FIELD_CPSR_C ]
                sys_msr_mask: 0xf
                access: CS_AC_WRITE
              -
                type: ARM_OP_IMM
                imm: 0x5
                access: CS_AC_READ
            update_flags: 1
          regs_write: [ cpsr ]
          groups: [ IsARM ]
  -
    input:
      bytes: [ 0xa4,0xf9,0xed,0x0b ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:0x80]!"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: d0
                neon_lane: 1
                access: CS_AC_READ_WRITE
              -
                type: ARM_OP_REG
                reg: d2
                neon_lane: 1
                access: CS_AC_READ_WRITE
              -
                type: ARM_OP_REG
                reg: d4
                neon_lane: 1
                access: CS_AC_READ_WRITE
              -
                type: ARM_OP_REG
                reg: d6
                neon_lane: 1
                access: CS_AC_READ_WRITE
              -
                type: ARM_OP_MEM
                mem_base: r4
                mem_align: 0x80
                access: CS_AC_READ_WRITE
          writeback: 1
          regs_read: [ d0, d2, d4, d6, r4 ]
          regs_write: [ r4, d0, d2, d4, d6 ]
  -
    input:
      bytes: [ 0x42,0x03,0xb0,0xf3 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_ARM, CS_MODE_V8, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "aesd.8 q0, q1"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: q0
                access: CS_AC_READ_WRITE
              -
                type: ARM_OP_REG
                reg: q1
                access: CS_AC_READ
          writeback: 1
          regs_read: [ q0, q1 ]
          regs_write: [ q0 ]
          groups: [ HasV8, HasAES ]
  -
    input:
      bytes: [ 0x11,0x57,0x54,0xfc ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "mrrc2 p7, #1, r5, r4, c1"
        details:
          arm:
            operands:
              -
                type: ARM_OP_PIMM
                imm: 7
                access: CS_AC_READ
              -
                type: ARM_OP_IMM
                imm: 0x1
                access: CS_AC_READ
              -
                type: ARM_OP_REG
                reg: r5
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: r4
                access: CS_AC_WRITE
              -
                type: ARM_OP_CIMM
                imm: 1
                access: CS_AC_READ
          regs_write: [ r5, r4 ]
          groups: [ IsARM, PreV8 ]
  -
    input:
      bytes: [ 0xd3,0x2f,0x82,0xe6 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "pkhtb r2, r2, r3, asr #0x1f"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r2
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: r2
                access: CS_AC_READ
              -
                type: ARM_OP_REG
                reg: r3
                access: CS_AC_READ
                shift_type: ARM_SFT_ASR
                shift_value: 31
          regs_read: [ r2, r3 ]
          regs_write: [ r2 ]
          groups: [ IsARM, HasV6 ]
  -
    input:
      bytes: [ 0x93,0x27,0x82,0xe6 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "pkhbt r2, r2, r3, lsl #0xf"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r2
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: r2
                access: CS_AC_READ
              -
                type: ARM_OP_REG
                reg: r3
                access: CS_AC_READ
                shift_type: ARM_SFT_LSL
                shift_value: 15
          regs_read: [ r2, r3 ]
          regs_write: [ r2 ]
          groups: [ IsARM, HasV6 ]
  -
    input:
      bytes: [ 0xb4,0x10,0xf0,0xe0 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "ldrht r1, [r0], #4"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r1
                access: CS_AC_WRITE
              -
                type: ARM_OP_MEM
                mem_base: r0
                access: CS_AC_READ
                mem_disp: 0x4
          writeback: 1
          regs_read: [ r0 ]
          regs_write: [ r0, r1 ]
          groups: [ IsARM ]
  -
    input:
      bytes: [ 0x2f,0xfa,0xa1,0xf3 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "sxtb16 r3, r1, ror #16"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r3
                access: CS_AC_WRITE
              -
                type: ARM_OP_REG
                reg: r1
                access: CS_AC_READ
                shift_type: ARM_SFT_ROR
                shift_value: 16
          regs_read: [ r1 ]
          regs_write: [ r3 ]
          groups: [ HasDSP, IsThumb2 ]
  -
    input:
      bytes: [ 0x00,0x02,0x01,0xf1 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "setend be"
        details:
          arm:
            operands:
              -
                type: ARM_OP_SETEND
          groups: [ IsARM ]
  -
    input:
      bytes: [ 0xd0,0xe8,0xaf,0x0f ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "lda r0, [r0]"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r0
                access: CS_AC_WRITE
              -
                type: ARM_OP_MEM
                mem_base: r0
                access: CS_AC_READ
          regs_read: [ r0 ]
          regs_write: [ r0 ]
          groups: [ IsThumb, HasAcquireRelease ]
  -
    input:
      bytes: [ 0xef,0xf3,0x11,0x85 ]
      arch: "CS_ARCH_ARM"
      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
      address: 0x0
    expected:
      insns:
      -
        asm_text: "ldrhi pc, [r1, #-0x3ef]"
        details:
          arm:
            operands:
              -
                type: ARM_OP_REG
                reg: r15
                access: CS_AC_WRITE
              -
                type: ARM_OP_MEM
                mem_base: r1
                mem_disp: 0x3ef
                access: CS_AC_READ
            cc: ARMCC_HI
          regs_read: [ cpsr, r1 ]
          regs_write: [ r15 ]
          groups: [ IsARM, jump ]
