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Initial Commit
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Sajid
229
thirdparty/capstone/arch/TriCore/TriCoreMapping.c
vendored
Normal file
229
thirdparty/capstone/arch/TriCore/TriCoreMapping.c
vendored
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
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#ifdef CAPSTONE_HAS_TRICORE
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#include <stdio.h> // debug
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#include <string.h>
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#include <assert.h>
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#include "../../Mapping.h"
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#include "../../utils.h"
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#include "../../cs_simple_types.h"
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#include "TriCoreMapping.h"
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#include "TriCoreLinkage.h"
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#define GET_INSTRINFO_ENUM
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#include "TriCoreGenInstrInfo.inc"
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static const insn_map insns[] = {
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// dummy item
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{ 0,
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0,
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#ifndef CAPSTONE_DIET
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{ 0 },
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{ 0 },
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{ 0 },
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0,
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0
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#endif
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},
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#include "TriCoreGenCSMappingInsn.inc"
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};
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void TriCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
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{
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// Not used. Information is set after disassembly.
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}
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#ifndef CAPSTONE_DIET
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static const tricore_reg flag_regs[] = { TRICORE_REG_PSW };
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#endif // CAPSTONE_DIET
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static inline void check_updates_flags(MCInst *MI)
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{
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#ifndef CAPSTONE_DIET
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if (!MI->flat_insn->detail)
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return;
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cs_detail *detail = MI->flat_insn->detail;
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for (int i = 0; i < detail->regs_write_count; ++i) {
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if (detail->regs_write[i] == 0)
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return;
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for (int j = 0; j < ARR_SIZE(flag_regs); ++j) {
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if (detail->regs_write[i] == flag_regs[j]) {
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detail->tricore.update_flags = true;
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return;
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}
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}
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}
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#endif // CAPSTONE_DIET
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}
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void TriCore_set_instr_map_data(MCInst *MI)
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{
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map_cs_id(MI, insns, ARR_SIZE(insns));
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map_implicit_reads(MI, insns);
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map_implicit_writes(MI, insns);
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check_updates_flags(MI);
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map_groups(MI, insns);
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}
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#ifndef CAPSTONE_DIET
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static const char * const insn_names[] = {
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NULL,
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#include "TriCoreGenCSMappingInsnName.inc"
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};
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// special alias insn
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static const name_map alias_insn_names[] = { { 0, NULL } };
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#endif
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const char *TriCore_insn_name(csh handle, unsigned int id)
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{
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#ifndef CAPSTONE_DIET
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unsigned int i;
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if (id >= TRICORE_INS_ENDING)
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return NULL;
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// handle special alias first
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for (i = 0; i < ARR_SIZE(alias_insn_names); i++) {
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if (alias_insn_names[i].id == id)
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return alias_insn_names[i].name;
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}
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return insn_names[id];
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#else
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return NULL;
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#endif
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}
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#ifndef CAPSTONE_DIET
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static const name_map group_name_maps[] = {
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{ TRICORE_GRP_INVALID, NULL },
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{ TRICORE_GRP_CALL, "call" },
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{ TRICORE_GRP_JUMP, "jump" },
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};
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#endif
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const char *TriCore_group_name(csh handle, unsigned int id)
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{
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#ifndef CAPSTONE_DIET
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if (id >= TRICORE_GRP_ENDING)
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return NULL;
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return group_name_maps[id].name;
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#else
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return NULL;
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#endif
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}
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#ifndef CAPSTONE_DIET
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static const map_insn_ops insn_operands[] = {
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#include "TriCoreGenCSMappingInsnOp.inc"
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};
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#endif
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void TriCore_set_access(MCInst *MI)
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{
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#ifndef CAPSTONE_DIET
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if (!(MI->csh->detail_opt == CS_OPT_ON && MI->flat_insn->detail))
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return;
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assert(MI->Opcode < ARR_SIZE(insn_operands));
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cs_detail *detail = MI->flat_insn->detail;
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cs_tricore *tc = &(detail->tricore);
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for (int i = 0; i < tc->op_count; ++i) {
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cs_ac_type ac = map_get_op_access(MI, i);
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cs_tricore_op *op = &tc->operands[i];
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op->access = ac;
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cs_op_type op_type = map_get_op_type(MI, i);
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if (op_type != CS_OP_REG) {
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continue;
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}
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if (ac & CS_AC_READ) {
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detail->regs_read[detail->regs_read_count++] = op->reg;
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}
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if (ac & CS_AC_WRITE) {
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detail->regs_write[detail->regs_write_count++] =
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op->reg;
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}
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}
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#endif
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}
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void TriCore_reg_access(const cs_insn *insn, cs_regs regs_read,
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uint8_t *regs_read_count, cs_regs regs_write,
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uint8_t *regs_write_count)
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{
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#ifndef CAPSTONE_DIET
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uint8_t read_count, write_count;
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cs_detail *detail = insn->detail;
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read_count = detail->regs_read_count;
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write_count = detail->regs_write_count;
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// implicit registers
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memcpy(regs_read, detail->regs_read,
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read_count * sizeof(detail->regs_read[0]));
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memcpy(regs_write, detail->regs_write,
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write_count * sizeof(detail->regs_write[0]));
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// explicit registers
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cs_tricore *tc = &detail->tricore;
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for (uint8_t i = 0; i < tc->op_count; i++) {
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cs_tricore_op *op = &(tc->operands[i]);
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switch ((int)op->type) {
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case TRICORE_OP_REG:
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if ((op->access & CS_AC_READ) &&
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!arr_exist(regs_read, read_count, op->reg)) {
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regs_read[read_count] = (uint16_t)op->reg;
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read_count++;
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}
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if ((op->access & CS_AC_WRITE) &&
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!arr_exist(regs_write, write_count, op->reg)) {
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regs_write[write_count] = (uint16_t)op->reg;
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write_count++;
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}
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break;
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case TRICORE_OP_MEM:
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// registers appeared in memory references always being read
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if ((op->mem.base != ARM_REG_INVALID) &&
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!arr_exist(regs_read, read_count, op->mem.base)) {
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regs_read[read_count] = (uint16_t)op->mem.base;
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read_count++;
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}
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default:
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break;
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}
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}
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*regs_read_count = read_count;
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*regs_write_count = write_count;
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#endif
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}
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bool TriCore_getInstruction(csh handle, const uint8_t *Bytes, size_t ByteLen,
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MCInst *MI, uint16_t *Size, uint64_t Address,
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void *Info)
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{
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return TriCore_LLVM_getInstruction(handle, Bytes, ByteLen, MI, Size,
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Address, Info);
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}
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void TriCore_printInst(MCInst *MI, SStream *O, void *Info)
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{
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TriCore_LLVM_printInst(MI, MI->address, O);
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}
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const char *TriCore_getRegisterName(csh handle, unsigned int RegNo)
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{
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return TriCore_LLVM_getRegisterName(RegNo);
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}
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#endif // CAPSTONE_HAS_TRICORE
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