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Initial Commit
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Sajid
250
thirdparty/capstone/arch/XCore/XCoreInstPrinter.c
vendored
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250
thirdparty/capstone/arch/XCore/XCoreInstPrinter.c
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//===-- XCoreInstPrinter.cpp - Convert XCore MCInst to assembly syntax --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an XCore MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
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#ifdef CAPSTONE_HAS_XCORE
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#ifdef _MSC_VER
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#pragma warning(disable : 4996) // disable MSVC's warning on strcpy()
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#pragma warning(disable : 28719) // disable MSVC's warning on strcpy()
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#endif
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <capstone/platform.h>
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#include "XCoreInstPrinter.h"
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#include "../../MCInst.h"
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#include "../../utils.h"
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#include "../../SStream.h"
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#include "../../MCRegisterInfo.h"
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#include "../../MathExtras.h"
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#include "XCoreMapping.h"
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static const char *getRegisterName(unsigned RegNo);
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void XCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
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{
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/*
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if (((cs_struct *)ud)->detail != CS_OPT_ON)
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return;
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*/
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}
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// stw sed, sp[3]
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void XCore_insn_extract(MCInst *MI, const char *code)
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{
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int id;
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char *p, *p2;
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char tmp[128];
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strcpy(tmp, code); // safe because code is way shorter than 128 bytes
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// find the first space
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p = strchr(tmp, ' ');
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if (p) {
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p++;
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// find the next ','
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p2 = strchr(p, ',');
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if (p2) {
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*p2 = '\0';
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id = XCore_reg_id(p);
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if (id) {
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// register
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if (MI->csh->detail_opt) {
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG;
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id;
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MI->flat_insn->detail->xcore.op_count++;
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}
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}
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// next should be register, or memory?
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// skip space
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p2++;
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while(*p2 && *p2 == ' ')
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p2++;
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if (*p2) {
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// find '['
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p = p2;
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while(*p && *p != '[')
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p++;
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if (*p) {
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// this is '['
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*p = '\0';
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id = XCore_reg_id(p2);
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if (id) {
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// base register
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if (MI->csh->detail_opt) {
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM;
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)id;
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID;
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0;
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = 1;
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}
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p++;
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p2 = p;
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// until ']'
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while(*p && *p != ']')
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p++;
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if (*p) {
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*p = '\0';
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// p2 is either index, or disp
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id = XCore_reg_id(p2);
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if (id) {
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// index register
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if (MI->csh->detail_opt) {
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = (uint8_t)id;
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}
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} else {
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// a number means disp
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if (MI->csh->detail_opt) {
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = atoi(p2);
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}
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}
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}
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if (MI->csh->detail_opt) {
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MI->flat_insn->detail->xcore.op_count++;
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}
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}
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} else {
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// a register?
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id = XCore_reg_id(p2);
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if (id) {
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// register
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if (MI->csh->detail_opt) {
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG;
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id;
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MI->flat_insn->detail->xcore.op_count++;
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}
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}
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}
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}
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} else {
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id = XCore_reg_id(p);
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if (id) {
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// register
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if (MI->csh->detail_opt) {
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG;
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id;
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MI->flat_insn->detail->xcore.op_count++;
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}
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}
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}
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}
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}
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static void set_mem_access(MCInst *MI, bool status, int reg)
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{
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if (MI->csh->detail_opt != CS_OPT_ON)
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return;
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MI->csh->doing_mem = status;
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if (status) {
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if (reg != 0xffff && reg != -0xffff) {
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM;
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if (reg) {
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)reg;
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} else {
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = XCORE_REG_INVALID;
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}
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID;
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0;
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = 1;
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} else {
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// the last op should be the memory base
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MI->flat_insn->detail->xcore.op_count--;
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM;
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg;
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG_INVALID;
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0;
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if (reg > 0)
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = 1;
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else
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.direct = -1;
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}
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} else {
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if (reg) {
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = (uint8_t)reg;
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// done, create the next operand slot
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MI->flat_insn->detail->xcore.op_count++;
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}
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}
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}
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static void _printOperand(MCInst *MI, MCOperand *MO, SStream *O)
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{
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if (MCOperand_isReg(MO)) {
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unsigned reg;
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reg = MCOperand_getReg(MO);
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SStream_concat0(O, getRegisterName(reg));
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if (MI->csh->detail_opt) {
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if (MI->csh->doing_mem) {
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if (MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base == ARM_REG_INVALID)
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)reg;
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else
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = (uint8_t)reg;
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} else {
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG;
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = reg;
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MI->flat_insn->detail->xcore.op_count++;
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}
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}
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} else if (MCOperand_isImm(MO)) {
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int32_t Imm = (int32_t)MCOperand_getImm(MO);
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printInt32(O, Imm);
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if (MI->csh->detail_opt) {
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if (MI->csh->doing_mem) {
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = Imm;
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} else {
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_IMM;
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MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].imm = Imm;
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MI->flat_insn->detail->xcore.op_count++;
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}
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}
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}
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}
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static void printOperand(MCInst *MI, int OpNum, SStream *O)
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{
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if (OpNum >= MI->size)
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return;
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_printOperand(MI, MCInst_getOperand(MI, OpNum), O);
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}
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static void printInlineJT(MCInst *MI, int OpNum, SStream *O)
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{
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}
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static void printInlineJT32(MCInst *MI, int OpNum, SStream *O)
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{
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}
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#define PRINT_ALIAS_INSTR
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#include "XCoreGenAsmWriter.inc"
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void XCore_printInst(MCInst *MI, SStream *O, void *Info)
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{
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printInstruction(MI, O, Info);
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set_mem_access(MI, false, 0);
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}
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#endif
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